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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:11 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF Date: Fri, 14 Nov 2025 10:51:21 +0000 Message-ID: <20251114105201.107406-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it has 6 clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module clocks + 1 external clock) on T2H and has multiple resets. Add support for the hardware flow control. Signed-off-by: Biju Das --- v2->v3: * Dropped cpu_relax() from rsci_finish_console_write() and added a comment. * Added sci_is_rsci_fifo_type() helper for reuse in probe() and remove(). v1->v2: * Updated commit description. * Updated multiline comment to fit into single line. * Updated set_termios() for getting baud_rate() --- drivers/tty/serial/rsci.c | 282 ++++++++++++++++++++++++++++++++++-- drivers/tty/serial/rsci.h | 1 + drivers/tty/serial/sh-sci.c | 13 +- 3 files changed, 285 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 9609ef73a0d4..43b2e5588d4d 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -11,6 +11,8 @@ #include #include #include + +#include "serial_mctrl_gpio.h" #include "rsci.h" =20 MODULE_IMPORT_NS("SH_SCI"); @@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI"); #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ #define CCR1_CTSE BIT(0) /* CTS Enable */ =20 +/* CCR2 (Common Control Register 2) */ +#define CCR2_INIT 0xFF000004 +#define CCR2_CKS_TCLK (0) /* TCLK clock */ +#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ +#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ +#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ +#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ +#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Selec= t */ +#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ +#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select= */ + +/* CCR3 (Common Control Register 3) */ +#define CCR3_INIT 0x1203 +#define CCR3_BLK BIT(29) /* Block Transfer Mode */ +#define CCR3_GM BIT(28) /* GSM Mode */ +#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ +#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ +#define CCR3_DEN BIT(21) /* Driver Enabled */ +#define CCR3_FM BIT(20) /* FIFO Mode Select */ +#define CCR3_MP BIT(19) /* Multi-Processor Mode */ +#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ +#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */ +#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */ +#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */ +#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */ +#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Se= lect */ +#define CCR3_STP BIT(14) /* Stop bit Length */ +#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ +#define CCR3_LSBF BIT(12) /* LSB First select */ +#define CCR3_CHR1 BIT(9) /* Character Length */ +#define CCR3_CHR0 BIT(8) /* Character Length */ +#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ +#define CCR3_CPOL BIT(1) /* Clock Polarity Select */ +#define CCR3_CPHA BIT(0) /* Clock Phase Select */ + /* FCR (FIFO Control Register) */ #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ #define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ @@ -142,21 +179,160 @@ static void rsci_start_rx(struct uart_port *port) rsci_serial_out(port, CCR0, ctrl); } =20 +static void rsci_enable_ms(struct uart_port *port) +{ + mctrl_gpio_enable_ms(to_sci_port(port)->gpios); +} + +static void rsci_init_pins(struct uart_port *port, unsigned int cflag) +{ + struct sci_port *s =3D to_sci_port(port); + + /* Use port-specific handler if provided */ + if (s->cfg->ops && s->cfg->ops->init_pins) { + s->cfg->ops->init_pins(port, cflag); + return; + } + + if (!s->has_rtscts) + return; + + if (s->autorts) + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | + CCR1_CTSE | CCR1_CTSPEN); +} + +static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) +{ + unsigned int bits; + + if (rx_trig >=3D port->fifosize) + rx_trig =3D port->fifosize - 1; + else if (rx_trig < 1) + rx_trig =3D 1; + + bits =3D rx_trig << 16; + rsci_serial_out(port, FCR, (rsci_serial_in(port, FCR) & ~FCR_RTRG4_0) | b= its); + + return rx_trig; +} + static void rsci_set_termios(struct uart_port *port, struct ktermios *term= ios, const struct ktermios *old) { + unsigned int ccr2_val =3D CCR2_INIT, ccr3_val =3D CCR3_INIT; + unsigned int ccr0_val =3D 0, ccr1_val =3D 0, ccr4_val =3D 0; + unsigned int brr1 =3D 255, cks1 =3D 0, srr1 =3D 15; struct sci_port *s =3D to_sci_port(port); + unsigned int brr =3D 255, cks =3D 0; + int min_err =3D INT_MAX, err; + unsigned long max_freq =3D 0; + unsigned int baud, i; unsigned long flags; + unsigned int ctrl; + int best_clk =3D -1; + + if ((termios->c_cflag & CSIZE) =3D=3D CS7) { + ccr3_val |=3D CCR3_CHR0; + } else { + termios->c_cflag &=3D ~CSIZE; + termios->c_cflag |=3D CS8; + } + + if (termios->c_cflag & PARENB) + ccr1_val |=3D CCR1_PE; + + if (termios->c_cflag & PARODD) + ccr1_val |=3D (CCR1_PE | CCR1_PM); + + if (termios->c_cflag & CSTOPB) + ccr3_val |=3D CCR3_STP; + + /* Enable noise filter function */ + ccr1_val |=3D CCR1_NFEN; + + /* + * earlyprintk comes here early on with port->uartclk set to zero. + * the clock framework is not up and running at this point so here + * we assume that 115200 is the maximum baud rate. please note that + * the baud rate is not programmed during earlyprintk - it is assumed + * that the previous boot loader has enabled required clocks and + * setup the baud rate generator hardware for us already. + */ + if (!port->uartclk) { + max_freq =3D 115200; + } else { + for (i =3D 0; i < SCI_NUM_CLKS; i++) + max_freq =3D max(max_freq, s->clk_rates[i]); + + max_freq /=3D min_sr(s); + } + + baud =3D uart_get_baud_rate(port, termios, old, 0, max_freq); + if (!baud) + goto done; + + /* Divided Functional Clock using standard Bit Rate Register */ + err =3D sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); + if (abs(err) < abs(min_err)) { + best_clk =3D SCI_FCK; + ccr0_val =3D 0; + min_err =3D err; + brr =3D brr1; + cks =3D cks1; + } + +done: + if (best_clk >=3D 0) + dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", + s->clks[best_clk], baud, min_err); =20 sci_port_enable(s); uart_port_lock_irqsave(port, &flags); =20 - /* For now, only RX enabling is supported */ - if (termios->c_cflag & CREAD) + uart_update_timeout(port, termios->c_cflag, baud); + + rsci_serial_out(port, CCR0, ccr0_val); + + ccr3_val |=3D CCR3_FM; + rsci_serial_out(port, CCR3, ccr3_val); + + ccr2_val |=3D (cks << 20) | (brr << 8); + rsci_serial_out(port, CCR2, ccr2_val); + + rsci_serial_out(port, CCR1, ccr1_val); + rsci_serial_out(port, CCR4, ccr4_val); + + ctrl =3D rsci_serial_in(port, FCR); + ctrl |=3D (FCR_RFRST | FCR_TFRST); + rsci_serial_out(port, FCR, ctrl); + + if (s->rx_trigger > 1) + rsci_scif_set_rtrg(port, s->rx_trigger); + + port->status &=3D ~UPSTAT_AUTOCTS; + s->autorts =3D false; + + if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) { + port->status |=3D UPSTAT_AUTOCTS; + s->autorts =3D true; + } + + rsci_init_pins(port, termios->c_cflag); + rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); + rsci_serial_out(port, FFCLR, FFCLR_DRC); + + ccr0_val |=3D CCR0_RE; + rsci_serial_out(port, CCR0, ccr0_val); + + if ((termios->c_cflag & CREAD) !=3D 0) rsci_start_rx(port); =20 uart_port_unlock_irqrestore(port, flags); sci_port_disable(s); + + if (UART_ENABLE_MS(port, termios->c_cflag)) + rsci_enable_ms(port); } =20 static int rsci_txfill(struct uart_port *port) @@ -181,13 +357,34 @@ static unsigned int rsci_tx_empty(struct uart_port *p= ort) =20 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) { - /* Not supported yet */ + if (mctrl & TIOCM_LOOP) { + /* Standard loopback mode */ + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); + } } =20 static unsigned int rsci_get_mctrl(struct uart_port *port) { - /* Not supported yet */ - return 0; + struct sci_port *s =3D to_sci_port(port); + struct mctrl_gpios *gpios =3D s->gpios; + unsigned int mctrl =3D 0; + + mctrl_gpio_get(gpios, &mctrl); + + /* + * CTS/RTS is handled in hardware when supported, while nothing + * else is wired up. + */ + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) + mctrl |=3D TIOCM_CTS; + + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) + mctrl |=3D TIOCM_DSR; + + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) + mctrl |=3D TIOCM_CAR; + + return mctrl; } =20 static void rsci_start_tx(struct uart_port *port) @@ -312,7 +509,8 @@ static void rsci_receive_chars(struct uart_port *port) continue; } =20 - /* Store data and status. + /* + * Store data and status. * Non FIFO mode is not supported */ if (rdat & RDR_FFER) { @@ -346,6 +544,28 @@ static void rsci_receive_chars(struct uart_port *port) } } =20 +static void rsci_break_ctl(struct uart_port *port, int break_state) +{ + unsigned short ccr0_val, ccr1_val; + unsigned long flags; + + uart_port_lock_irqsave(port, &flags); + ccr1_val =3D rsci_serial_in(port, CCR1); + ccr0_val =3D rsci_serial_in(port, CCR0); + + if (break_state =3D=3D -1) { + ccr1_val =3D (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT; + ccr0_val &=3D ~CCR0_TE; + } else { + ccr1_val =3D (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO; + ccr0_val |=3D CCR0_TE; + } + + rsci_serial_out(port, CCR1, ccr1_val); + rsci_serial_out(port, CCR0, ccr0_val); + uart_port_unlock_irqrestore(port, flags); +} + static void rsci_poll_put_char(struct uart_port *port, unsigned char c) { u32 status; @@ -367,14 +587,30 @@ static void rsci_poll_put_char(struct uart_port *port= , unsigned char c) static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) { struct sci_port *s =3D to_sci_port(port); - u32 ctrl_temp =3D - s->params->param_bits->rxtx_enable | CCR0_TIE | - s->hscif_tot; + u32 ctrl_temp =3D s->params->param_bits->rxtx_enable; + + if (s->type =3D=3D SCI_PORT_RSCI) + ctrl_temp |=3D CCR0_TIE | s->hscif_tot; + rsci_serial_out(port, CCR0, ctrl_temp); } =20 +static void rsci_finish_console_write(struct uart_port *port, u32 ctrl) +{ + /* First set TE =3D 0 and then restore the CCR0 value */ + rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE); + rsci_serial_out(port, CCR0, ctrl); +} + static const char *rsci_type(struct uart_port *port) { + struct sci_port *s =3D to_sci_port(port); + + switch (s->type) { + case RSCI_PORT_SCIF: + return "scif"; + } + return "rsci"; } =20 @@ -413,6 +649,17 @@ static const struct sci_port_params rsci_port_params = =3D { .common_regs =3D &rsci_common_regs, }; =20 +static const struct sci_port_params rsci_rzg3e_scif_port_params =3D { + .fifosize =3D 32, + .overrun_reg =3D CSR, + .overrun_mask =3D CSR_ORER, + .sampling_rate_mask =3D SCI_SR(32), + .error_mask =3D RSCI_DEFAULT_ERROR_MASK, + .error_clear =3D RSCI_ERROR_CLEAR, + .param_bits =3D &rsci_port_param_bits, + .common_regs =3D &rsci_common_regs, +}; + static const struct uart_ops rsci_uart_ops =3D { .tx_empty =3D rsci_tx_empty, .set_mctrl =3D rsci_set_mctrl, @@ -420,6 +667,8 @@ static const struct uart_ops rsci_uart_ops =3D { .start_tx =3D rsci_start_tx, .stop_tx =3D rsci_stop_tx, .stop_rx =3D rsci_stop_rx, + .enable_ms =3D rsci_enable_ms, + .break_ctl =3D rsci_break_ctl, .startup =3D sci_startup, .shutdown =3D sci_shutdown, .set_termios =3D rsci_set_termios, @@ -439,6 +688,7 @@ static const struct sci_port_ops rsci_port_ops =3D { .receive_chars =3D rsci_receive_chars, .poll_put_char =3D rsci_poll_put_char, .prepare_console_write =3D rsci_prepare_console_write, + .finish_console_write =3D rsci_finish_console_write, .suspend_regs_size =3D rsci_suspend_regs_size, .shutdown_complete =3D rsci_shutdown_complete, }; @@ -450,6 +700,13 @@ struct sci_of_data of_sci_rsci_data =3D { .params =3D &rsci_port_params, }; =20 +struct sci_of_data of_rsci_scif_data =3D { + .type =3D RSCI_PORT_SCIF, + .ops =3D &rsci_port_ops, + .uart_ops =3D &rsci_uart_ops, + .params =3D &rsci_rzg3e_scif_port_params, +}; + #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON =20 static int __init rsci_early_console_setup(struct earlycon_device *device, @@ -458,6 +715,13 @@ static int __init rsci_early_console_setup(struct earl= ycon_device *device, return scix_early_console_setup(device, &of_sci_rsci_data); } =20 +static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_devi= ce *device, + const char *opt) +{ + return scix_early_console_setup(device, &of_rsci_scif_data); +} + +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early= _console_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_set= up); =20 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h index 2af3f28b465a..ba255f58c088 100644 --- a/drivers/tty/serial/rsci.h +++ b/drivers/tty/serial/rsci.h @@ -6,5 +6,6 @@ #include "sh-sci-common.h" =20 extern struct sci_of_data of_sci_rsci_data; +extern struct sci_of_data of_rsci_scif_data; =20 #endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index e269f4f9edd0..7c3d25a6138c 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3563,6 +3563,11 @@ static struct uart_driver sci_uart_driver =3D { .cons =3D SCI_CONSOLE, }; =20 +static bool sci_is_rsci_fifo_type(u8 type) +{ + return (type =3D=3D SCI_PORT_RSCI || type =3D=3D RSCI_PORT_SCIF); +} + static void sci_remove(struct platform_device *dev) { struct sci_port *s =3D platform_get_drvdata(dev); @@ -3574,7 +3579,7 @@ static void sci_remove(struct platform_device *dev) if (s->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (type =3D=3D PORT_SCIFA || type =3D=3D PORT_SCIFB || type =3D=3D PORT_= HSCIF || - type =3D=3D SCI_PORT_RSCI) + sci_is_rsci_fifo_type(type)) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } =20 @@ -3669,6 +3674,10 @@ static const struct of_device_id of_sci_match[] __ma= ybe_unused =3D { .data =3D &of_sci_scif_rzv2h, }, #ifdef CONFIG_SERIAL_RSCI + { + .compatible =3D "renesas,r9a09g047-rscif", + .data =3D &of_rsci_scif_data, + }, { .compatible =3D "renesas,r9a09g077-rsci", .data =3D &of_sci_rsci_data, @@ -3936,7 +3945,7 @@ static int sci_probe(struct platform_device *dev) return ret; } if (sp->type =3D=3D PORT_SCIFA || sp->type =3D=3D PORT_SCIFB || - sp->type =3D=3D PORT_HSCIF || sp->type =3D=3D SCI_PORT_RSCI) { + sp->type =3D=3D PORT_HSCIF || sci_is_rsci_fifo_type(sp->type)) { ret =3D device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) { --=20 2.43.0