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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:04 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Date: Fri, 14 Nov 2025 10:51:10 +0000 Message-ID: <20251114105201.107406-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add documentation for the serial communication interface (RSCI) found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v2->v3: * Dropped 1st and 3rd items from clk-names and added minItems for the range. * Added minItems for clk and clk-names for RZ/T2H as the range is 2-3 * Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6 * Retained the tag as it is trivial change. v1->v2: * Updated commit message * Added resets:false for non RZ/G3E SoCs. --- .../bindings/serial/renesas,rsci.yaml | 85 ++++++++++++++++--- 1 file changed, 74 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/D= ocumentation/devicetree/bindings/serial/renesas,rsci.yaml index 6b1f827a335b..1a35d6fa67b1 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -10,17 +10,16 @@ maintainers: - Geert Uytterhoeven - Lad Prabhakar =20 -allOf: - - $ref: serial.yaml# - properties: compatible: oneOf: - - items: - - const: renesas,r9a09g087-rsci # RZ/N2H - - const: renesas,r9a09g077-rsci # RZ/T2H + - enum: + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode + - renesas,r9a09g077-rsci # RZ/T2H =20 - items: + - const: renesas,r9a09g087-rsci # RZ/N2H - const: renesas,r9a09g077-rsci # RZ/T2H =20 reg: @@ -42,14 +41,36 @@ properties: =20 clocks: minItems: 2 - maxItems: 3 + maxItems: 6 =20 clock-names: - minItems: 2 + oneOf: + - items: + - const: operation + - const: bus + - const: sck # optional external clock input + + minItems: 2 + + - items: + - const: bus + - const: tclk + - const: tclk_div64 + - const: tclk_div16 + - const: tclk_div4 + - const: sck # optional external clock input + + minItems: 5 + + resets: + items: + - description: Input for resetting the APB clock + - description: Input for resetting TCLK + + reset-names: items: - - const: operation - - const: bus - - const: sck # optional external clock input + - const: presetn + - const: tresetn =20 power-domains: maxItems: 1 @@ -62,6 +83,48 @@ required: - clock-names - power-domains =20 +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-rsci + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g047-rsci + - renesas,r9a09g047-rscif + then: + properties: + clocks: + minItems: 5 + maxItems: 6 + + clock-names: + minItems: 5 + maxItems: 6 + + required: + - resets + - reset-names + else: + properties: + resets: false + unevaluatedProperties: false =20 examples: --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C63E313E19 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:05 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 02/13] serial: rsci: Drop rsci_clear_CFC() Date: Fri, 14 Nov 2025 10:51:11 +0000 Message-ID: <20251114105201.107406-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop rsci_clear_CFC() by reusing rsci_clear_SCxSR() as the contents of both functions are the same. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index b3c48dc1e07d..9681e8ef4bfb 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -199,11 +199,6 @@ static unsigned int rsci_get_mctrl(struct uart_port *p= ort) return 0; } =20 -static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) -{ - rsci_serial_out(port, CFCLR, mask); -} - static void rsci_start_tx(struct uart_port *port) { struct sci_port *sp =3D to_sci_port(port); @@ -275,7 +270,7 @@ static void rsci_transmit_chars(struct uart_port *port) break; } =20 - rsci_clear_CFC(port, CFCLR_TDREC); + rsci_clear_SCxSR(port, CFCLR_TDREC); rsci_serial_out(port, TDR, c); =20 port->icount.tx++; --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D592E313295 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:05 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 03/13] serial: sh-sci: Drop extra lines Date: Fri, 14 Nov 2025 10:51:12 +0000 Message-ID: <20251114105201.107406-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Shorten the number lines in sci_init_clocks() by fitting the error messages within an 100-character length limit. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Updated dev_err_probe() in sci_init_clocks() as it fits in 100-column limit. v1->v2: * Updated commit message 80-character->100-character. * Increased line limit for error messages to 100-column limit. --- drivers/tty/serial/sh-sci.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 53edbf1d8963..1065773555ba 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3186,11 +3186,8 @@ static int sci_init_clocks(struct sci_port *sci_port= , struct device *dev) return PTR_ERR(clk); =20 if (!clk && sci_port->type =3D=3D SCI_PORT_RSCI && - (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) { - return dev_err_probe(dev, -ENODEV, - "failed to get %s\n", - name); - } + (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) + return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); =20 if (!clk && i =3D=3D SCI_FCK) { /* @@ -3200,16 +3197,13 @@ static int sci_init_clocks(struct sci_port *sci_por= t, struct device *dev) */ clk =3D devm_clk_get(dev, "peripheral_clk"); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:06 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 04/13] serial: rsci: Drop unused macro DCR Date: Fri, 14 Nov 2025 10:51:13 +0000 Message-ID: <20251114105201.107406-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop unused macro DCR and its bit definition. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 9681e8ef4bfb..9fa5d387d7db 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -24,7 +24,6 @@ MODULE_IMPORT_NS("SH_SCI"); #define CCR3 0x14 #define CCR4 0x18 #define FCR 0x24 -#define DCR 0x30 #define CSR 0x48 #define FRSR 0x50 #define FTSR 0x54 @@ -119,8 +118,6 @@ MODULE_IMPORT_NS("SH_SCI"); /* FFCLR (FIFO Flag CLear Register) */ #define FFCLR_DRC BIT(0) /* DR Clear */ =20 -#define DCR_DEPOL BIT(0) - static u32 rsci_serial_in(struct uart_port *p, int offset) { return readl(p->membase + offset); --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C48E31329B for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:06 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 05/13] serial: rsci: Drop unused TDR register Date: Fri, 14 Nov 2025 10:51:14 +0000 Message-ID: <20251114105201.107406-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop the unused TDR register-related macros. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 9fa5d387d7db..9609ef73a0d4 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -35,12 +35,6 @@ MODULE_IMPORT_NS("SH_SCI"); #define RDR_FPER BIT(11) /* FIFO Parity Error */ #define RDR_RDAT_MSK GENMASK(8, 0) =20 -/* TDR (Transmit Data Register) */ -#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ -#define TDR_TDAT_9BIT_LSHIFT 0 -#define TDR_TDAT_9BIT_VAL 0x1FF -#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) - /* CCR0 (Common Control Register 0) */ #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ #define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 084A7313E11 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:07 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 06/13] serial: sh-sci: Use devm_reset_control_array_get_exclusive() Date: Fri, 14 Nov 2025 10:51:15 +0000 Message-ID: <20251114105201.107406-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Replace devm_*_get_exclusive()->devm_*_array_get_exclusive() to support existing SoCs along with RZ/G3E as RZ/G3E has 2 resets. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 1065773555ba..78fb3b6a318b 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3710,7 +3710,7 @@ static struct plat_sci_port *sci_parse_dt(struct plat= form_device *pdev, =20 data =3D of_device_get_match_data(&pdev->dev); =20 - rstc =3D devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + rstc =3D devm_reset_control_array_get_optional_exclusive(&pdev->dev); if (IS_ERR(rstc)) return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), "failed to get reset ctrl\n")); --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6116313E02 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:08 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 07/13] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs Date: Fri, 14 Nov 2025 10:51:16 +0000 Message-ID: <20251114105201.107406-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E RSCI tx/rx supports both FIFO and non-FIFO mode. It has 32-stage FIFO. Add RSCI_PORT_SCI port ID for non-FIFO mode and RSCI_PORT_SCIF port ID for FIFO mode. Update the rx_trigger for both these modes. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 2 ++ drivers/tty/serial/sh-sci.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index e3c028df14f1..77f9a67d8efc 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -8,6 +8,8 @@ /* Private port IDs */ enum SCI_PORT_TYPE { SCI_PORT_RSCI =3D BIT(7) | 0, + RSCI_PORT_SCI =3D BIT(7) | 1, + RSCI_PORT_SCIF =3D BIT(7) | 2, }; =20 enum SCI_CLKS { diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 78fb3b6a318b..66ab85571230 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3326,6 +3326,9 @@ static int sci_init_single(struct platform_device *de= v, case SCI_PORT_RSCI: sci_port->rx_trigger =3D 15; break; + case RSCI_PORT_SCIF: + sci_port->rx_trigger =3D 32; + break; default: sci_port->rx_trigger =3D 1; break; --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2667314A61 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:09 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 08/13] serial: sh-sci: Add sci_is_rsci_type() Date: Fri, 14 Nov 2025 10:51:17 +0000 Message-ID: <20251114105201.107406-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add sci_is_rsci_type() for RSCI port type. This will simplify the code when the support added for RSCI_PORT_{SCI,SCIF} private PORT type. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 66ab85571230..2da36e8ce555 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1182,6 +1182,11 @@ static int sci_handle_errors(struct uart_port *port) return copied; } =20 +static bool sci_is_rsci_type(u8 type) +{ + return (type =3D=3D SCI_PORT_RSCI || type =3D=3D RSCI_PORT_SCI || type = =3D=3D RSCI_PORT_SCIF); +} + static int sci_handle_fifo_overrun(struct uart_port *port) { struct tty_port *tport =3D &port->state->port; @@ -1190,7 +1195,7 @@ static int sci_handle_fifo_overrun(struct uart_port *= port) int copied =3D 0; u32 status; =20 - if (s->type !=3D SCI_PORT_RSCI) { + if (!sci_is_rsci_type(s->type)) { reg =3D sci_getreg(port, s->params->overrun_reg); if (!reg->size) return 0; @@ -1198,7 +1203,7 @@ static int sci_handle_fifo_overrun(struct uart_port *= port) =20 status =3D s->ops->read_reg(port, s->params->overrun_reg); if (status & s->params->overrun_mask) { - if (s->type =3D=3D SCI_PORT_RSCI) { + if (sci_is_rsci_type(s->type)) { /* * All of the CFCLR_*C clearing bits match the corresponding * CSR_*status bits. So, reuse the overrun mask for clearing. @@ -2015,7 +2020,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void= *ptr) unsigned long flags; u32 ctrl; =20 - if (s->type !=3D PORT_SCI && s->type !=3D SCI_PORT_RSCI) + if (s->type !=3D PORT_SCI && !sci_is_rsci_type(s->type)) return sci_tx_interrupt(irq, ptr); =20 uart_port_lock_irqsave(port, &flags); @@ -3289,7 +3294,7 @@ static int sci_init_single(struct platform_device *de= v, * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so * shuffle the interrupts. */ - if (p->type =3D=3D PORT_SCI || p->type =3D=3D SCI_PORT_RSCI) + if (p->type =3D=3D PORT_SCI || sci_is_rsci_type(p->type)) swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); =20 /* The SCI generates several interrupts. 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:10 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 09/13] serial: sh-sci: Add support for RZ/G3E RSCI clks Date: Fri, 14 Nov 2025 10:51:18 +0000 Message-ID: <20251114105201.107406-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E RSCI has 6 clocks (5 module clocks + 1 external clock). Add support for the module clocks. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Updated commit description. --- drivers/tty/serial/sh-sci-common.h | 3 +++ drivers/tty/serial/sh-sci.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index 77f9a67d8efc..6c849757119b 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -17,6 +17,9 @@ enum SCI_CLKS { SCI_SCK, /* Optional External Clock */ SCI_BRG_INT, /* Optional BRG Internal Clock Source */ SCI_SCIF_CLK, /* Optional BRG External Clock Source */ + SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */ + SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */ + SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */ SCI_NUM_CLKS }; =20 diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 2da36e8ce555..3b03d3d3f2c7 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3172,6 +3172,9 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) [SCI_SCK] =3D "sck", [SCI_BRG_INT] =3D "brg_int", [SCI_SCIF_CLK] =3D "scif_clk", + [SCI_FCK_DIV64] =3D "tclk_div64", + [SCI_FCK_DIV16] =3D "tclk_div16", + [SCI_FCK_DIV4] =3D "tclk_div4", }; struct clk *clk; unsigned int i; @@ -3181,6 +3184,9 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) } else if (sci_port->type =3D=3D SCI_PORT_RSCI) { clk_names[SCI_FCK] =3D "operation"; clk_names[SCI_BRG_INT] =3D "bus"; + } else if (sci_port->type =3D=3D RSCI_PORT_SCI || sci_port->type =3D=3D R= SCI_PORT_SCIF) { + clk_names[SCI_FCK] =3D "tclk"; + clk_names[SCI_BRG_INT] =3D "bus"; } =20 for (i =3D 0; i < SCI_NUM_CLKS; i++) { @@ -3194,6 +3200,12 @@ static int sci_init_clocks(struct sci_port *sci_port= , struct device *dev) (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT)) return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); =20 + if (!clk && (sci_port->type =3D=3D RSCI_PORT_SCI || + sci_port->type =3D=3D RSCI_PORT_SCIF) && + (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT || i =3D=3D SCI_FCK_DIV64 = || + i =3D=3D SCI_FCK_DIV16 || i =3D=3D SCI_FCK_DIV4)) + return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); + if (!clk && i =3D=3D SCI_FCK) { /* * Not all SH platforms declare a clock lookup entry --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 246BE314D2E for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:10 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 10/13] serial: sh-sci: Make sci_scbrr_calc() public Date: Fri, 14 Nov 2025 10:51:19 +0000 Message-ID: <20251114105201.107406-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Make the function sci_scbrr_calc() public for code reuse to support RZ/G3E RSCI IP. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 3 +++ drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index 6c849757119b..41a437440dfa 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -170,6 +170,9 @@ void sci_port_enable(struct sci_port *sci_port); int sci_startup(struct uart_port *port); void sci_shutdown(struct uart_port *port); =20 +int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, + unsigned int *srr, unsigned int *cks); + #define min_sr(_port) ffs((_port)->sampling_rate_mask) #define max_sr(_port) fls((_port)->sampling_rate_mask) =20 diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 3b03d3d3f2c7..c7f8a9b470fe 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2573,9 +2573,8 @@ static int sci_brg_calc(struct sci_port *s, unsigned = int bps, } =20 /* calculate sample rate, BRR, and clock select */ -static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, - unsigned int *brr, unsigned int *srr, - unsigned int *cks) +int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, + unsigned int *srr, unsigned int *cks) { unsigned long freq =3D s->clk_rates[SCI_FCK]; unsigned int sr, br, prediv, scrate, c; @@ -2639,6 +2638,7 @@ static int sci_scbrr_calc(struct sci_port *s, unsigne= d int bps, min_err, *brr, *srr + 1, *cks); return min_err; } +EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI"); =20 static void sci_reset(struct uart_port *port) { --=20 2.43.0 From nobody Mon Feb 9 03:31:12 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0EC231328F for ; Fri, 14 Nov 2025 10:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763117536; cv=none; b=VnHuMvIOZiBobkQQZWpM2ZCW+pGyOnWu6x45ooOzxykbqwnCEKOXp08maV/DPrUccJD8myLFeONqKOztNuNY6fTYP3yQtc68nLtb8occIbQER1x/Dqg0ticytYqw2FgMm6jY9jsXnj6X7ctwyfxeQX1yFH8i2YH0onjxaxQ8DL8= ARC-Message-Signature: i=1; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:11 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 11/13] serial: sh-sci: Add finish_console_write() callback Date: Fri, 14 Nov 2025 10:51:20 +0000 Message-ID: <20251114105201.107406-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add finish_console_write() callback as RZ/G3E RSCI IP needs special handling compared to other SoCs. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 1 + drivers/tty/serial/sh-sci.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index 41a437440dfa..4e6fee828243 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -94,6 +94,7 @@ struct sci_port_ops { void (*shutdown_complete)(struct uart_port *port); =20 void (*prepare_console_write)(struct uart_port *port, u32 ctrl); + void (*finish_console_write)(struct uart_port *port, u32 ctrl); void (*console_save)(struct uart_port *port); void (*console_restore)(struct uart_port *port); size_t (*suspend_regs_size)(void); diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index c7f8a9b470fe..e269f4f9edd0 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3436,7 +3436,10 @@ static void serial_console_write(struct console *co,= const char *s, cpu_relax(); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:11 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF Date: Fri, 14 Nov 2025 10:51:21 +0000 Message-ID: <20251114105201.107406-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it has 6 clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module clocks + 1 external clock) on T2H and has multiple resets. Add support for the hardware flow control. Signed-off-by: Biju Das --- v2->v3: * Dropped cpu_relax() from rsci_finish_console_write() and added a comment. * Added sci_is_rsci_fifo_type() helper for reuse in probe() and remove(). v1->v2: * Updated commit description. * Updated multiline comment to fit into single line. * Updated set_termios() for getting baud_rate() --- drivers/tty/serial/rsci.c | 282 ++++++++++++++++++++++++++++++++++-- drivers/tty/serial/rsci.h | 1 + drivers/tty/serial/sh-sci.c | 13 +- 3 files changed, 285 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 9609ef73a0d4..43b2e5588d4d 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -11,6 +11,8 @@ #include #include #include + +#include "serial_mctrl_gpio.h" #include "rsci.h" =20 MODULE_IMPORT_NS("SH_SCI"); @@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI"); #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ #define CCR1_CTSE BIT(0) /* CTS Enable */ =20 +/* CCR2 (Common Control Register 2) */ +#define CCR2_INIT 0xFF000004 +#define CCR2_CKS_TCLK (0) /* TCLK clock */ +#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ +#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ +#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ +#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ +#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Selec= t */ +#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ +#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select= */ + +/* CCR3 (Common Control Register 3) */ +#define CCR3_INIT 0x1203 +#define CCR3_BLK BIT(29) /* Block Transfer Mode */ +#define CCR3_GM BIT(28) /* GSM Mode */ +#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ +#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ +#define CCR3_DEN BIT(21) /* Driver Enabled */ +#define CCR3_FM BIT(20) /* FIFO Mode Select */ +#define CCR3_MP BIT(19) /* Multi-Processor Mode */ +#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ +#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */ +#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */ +#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */ +#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */ +#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Se= lect */ +#define CCR3_STP BIT(14) /* Stop bit Length */ +#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ +#define CCR3_LSBF BIT(12) /* LSB First select */ +#define CCR3_CHR1 BIT(9) /* Character Length */ +#define CCR3_CHR0 BIT(8) /* Character Length */ +#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ +#define CCR3_CPOL BIT(1) /* Clock Polarity Select */ +#define CCR3_CPHA BIT(0) /* Clock Phase Select */ + /* FCR (FIFO Control Register) */ #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ #define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ @@ -142,21 +179,160 @@ static void rsci_start_rx(struct uart_port *port) rsci_serial_out(port, CCR0, ctrl); } =20 +static void rsci_enable_ms(struct uart_port *port) +{ + mctrl_gpio_enable_ms(to_sci_port(port)->gpios); +} + +static void rsci_init_pins(struct uart_port *port, unsigned int cflag) +{ + struct sci_port *s =3D to_sci_port(port); + + /* Use port-specific handler if provided */ + if (s->cfg->ops && s->cfg->ops->init_pins) { + s->cfg->ops->init_pins(port, cflag); + return; + } + + if (!s->has_rtscts) + return; + + if (s->autorts) + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | + CCR1_CTSE | CCR1_CTSPEN); +} + +static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) +{ + unsigned int bits; + + if (rx_trig >=3D port->fifosize) + rx_trig =3D port->fifosize - 1; + else if (rx_trig < 1) + rx_trig =3D 1; + + bits =3D rx_trig << 16; + rsci_serial_out(port, FCR, (rsci_serial_in(port, FCR) & ~FCR_RTRG4_0) | b= its); + + return rx_trig; +} + static void rsci_set_termios(struct uart_port *port, struct ktermios *term= ios, const struct ktermios *old) { + unsigned int ccr2_val =3D CCR2_INIT, ccr3_val =3D CCR3_INIT; + unsigned int ccr0_val =3D 0, ccr1_val =3D 0, ccr4_val =3D 0; + unsigned int brr1 =3D 255, cks1 =3D 0, srr1 =3D 15; struct sci_port *s =3D to_sci_port(port); + unsigned int brr =3D 255, cks =3D 0; + int min_err =3D INT_MAX, err; + unsigned long max_freq =3D 0; + unsigned int baud, i; unsigned long flags; + unsigned int ctrl; + int best_clk =3D -1; + + if ((termios->c_cflag & CSIZE) =3D=3D CS7) { + ccr3_val |=3D CCR3_CHR0; + } else { + termios->c_cflag &=3D ~CSIZE; + termios->c_cflag |=3D CS8; + } + + if (termios->c_cflag & PARENB) + ccr1_val |=3D CCR1_PE; + + if (termios->c_cflag & PARODD) + ccr1_val |=3D (CCR1_PE | CCR1_PM); + + if (termios->c_cflag & CSTOPB) + ccr3_val |=3D CCR3_STP; + + /* Enable noise filter function */ + ccr1_val |=3D CCR1_NFEN; + + /* + * earlyprintk comes here early on with port->uartclk set to zero. + * the clock framework is not up and running at this point so here + * we assume that 115200 is the maximum baud rate. please note that + * the baud rate is not programmed during earlyprintk - it is assumed + * that the previous boot loader has enabled required clocks and + * setup the baud rate generator hardware for us already. + */ + if (!port->uartclk) { + max_freq =3D 115200; + } else { + for (i =3D 0; i < SCI_NUM_CLKS; i++) + max_freq =3D max(max_freq, s->clk_rates[i]); + + max_freq /=3D min_sr(s); + } + + baud =3D uart_get_baud_rate(port, termios, old, 0, max_freq); + if (!baud) + goto done; + + /* Divided Functional Clock using standard Bit Rate Register */ + err =3D sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); + if (abs(err) < abs(min_err)) { + best_clk =3D SCI_FCK; + ccr0_val =3D 0; + min_err =3D err; + brr =3D brr1; + cks =3D cks1; + } + +done: + if (best_clk >=3D 0) + dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", + s->clks[best_clk], baud, min_err); =20 sci_port_enable(s); uart_port_lock_irqsave(port, &flags); =20 - /* For now, only RX enabling is supported */ - if (termios->c_cflag & CREAD) + uart_update_timeout(port, termios->c_cflag, baud); + + rsci_serial_out(port, CCR0, ccr0_val); + + ccr3_val |=3D CCR3_FM; + rsci_serial_out(port, CCR3, ccr3_val); + + ccr2_val |=3D (cks << 20) | (brr << 8); + rsci_serial_out(port, CCR2, ccr2_val); + + rsci_serial_out(port, CCR1, ccr1_val); + rsci_serial_out(port, CCR4, ccr4_val); + + ctrl =3D rsci_serial_in(port, FCR); + ctrl |=3D (FCR_RFRST | FCR_TFRST); + rsci_serial_out(port, FCR, ctrl); + + if (s->rx_trigger > 1) + rsci_scif_set_rtrg(port, s->rx_trigger); + + port->status &=3D ~UPSTAT_AUTOCTS; + s->autorts =3D false; + + if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) { + port->status |=3D UPSTAT_AUTOCTS; + s->autorts =3D true; + } + + rsci_init_pins(port, termios->c_cflag); + rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); + rsci_serial_out(port, FFCLR, FFCLR_DRC); + + ccr0_val |=3D CCR0_RE; + rsci_serial_out(port, CCR0, ccr0_val); + + if ((termios->c_cflag & CREAD) !=3D 0) rsci_start_rx(port); =20 uart_port_unlock_irqrestore(port, flags); sci_port_disable(s); + + if (UART_ENABLE_MS(port, termios->c_cflag)) + rsci_enable_ms(port); } =20 static int rsci_txfill(struct uart_port *port) @@ -181,13 +357,34 @@ static unsigned int rsci_tx_empty(struct uart_port *p= ort) =20 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) { - /* Not supported yet */ + if (mctrl & TIOCM_LOOP) { + /* Standard loopback mode */ + rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); + } } =20 static unsigned int rsci_get_mctrl(struct uart_port *port) { - /* Not supported yet */ - return 0; + struct sci_port *s =3D to_sci_port(port); + struct mctrl_gpios *gpios =3D s->gpios; + unsigned int mctrl =3D 0; + + mctrl_gpio_get(gpios, &mctrl); + + /* + * CTS/RTS is handled in hardware when supported, while nothing + * else is wired up. + */ + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) + mctrl |=3D TIOCM_CTS; + + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) + mctrl |=3D TIOCM_DSR; + + if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) + mctrl |=3D TIOCM_CAR; + + return mctrl; } =20 static void rsci_start_tx(struct uart_port *port) @@ -312,7 +509,8 @@ static void rsci_receive_chars(struct uart_port *port) continue; } =20 - /* Store data and status. + /* + * Store data and status. * Non FIFO mode is not supported */ if (rdat & RDR_FFER) { @@ -346,6 +544,28 @@ static void rsci_receive_chars(struct uart_port *port) } } =20 +static void rsci_break_ctl(struct uart_port *port, int break_state) +{ + unsigned short ccr0_val, ccr1_val; + unsigned long flags; + + uart_port_lock_irqsave(port, &flags); + ccr1_val =3D rsci_serial_in(port, CCR1); + ccr0_val =3D rsci_serial_in(port, CCR0); + + if (break_state =3D=3D -1) { + ccr1_val =3D (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT; + ccr0_val &=3D ~CCR0_TE; + } else { + ccr1_val =3D (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO; + ccr0_val |=3D CCR0_TE; + } + + rsci_serial_out(port, CCR1, ccr1_val); + rsci_serial_out(port, CCR0, ccr0_val); + uart_port_unlock_irqrestore(port, flags); +} + static void rsci_poll_put_char(struct uart_port *port, unsigned char c) { u32 status; @@ -367,14 +587,30 @@ static void rsci_poll_put_char(struct uart_port *port= , unsigned char c) static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) { struct sci_port *s =3D to_sci_port(port); - u32 ctrl_temp =3D - s->params->param_bits->rxtx_enable | CCR0_TIE | - s->hscif_tot; + u32 ctrl_temp =3D s->params->param_bits->rxtx_enable; + + if (s->type =3D=3D SCI_PORT_RSCI) + ctrl_temp |=3D CCR0_TIE | s->hscif_tot; + rsci_serial_out(port, CCR0, ctrl_temp); } =20 +static void rsci_finish_console_write(struct uart_port *port, u32 ctrl) +{ + /* First set TE =3D 0 and then restore the CCR0 value */ + rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE); + rsci_serial_out(port, CCR0, ctrl); +} + static const char *rsci_type(struct uart_port *port) { + struct sci_port *s =3D to_sci_port(port); + + switch (s->type) { + case RSCI_PORT_SCIF: + return "scif"; + } + return "rsci"; } =20 @@ -413,6 +649,17 @@ static const struct sci_port_params rsci_port_params = =3D { .common_regs =3D &rsci_common_regs, }; =20 +static const struct sci_port_params rsci_rzg3e_scif_port_params =3D { + .fifosize =3D 32, + .overrun_reg =3D CSR, + .overrun_mask =3D CSR_ORER, + .sampling_rate_mask =3D SCI_SR(32), + .error_mask =3D RSCI_DEFAULT_ERROR_MASK, + .error_clear =3D RSCI_ERROR_CLEAR, + .param_bits =3D &rsci_port_param_bits, + .common_regs =3D &rsci_common_regs, +}; + static const struct uart_ops rsci_uart_ops =3D { .tx_empty =3D rsci_tx_empty, .set_mctrl =3D rsci_set_mctrl, @@ -420,6 +667,8 @@ static const struct uart_ops rsci_uart_ops =3D { .start_tx =3D rsci_start_tx, .stop_tx =3D rsci_stop_tx, .stop_rx =3D rsci_stop_rx, + .enable_ms =3D rsci_enable_ms, + .break_ctl =3D rsci_break_ctl, .startup =3D sci_startup, .shutdown =3D sci_shutdown, .set_termios =3D rsci_set_termios, @@ -439,6 +688,7 @@ static const struct sci_port_ops rsci_port_ops =3D { .receive_chars =3D rsci_receive_chars, .poll_put_char =3D rsci_poll_put_char, .prepare_console_write =3D rsci_prepare_console_write, + .finish_console_write =3D rsci_finish_console_write, .suspend_regs_size =3D rsci_suspend_regs_size, .shutdown_complete =3D rsci_shutdown_complete, }; @@ -450,6 +700,13 @@ struct sci_of_data of_sci_rsci_data =3D { .params =3D &rsci_port_params, }; =20 +struct sci_of_data of_rsci_scif_data =3D { + .type =3D RSCI_PORT_SCIF, + .ops =3D &rsci_port_ops, + .uart_ops =3D &rsci_uart_ops, + .params =3D &rsci_rzg3e_scif_port_params, +}; + #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON =20 static int __init rsci_early_console_setup(struct earlycon_device *device, @@ -458,6 +715,13 @@ static int __init rsci_early_console_setup(struct earl= ycon_device *device, return scix_early_console_setup(device, &of_sci_rsci_data); } =20 +static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_devi= ce *device, + const char *opt) +{ + return scix_early_console_setup(device, &of_rsci_scif_data); +} + +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early= _console_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_set= up); =20 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h index 2af3f28b465a..ba255f58c088 100644 --- a/drivers/tty/serial/rsci.h +++ b/drivers/tty/serial/rsci.h @@ -6,5 +6,6 @@ #include "sh-sci-common.h" =20 extern struct sci_of_data of_sci_rsci_data; +extern struct sci_of_data of_rsci_scif_data; =20 #endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index e269f4f9edd0..7c3d25a6138c 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3563,6 +3563,11 @@ static struct uart_driver sci_uart_driver =3D { .cons =3D SCI_CONSOLE, }; =20 +static bool sci_is_rsci_fifo_type(u8 type) +{ + return (type =3D=3D SCI_PORT_RSCI || type =3D=3D RSCI_PORT_SCIF); +} + static void sci_remove(struct platform_device *dev) { struct sci_port *s =3D platform_get_drvdata(dev); @@ -3574,7 +3579,7 @@ static void sci_remove(struct platform_device *dev) if (s->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (type =3D=3D PORT_SCIFA || type =3D=3D PORT_SCIFB || type =3D=3D PORT_= HSCIF || - type =3D=3D SCI_PORT_RSCI) + sci_is_rsci_fifo_type(type)) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } =20 @@ -3669,6 +3674,10 @@ static const struct of_device_id of_sci_match[] __ma= ybe_unused =3D { .data =3D &of_sci_scif_rzv2h, }, #ifdef CONFIG_SERIAL_RSCI + { + .compatible =3D "renesas,r9a09g047-rscif", + .data =3D &of_rsci_scif_data, + }, { .compatible =3D "renesas,r9a09g077-rsci", .data =3D &of_sci_rsci_data, @@ -3936,7 +3945,7 @@ static int sci_probe(struct platform_device *dev) return ret; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f17cbfsm9031255f8f.35.2025.11.14.02.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:52:12 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 13/13] serial: sh-sci: Add support for RZ/G3E RSCI SCI Date: Fri, 14 Nov 2025 10:51:22 +0000 Message-ID: <20251114105201.107406-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> References: <20251114105201.107406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for RZ/G3E RSCI SCI(a.k.a non FIFO mode). Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- drivers/tty/serial/rsci.c | 138 +++++++++++++++++++++++++----------- drivers/tty/serial/rsci.h | 1 + drivers/tty/serial/sh-sci.c | 4 ++ 3 files changed, 103 insertions(+), 40 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index 43b2e5588d4d..39960e7c60ac 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -161,8 +161,11 @@ static void rsci_serial_out(struct uart_port *p, int o= ffset, int value) =20 static void rsci_clear_DRxC(struct uart_port *port) { + struct sci_port *s =3D to_sci_port(port); + rsci_serial_out(port, CFCLR, CFCLR_RDRFC); - rsci_serial_out(port, FFCLR, FFCLR_DRC); + if (s->type !=3D RSCI_PORT_SCI) + rsci_serial_out(port, FFCLR, FFCLR_DRC); } =20 static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask) @@ -229,7 +232,6 @@ static void rsci_set_termios(struct uart_port *port, st= ruct ktermios *termios, unsigned long max_freq =3D 0; unsigned int baud, i; unsigned long flags; - unsigned int ctrl; int best_clk =3D -1; =20 if ((termios->c_cflag & CSIZE) =3D=3D CS7) { @@ -294,7 +296,11 @@ static void rsci_set_termios(struct uart_port *port, s= truct ktermios *termios, =20 rsci_serial_out(port, CCR0, ccr0_val); =20 - ccr3_val |=3D CCR3_FM; + if (s->type =3D=3D RSCI_PORT_SCI) + ccr3_val |=3D CCR3_RXDESEL; + else + ccr3_val |=3D CCR3_FM; + rsci_serial_out(port, CCR3, ccr3_val); =20 ccr2_val |=3D (cks << 20) | (brr << 8); @@ -303,12 +309,16 @@ static void rsci_set_termios(struct uart_port *port, = struct ktermios *termios, rsci_serial_out(port, CCR1, ccr1_val); rsci_serial_out(port, CCR4, ccr4_val); =20 - ctrl =3D rsci_serial_in(port, FCR); - ctrl |=3D (FCR_RFRST | FCR_TFRST); - rsci_serial_out(port, FCR, ctrl); + if (s->type !=3D RSCI_PORT_SCI) { + unsigned int ctrl; =20 - if (s->rx_trigger > 1) - rsci_scif_set_rtrg(port, s->rx_trigger); + ctrl =3D rsci_serial_in(port, FCR); + ctrl |=3D (FCR_RFRST | FCR_TFRST); + rsci_serial_out(port, FCR, ctrl); + + if (s->rx_trigger > 1) + rsci_scif_set_rtrg(port, s->rx_trigger); + } =20 port->status &=3D ~UPSTAT_AUTOCTS; s->autorts =3D false; @@ -320,7 +330,8 @@ static void rsci_set_termios(struct uart_port *port, st= ruct ktermios *termios, =20 rsci_init_pins(port, termios->c_cflag); rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); - rsci_serial_out(port, FFCLR, FFCLR_DRC); + if (s->type !=3D RSCI_PORT_SCI) + rsci_serial_out(port, FFCLR, FFCLR_DRC); =20 ccr0_val |=3D CCR0_RE; rsci_serial_out(port, CCR0, ccr0_val); @@ -337,12 +348,23 @@ static void rsci_set_termios(struct uart_port *port, = struct ktermios *termios, =20 static int rsci_txfill(struct uart_port *port) { - return rsci_serial_in(port, FTSR); + struct sci_port *s =3D to_sci_port(port); + + if (s->type =3D=3D RSCI_PORT_SCI) + return !(rsci_serial_in(port, CSR) & CSR_TDRE); + else + return rsci_serial_in(port, FTSR); } =20 static int rsci_rxfill(struct uart_port *port) { - u32 val =3D rsci_serial_in(port, FRSR); + struct sci_port *s =3D to_sci_port(port); + u32 val; + + if (s->type =3D=3D RSCI_PORT_SCI) + return (rsci_serial_in(port, CSR) & CSR_RDRF) !=3D 0; + + val =3D rsci_serial_in(port, FRSR); =20 return FIELD_GET(FRSR_R5_0, val); } @@ -357,7 +379,9 @@ static unsigned int rsci_tx_empty(struct uart_port *por= t) =20 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) { - if (mctrl & TIOCM_LOOP) { + struct sci_port *s =3D to_sci_port(port); + + if ((mctrl & TIOCM_LOOP) && s->type !=3D RSCI_PORT_SCI) { /* Standard loopback mode */ rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); } @@ -478,12 +502,13 @@ static void rsci_transmit_chars(struct uart_port *por= t) static void rsci_receive_chars(struct uart_port *port) { struct tty_port *tport =3D &port->state->port; + struct sci_port *s =3D to_sci_port(port); u32 rdat, status, frsr_status =3D 0; int i, count, copied =3D 0; unsigned char flag; =20 status =3D rsci_serial_in(port, CSR); - frsr_status =3D rsci_serial_in(port, FRSR); + frsr_status =3D (s->type =3D=3D RSCI_PORT_SCI) ? 0 : rsci_serial_in(port,= FRSR); =20 if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) return; @@ -496,34 +521,40 @@ static void rsci_receive_chars(struct uart_port *port) if (count =3D=3D 0) break; =20 - for (i =3D 0; i < count; i++) { - char c; - - rdat =3D rsci_serial_in(port, RDR); - /* 9-bits data is not supported yet */ - c =3D rdat & RDR_RDAT_MSK; - - if (uart_handle_sysrq_char(port, c)) { - count--; - i--; - continue; - } - - /* - * Store data and status. - * Non FIFO mode is not supported - */ - if (rdat & RDR_FFER) { - flag =3D TTY_FRAME; - port->icount.frame++; - } else if (rdat & RDR_FPER) { - flag =3D TTY_PARITY; - port->icount.parity++; - } else { - flag =3D TTY_NORMAL; + if (s->type =3D=3D RSCI_PORT_SCI) { + char c =3D rsci_serial_in(port, RDR) & RDR_RDAT_MSK; + + if (uart_handle_sysrq_char(port, c)) + count =3D 0; + else + tty_insert_flip_char(tport, c, TTY_NORMAL); + } else { + for (i =3D 0; i < count; i++) { + char c; + + rdat =3D rsci_serial_in(port, RDR); + /* 9-bits data is not supported yet */ + c =3D rdat & RDR_RDAT_MSK; + + if (uart_handle_sysrq_char(port, c)) { + count--; + i--; + continue; + } + + /* Store data and status */ + if (rdat & RDR_FFER) { + flag =3D TTY_FRAME; + port->icount.frame++; + } else if (rdat & RDR_FPER) { + flag =3D TTY_PARITY; + port->icount.parity++; + } else { + flag =3D TTY_NORMAL; + } + + tty_insert_flip_char(tport, c, flag); } - - tty_insert_flip_char(tport, c, flag); } =20 rsci_serial_in(port, CSR); /* dummy read */ @@ -607,6 +638,8 @@ static const char *rsci_type(struct uart_port *port) struct sci_port *s =3D to_sci_port(port); =20 switch (s->type) { + case RSCI_PORT_SCI: + return "sci"; case RSCI_PORT_SCIF: return "scif"; } @@ -649,6 +682,17 @@ static const struct sci_port_params rsci_port_params = =3D { .common_regs =3D &rsci_common_regs, }; =20 +static const struct sci_port_params rsci_rzg3e_sci_port_params =3D { + .fifosize =3D 1, + .overrun_reg =3D CSR, + .overrun_mask =3D CSR_ORER, + .sampling_rate_mask =3D SCI_SR(32), + .error_mask =3D RSCI_DEFAULT_ERROR_MASK, + .error_clear =3D RSCI_ERROR_CLEAR, + .param_bits =3D &rsci_port_param_bits, + .common_regs =3D &rsci_common_regs, +}; + static const struct sci_port_params rsci_rzg3e_scif_port_params =3D { .fifosize =3D 32, .overrun_reg =3D CSR, @@ -700,6 +744,13 @@ struct sci_of_data of_sci_rsci_data =3D { .params =3D &rsci_port_params, }; =20 +struct sci_of_data of_rsci_sci_data =3D { + .type =3D RSCI_PORT_SCI, + .ops =3D &rsci_port_ops, + .uart_ops =3D &rsci_uart_ops, + .params =3D &rsci_rzg3e_sci_port_params, +}; + struct sci_of_data of_rsci_scif_data =3D { .type =3D RSCI_PORT_SCIF, .ops =3D &rsci_port_ops, @@ -715,12 +766,19 @@ static int __init rsci_early_console_setup(struct ear= lycon_device *device, return scix_early_console_setup(device, &of_sci_rsci_data); } =20 +static int __init rsci_rzg3e_sci_early_console_setup(struct earlycon_devic= e *device, + const char *opt) +{ + return scix_early_console_setup(device, &of_rsci_sci_data); +} + static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_devi= ce *device, const char *opt) { return scix_early_console_setup(device, &of_rsci_scif_data); } =20 +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_sci_early_c= onsole_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early= _console_setup); OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_set= up); =20 diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h index ba255f58c088..df7a7edad7d4 100644 --- a/drivers/tty/serial/rsci.h +++ b/drivers/tty/serial/rsci.h @@ -6,6 +6,7 @@ #include "sh-sci-common.h" =20 extern struct sci_of_data of_sci_rsci_data; +extern struct sci_of_data of_rsci_sci_data; extern struct sci_of_data of_rsci_scif_data; =20 #endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 7c3d25a6138c..82e472957913 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3674,6 +3674,10 @@ static const struct of_device_id of_sci_match[] __ma= ybe_unused =3D { .data =3D &of_sci_scif_rzv2h, }, #ifdef CONFIG_SERIAL_RSCI + { + .compatible =3D "renesas,r9a09g047-rsci", + .data =3D &of_rsci_sci_data, + }, { .compatible =3D "renesas,r9a09g047-rscif", .data =3D &of_rsci_scif_data, --=20 2.43.0