From nobody Mon Feb 9 12:25:07 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BAD930EF71; Fri, 14 Nov 2025 10:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115058; cv=none; b=Yj9AD3CD5R+kiHwFBWENKR8Hnq3cb+MXdmNQv6S9ZHADKvkT38+u1vQzLSpwitz6F9wqvq26xgSVQDXa40n+98rCTloTtt6E6hBtErY/NHAJoVuxuAFsddCRNK7hrnDSYJCd2B6WYIA3ix06OdZzII3G68QFdJBVd/eFBEj/WVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115058; c=relaxed/simple; bh=y0R355uAebCKJwwcxV5wFFdVmXK5xnO/pzj3PYhKo+Y=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T6eMPSqAHz3rKFeEJNDAyATKWd1cjqCWXyzP7npzEdm2vtam0yuiYpEWMvQjJoIJWwPI3/Jb5yhn6oUTeTKBVsv1Qvnqa2UAOEILD+BlajUFQ4hydcnS/zooe6QllrossJ4jygMzKz1lbOrs/8q41BX2wFdlq9FvY2MG+yWdouA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 14 Nov 2025 18:10:42 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 14 Nov 2025 18:10:42 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH v2 2/4] spi: aspeed: Enable Quad SPI mode for page program Date: Fri, 14 Nov 2025 18:10:40 +0800 Message-ID: <20251114101042.1520997-3-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> References: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ensure the controller switches to quad I/O mode when spi-tx-bus-width dts property is 4 and the Quad SPI program opcode (32h or 34h) is used. Without this change, high-bit data will be lost during page programming. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 179c47ffbfeb..4163632fed8b 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -263,11 +263,15 @@ static ssize_t aspeed_spi_write_user(struct aspeed_sp= i_chip *chip, const struct spi_mem_op *op) { int ret; + int io_mode =3D aspeed_spi_get_io_mode(op); =20 aspeed_spi_start_user(chip); ret =3D aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op-= >cmd.opcode); if (ret < 0) goto stop_user; + + aspeed_spi_set_io_mode(chip, io_mode); + aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes= ); stop_user: aspeed_spi_stop_user(chip); --=20 2.34.1