From nobody Sun Feb 8 16:05:30 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7912230C612; Fri, 14 Nov 2025 10:10:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115056; cv=none; b=sBsnN394/Fa4Ak4tg6Zz5dB/Nr4UVMXCp9iVw4i6XszPAvzRC358MaRE9ac+55KjfLlHUGjYch5X/xgaEfknR8T0z7F8iXCpI/jWjZPjD7HvlGG5ruNb8sDQtWGOjlOlrmq1r0EextvwK1aQS8ipNdRrgvmuFeb5fGw80ZN2msE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115056; c=relaxed/simple; bh=KMnliyZQCR7HQD6k1yLADQalxUxMfja7aEXAPjdWxso=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TAEywz0SW0j3twIKV1jXw/E3mHlpwn/c1JogYGJ8sTGSyS7/e1yfm6phI5Q0HqE1SJpygfJ4rwWGSavS0/ZZnUHh8nHQB3WvxrKqC/i8ddYOOmQ7oGVexTgZlTRKkU4t25BZfdef9qRO8P7qnS2qpZCU4/kr/uiCb94XB4NQs/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 14 Nov 2025 18:10:42 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 14 Nov 2025 18:10:42 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , CC: Conor Dooley Subject: [PATCH v2 1/4] dt-bindings: spi: aspeed,ast2600-fmc: Add AST2700 SoC support Date: Fri, 14 Nov 2025 18:10:39 +0800 Message-ID: <20251114101042.1520997-2-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> References: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add AST2700 to the list of supported SoCs in the ASPEED FMC/SPI bindings. AST2700 FMC/SPI controllers are not compatible with AST2600 due to the following hardware differences: - Address decoding unit uses 64KB granularity (AST2600 uses 1MB). - Segment register semantics are changed. AST2600: start <=3D range <=3D end AST2700: start <=3D range < end - Hardware limitations in AST2600 address decoding registers have been resolved in AST2700, so extra callback function used for bug fixup is no longer required. These differences require distinct compatible strings for AST2700. Signed-off-by: Chin-Ting Kuo Acked-by: Conor Dooley --- Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml = b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml index 57d932af4506..80e542624cc6 100644 --- a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml @@ -12,7 +12,7 @@ maintainers: =20 description: | This binding describes the Aspeed Static Memory Controllers (FMC and - SPI) of the AST2400, AST2500 and AST2600 SOCs. + SPI) of the AST2400, AST2500, AST2600 and AST2700 SOCs. =20 allOf: - $ref: spi-controller.yaml# @@ -20,6 +20,8 @@ allOf: properties: compatible: enum: + - aspeed,ast2700-fmc + - aspeed,ast2700-spi - aspeed,ast2600-fmc - aspeed,ast2600-spi - aspeed,ast2500-fmc --=20 2.34.1 From nobody Sun Feb 8 16:05:30 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BAD930EF71; Fri, 14 Nov 2025 10:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115058; cv=none; b=Yj9AD3CD5R+kiHwFBWENKR8Hnq3cb+MXdmNQv6S9ZHADKvkT38+u1vQzLSpwitz6F9wqvq26xgSVQDXa40n+98rCTloTtt6E6hBtErY/NHAJoVuxuAFsddCRNK7hrnDSYJCd2B6WYIA3ix06OdZzII3G68QFdJBVd/eFBEj/WVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115058; c=relaxed/simple; bh=y0R355uAebCKJwwcxV5wFFdVmXK5xnO/pzj3PYhKo+Y=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T6eMPSqAHz3rKFeEJNDAyATKWd1cjqCWXyzP7npzEdm2vtam0yuiYpEWMvQjJoIJWwPI3/Jb5yhn6oUTeTKBVsv1Qvnqa2UAOEILD+BlajUFQ4hydcnS/zooe6QllrossJ4jygMzKz1lbOrs/8q41BX2wFdlq9FvY2MG+yWdouA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 14 Nov 2025 18:10:42 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 14 Nov 2025 18:10:42 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH v2 2/4] spi: aspeed: Enable Quad SPI mode for page program Date: Fri, 14 Nov 2025 18:10:40 +0800 Message-ID: <20251114101042.1520997-3-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> References: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ensure the controller switches to quad I/O mode when spi-tx-bus-width dts property is 4 and the Quad SPI program opcode (32h or 34h) is used. Without this change, high-bit data will be lost during page programming. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 179c47ffbfeb..4163632fed8b 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -263,11 +263,15 @@ static ssize_t aspeed_spi_write_user(struct aspeed_sp= i_chip *chip, const struct spi_mem_op *op) { int ret; + int io_mode =3D aspeed_spi_get_io_mode(op); =20 aspeed_spi_start_user(chip); ret =3D aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op-= >cmd.opcode); if (ret < 0) goto stop_user; + + aspeed_spi_set_io_mode(chip, io_mode); + aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes= ); stop_user: aspeed_spi_stop_user(chip); --=20 2.34.1 From nobody Sun Feb 8 16:05:30 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D7E230F7F9; Fri, 14 Nov 2025 10:10:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115060; cv=none; b=MRkmIkYN8geRyuraDYqme8Dhe2fcXx50Gc1AUNvj1qmPvdNoTYRNHU3IC/3HlGQADJ14Sg6lOwGsEs7/9darNTpwruiWSpy9lyaRHgMp3Nzvgl6dTy0vjGQoKcsX7gLMUIX+ubJRZ/eWKadvGGEMGqGBG9ZlZ9JO6jU0Vii9kPw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115060; c=relaxed/simple; bh=WYasyDutiN9J04g4w7tsx80DcE2lP79ppqoN5EAnPH8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SOe21ErAd4o5tp3Tl8U/KVWfBM5KaaIBLcrzdLBzrJDy+JXBpw4nvF0Nlrpl4LsYPhUk5QJ/lxzVxs/Bf2tQsHnvAqQeW9gUDJBpAQDjNzKqBeAIRyrKeLIW93gcd4PtTPxJn2Rp91tfnbzoCBeKlPw7aHUCg/8c/fyQ2vNC6FM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 14 Nov 2025 18:10:42 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 14 Nov 2025 18:10:42 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH v2 3/4] spi: aspeed: Use phys_addr_t for bus addresses to support 64-bit platforms Date: Fri, 14 Nov 2025 18:10:41 +0800 Message-ID: <20251114101042.1520997-4-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> References: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update bus address types from u32 to phys_addr_t to support systems with 64-bit memory address space. This change ensures compatibility with upcoming SoCs that extend the system bus beyond 32-bit, while maintaining support for existing platforms. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 4163632fed8b..d1a8bdf6d540 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -82,9 +82,10 @@ struct aspeed_spi_data { u32 hdiv_max; u32 min_window_size; =20 - u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg); - u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg); - u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end); + phys_addr_t (*segment_start)(struct aspeed_spi *aspi, u32 reg); + phys_addr_t (*segment_end)(struct aspeed_spi *aspi, u32 reg); + u32 (*segment_reg)(struct aspeed_spi *aspi, phys_addr_t start, + phys_addr_t end); int (*adjust_window)(struct aspeed_spi *aspi); u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz); int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv, @@ -97,7 +98,7 @@ struct aspeed_spi { const struct aspeed_spi_data *data; =20 void __iomem *regs; - u32 ahb_base_phy; + phys_addr_t ahb_base_phy; u32 ahb_window_size; u32 num_cs; struct device *dev; @@ -484,9 +485,9 @@ static int aspeed_spi_chip_set_default_window(struct as= peed_spi *aspi) /* Assign the minimum window size to each CS */ for (cs =3D 0; cs < aspi->num_cs; cs++) { aspi->chips[cs].ahb_window_size =3D aspi->data->min_window_size; - dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ]", - cs, aspi->ahb_base_phy + aspi->data->min_window_size * cs, - aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1); + dev_dbg(aspi->dev, "CE%d default window [ 0x%.9llx - 0x%.9llx ]", + cs, (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs), + (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1)); } =20 /* Close unused CS */ @@ -930,17 +931,18 @@ static void aspeed_spi_remove(struct platform_device = *pdev) * The address range is encoded with absolute addresses in the overall * mapping window. */ -static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg) +static phys_addr_t aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 r= eg) { return ((reg >> 16) & 0xFF) << 23; } =20 -static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) +static phys_addr_t aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) { return ((reg >> 24) & 0xFF) << 23; } =20 -static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 = end) +static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, + phys_addr_t start, phys_addr_t end) { return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); } @@ -952,16 +954,16 @@ static u32 aspeed_spi_segment_reg(struct aspeed_spi *= aspi, u32 start, u32 end) =20 #define AST2600_SEG_ADDR_MASK 0x0ff00000 =20 -static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi, - u32 reg) +static phys_addr_t aspeed_spi_segment_ast2600_start(struct aspeed_spi *asp= i, + u32 reg) { u32 start_offset =3D (reg << 16) & AST2600_SEG_ADDR_MASK; =20 return aspi->ahb_base_phy + start_offset; } =20 -static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, - u32 reg) +static phys_addr_t aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, + u32 reg) { u32 end_offset =3D reg & AST2600_SEG_ADDR_MASK; =20 @@ -973,7 +975,7 @@ static u32 aspeed_spi_segment_ast2600_end(struct aspeed= _spi *aspi, } =20 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi, - u32 start, u32 end) + phys_addr_t start, phys_addr_t end) { /* disable zero size segments */ if (start =3D=3D end) --=20 2.34.1 From nobody Sun Feb 8 16:05:30 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96E7F30FC13; Fri, 14 Nov 2025 10:11:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763115062; cv=none; b=OKBn3WRmOkYAgw+Fjdt+WXPQTzIGEieKSiw+3dmIbFILzLX6ZRudU/GopEfTlnPBkDA1Zn9vct/XRRdLEn+Lu7GCP+aNm1KQOemL8YQmcohDCy9B4xIv6hvIBCcTrM/w23Z8OvrHBZuJECg/PtzUP8FxzDL1NBEHJcisU4aSYyE= ARC-Message-Signature: i=1; a=rsa-sha256; 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Fri, 14 Nov 2025 18:10:43 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH v2 4/4] spi: aspeed: Add support for the AST2700 SPI controller Date: Fri, 14 Nov 2025 18:10:42 +0800 Message-ID: <20251114101042.1520997-5-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> References: <20251114101042.1520997-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the driver to support the AST2700 SPI controller. Compared to AST2600, AST2700 has the following characteristics: - A 64-bit memory address space. - A 64KB address decoding unit. - Segment registers now use (start <=3D range < end) semantics, which differs slightly from (start <=3D range <=3D end) in AST2600. - Known issues related to address decoding range registers have been resolved, and the decoding range is now 1GB, which is sufficient. Therefore, the adjust_window callback is no longer required on AST2700 for range adjustment and bug fixes. - The SPI clock divider method and timing calibration logic remain unchanged from AST2600. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 71 ++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index d1a8bdf6d540..db3e096f2eb0 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -985,6 +985,41 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspee= d_spi *aspi, ((end - 1) & AST2600_SEG_ADDR_MASK); } =20 +/* The Segment Registers of the AST2700 use a 64KB unit. */ +#define AST2700_SEG_ADDR_MASK 0x7fff0000 + +static phys_addr_t aspeed_spi_segment_ast2700_start(struct aspeed_spi *asp= i, + u32 reg) +{ + u64 start_offset =3D (reg << 16) & AST2700_SEG_ADDR_MASK; + + if (!start_offset) + return aspi->ahb_base_phy; + + return aspi->ahb_base_phy + start_offset; +} + +static phys_addr_t aspeed_spi_segment_ast2700_end(struct aspeed_spi *aspi, + u32 reg) +{ + u64 end_offset =3D reg & AST2700_SEG_ADDR_MASK; + + if (!end_offset) + return aspi->ahb_base_phy; + + return aspi->ahb_base_phy + end_offset; +} + +static u32 aspeed_spi_segment_ast2700_reg(struct aspeed_spi *aspi, + phys_addr_t start, phys_addr_t end) +{ + if (start =3D=3D end) + return 0; + + return (u32)(((start & AST2700_SEG_ADDR_MASK) >> 16) | + (end & AST2700_SEG_ADDR_MASK)); +} + /* * Read timing compensation sequences */ @@ -1511,6 +1546,40 @@ static const struct aspeed_spi_data ast2600_spi_data= =3D { .adjust_window =3D aspeed_adjust_window_ast2600, }; =20 +static const struct aspeed_spi_data ast2700_fmc_data =3D { + .max_cs =3D 3, + .hastype =3D false, + .mode_bits =3D SPI_RX_QUAD | SPI_TX_QUAD, + .we0 =3D 16, + .ctl0 =3D CE0_CTRL_REG, + .timing =3D CE0_TIMING_COMPENSATION_REG, + .hclk_mask =3D 0xf0fff0ff, + .hdiv_max =3D 2, + .min_window_size =3D 0x10000, + .get_clk_div =3D aspeed_get_clk_div_ast2600, + .calibrate =3D aspeed_spi_ast2600_calibrate, + .segment_start =3D aspeed_spi_segment_ast2700_start, + .segment_end =3D aspeed_spi_segment_ast2700_end, + .segment_reg =3D aspeed_spi_segment_ast2700_reg, +}; + +static const struct aspeed_spi_data ast2700_spi_data =3D { + .max_cs =3D 2, + .hastype =3D false, + .mode_bits =3D SPI_RX_QUAD | SPI_TX_QUAD, + .we0 =3D 16, + .ctl0 =3D CE0_CTRL_REG, + .timing =3D CE0_TIMING_COMPENSATION_REG, + .hclk_mask =3D 0xf0fff0ff, + .hdiv_max =3D 2, + .min_window_size =3D 0x10000, + .get_clk_div =3D aspeed_get_clk_div_ast2600, + .calibrate =3D aspeed_spi_ast2600_calibrate, + .segment_start =3D aspeed_spi_segment_ast2700_start, + .segment_end =3D aspeed_spi_segment_ast2700_end, + .segment_reg =3D aspeed_spi_segment_ast2700_reg, +}; + static const struct of_device_id aspeed_spi_matches[] =3D { { .compatible =3D "aspeed,ast2400-fmc", .data =3D &ast2400_fmc_data }, { .compatible =3D "aspeed,ast2400-spi", .data =3D &ast2400_spi_data }, @@ -1518,6 +1587,8 @@ static const struct of_device_id aspeed_spi_matches[]= =3D { { .compatible =3D "aspeed,ast2500-spi", .data =3D &ast2500_spi_data }, { .compatible =3D "aspeed,ast2600-fmc", .data =3D &ast2600_fmc_data }, { .compatible =3D "aspeed,ast2600-spi", .data =3D &ast2600_spi_data }, + { .compatible =3D "aspeed,ast2700-fmc", .data =3D &ast2700_fmc_data }, + { .compatible =3D "aspeed,ast2700-spi", .data =3D &ast2700_spi_data }, { } }; MODULE_DEVICE_TABLE(of, aspeed_spi_matches); --=20 2.34.1