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Fri, 14 Nov 2025 00:28:39 -0800 (PST) Received: from hu-sartgarg-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b927c24254sm4485425b3a.64.2025.11.14.00.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 00:28:39 -0800 (PST) From: Sarthak Garg To: Adrian Hunter , Ulf Hansson Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com, Sarthak Garg Subject: [PATCH V2] mmc: sdhci-msm: Avoid early clock doubling during HS400 transition Date: Fri, 14 Nov 2025 13:58:24 +0530 Message-Id: <20251114082824.3825501-1-sarthak.garg@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Jv38bc4C c=1 sm=1 tr=0 ts=6916e839 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ZhLSBf8pC8IsRUYoglEA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA2NSBTYWx0ZWRfX0FII1KTToQcO ib//xfHtHrRLwPmd94ZDIxlK0mpn/q4qrvRhcCuh73QUqTp9DjaM8u2L4BGBhjHpq0ExpGz8KIl gEed+EKZcaHgNgvnxrRHMD7OB+58WaCApwliTHsJUjN4qQRyvH5ZwK69KJNG2DVk2TWtnCHmvDt g5RiP5CdirGAdXf6juMP10wvkSfLjp98CKRKDL4enkmzTKyCzIlYYRFZQGRPZ6VnH7C/1dI5KtZ KkXRR2eYhn2X2VncuDN2luusrzkjb7xNtHTar3jVGpXbKviWRG37bgXVvPXMzSLChgb11D6O2rl 8F6zi6MdSOXycX2Z1AR8eAwnGMefrzW6pN3PGNf8FSXIumtaSanJpcwAhCv4YI7X0xsVyyOv3ct ww3hTtTiRKXs+UWTxJ2SxslcknFhEA== X-Proofpoint-ORIG-GUID: MKt-dXKhkXif7EN5nhljAcVZzvo6C02G X-Proofpoint-GUID: MKt-dXKhkXif7EN5nhljAcVZzvo6C02G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_02,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140065 Content-Type: text/plain; charset="utf-8" According to the hardware programming guide, the clock frequency must remain below 52MHz during the transition to HS400 mode. However,in the current implementation, the timing is set to HS400 (a DDR mode) before adjusting the clock. This causes the clock to double prematurely to 104MHz during the transition phase, violating the specification and potentially resulting in CRC errors or CMD timeouts. This change ensures that clock doubling is avoided during intermediate transitions and is applied only when the card requires a 200MHz clock for HS400 operation. Signed-off-by: Sarthak Garg Acked-by: Adrian Hunter Reviewed-by: Bjorn Andersson --- Changes from v1: As per Bjorn Andersson's comment : - Pass "timing" as an argument to msm_set_clock_rate_for_bus_mode(), and then pass host, clock, and timing to msm_get_clock_mult_for_bus_mode() to align with the original intent of the prototype. --- drivers/mmc/host/sdhci-msm.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4e5edbf2fc9b..3b85233131b3 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -344,41 +344,43 @@ static void sdhci_msm_v5_variant_writel_relaxed(u32 v= al, writel_relaxed(val, host->ioaddr + offset); } =20 -static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *hos= t) +static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *hos= t, + unsigned int clock, + unsigned int timing) { - struct mmc_ios ios =3D host->mmc->ios; /* * The SDHC requires internal clock frequency to be double the * actual clock that will be set for DDR mode. The controller * uses the faster clock(100/400MHz) for some of its parts and * send the actual required clock (50/200MHz) to the card. */ - if (ios.timing =3D=3D MMC_TIMING_UHS_DDR50 || - ios.timing =3D=3D MMC_TIMING_MMC_DDR52 || - ios.timing =3D=3D MMC_TIMING_MMC_HS400 || + if (timing =3D=3D MMC_TIMING_UHS_DDR50 || + timing =3D=3D MMC_TIMING_MMC_DDR52 || + (timing =3D=3D MMC_TIMING_MMC_HS400 && + clock =3D=3D MMC_HS200_MAX_DTR) || host->flags & SDHCI_HS400_TUNING) return 2; return 1; } =20 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, - unsigned int clock) + unsigned int clock, + unsigned int timing) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); - struct mmc_ios curr_ios =3D host->mmc->ios; struct clk *core_clk =3D msm_host->bulk_clks[0].clk; unsigned long achieved_rate; unsigned int desired_rate; unsigned int mult; int rc; =20 - mult =3D msm_get_clock_mult_for_bus_mode(host); + mult =3D msm_get_clock_mult_for_bus_mode(host, clock, timing); desired_rate =3D clock * mult; rc =3D dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate); if (rc) { pr_err("%s: Failed to set clock at rate %u at timing %d\n", - mmc_hostname(host->mmc), desired_rate, curr_ios.timing); + mmc_hostname(host->mmc), desired_rate, timing); return; } =20 @@ -397,7 +399,7 @@ static void msm_set_clock_rate_for_bus_mode(struct sdhc= i_host *host, msm_host->clk_rate =3D desired_rate; =20 pr_debug("%s: Setting clock at rate %lu at timing %d\n", - mmc_hostname(host->mmc), achieved_rate, curr_ios.timing); + mmc_hostname(host->mmc), achieved_rate, timing); } =20 /* Platform specific tuning */ @@ -1239,7 +1241,7 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) */ if (host->flags & SDHCI_HS400_TUNING) { sdhci_msm_hc_select_mode(host); - msm_set_clock_rate_for_bus_mode(host, ios.clock); + msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing); host->flags &=3D ~SDHCI_HS400_TUNING; } =20 @@ -1864,6 +1866,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *ho= st, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + struct mmc_ios ios =3D host->mmc->ios; =20 if (!clock) { host->mmc->actual_clock =3D msm_host->clk_rate =3D 0; @@ -1872,7 +1875,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *ho= st, unsigned int clock) =20 sdhci_msm_hc_select_mode(host); =20 - msm_set_clock_rate_for_bus_mode(host, clock); + msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing); out: __sdhci_msm_set_clock(host, clock); } --=20 2.34.1