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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8b2aee9eeeasm293422985a.9.2025.11.14.00.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 00:26:59 -0800 (PST) From: Wenmeng Liu To: rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org, vladimir.zapolskiy@linaro.org, mchehab@kernel.org Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, wenmeng.liu@oss.qualcomm.com Subject: [PATCH v4] media: qcom: camss: Add support for regulator init_load_uA in CSIPHY Date: Fri, 14 Nov 2025 16:26:49 +0800 Message-Id: <20251114082649.4240-1-wenmeng.liu@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: YzRuPkR7axDQi90MiKG3gmb5vtL2l74e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA2NSBTYWx0ZWRfX1SbhuwZ7HqXy gsBHqdySgBhw2XKmjDg93Zw9unXgE1f3FIJdgWBjSBM6OLownxoarN5VrRn31UQkplj1EAJVPEa dRJIXA0ooI3vzuY5RlgVXY6QBQlmA9GWFTQq1nW+8dX+XCHSjnggJGIHTZvD0YhDnj+F7947ZGW NgSWQHncUA1LemBrP4V9WycaHU1bogvQAYhGFER1kYccuO5rwm0rLO5esTUmrR83tujTF5k5Pq6 ep9lb2ktma+yXzXfGv8vxlFeSqtzHCAJmermoiz6CdrEGma20Xoz3grVZpT8rLs/gXCZArL+SE8 zlBlbCRMLD0MlST+NSijS7/FQ6wF+mSkEAKEcikde//EvYjBkfZLeX/M8ClNCl5OySiluPvdFLK lsbgyX1Yop17IO+u3p4vSynqBrcY9A== X-Authority-Analysis: v=2.4 cv=MNdtWcZl c=1 sm=1 tr=0 ts=6916e7dc cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=5sd4MONqg-jDtnBtIU4A:9 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: YzRuPkR7axDQi90MiKG3gmb5vtL2l74e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_02,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140065 Content-Type: text/plain; charset="utf-8" Some Qualcomm regulators are configured with initial mode as HPM (High Power Mode), which may lead to higher power consumption. To reduce power usage, it's preferable to set the initial mode to LPM (Low Power Mode). To ensure the regulator can switch from LPM to HPM when needed, this patch adds current load configuration for CAMSS CSIPHY. This allows the regulator framework to scale the mode dynamically based on the load requirement. The current default value for current is uninitialized or random. To address this, initial current values are added for the following platforms: MSM8916, MSM8939, MSM8953, MSM8996, QCM2290, SDM670, SM8250, SC7280, SM8550, SM8650, QCS8300, SA8775P and X1E80100. For SDM660, SDM845, SC8280XP the value is set to 0, indicating that no default current value is configured, the other values are derived from the power grid. Signed-off-by: Wenmeng Liu --- Changes in v4: - Add MSM8939 SM8650 support. - Link to v3:https://lore.kernel.org/all/20250912103631.1184-1-wenmeng.liu@= oss.qualcomm.com/ Changes in v3: - Use devm_regulator_bulk_get_const instead of devm_regulator_bulk_get. - Set the default current value to 0. - Refactor the code to minimize data copying, and support more platform-spe= cific values. - Link to v2: https://lore.kernel.org/all/20250729-camss_csiphy_current-v2-= 1-da3c72a2055c@quicinc.com/ Changes in v2: - Change the source of the current value from DTS to CAMSS resource - Link to v1: https://lore.kernel.org/all/20250620040736.3032667-1-quic_wen= mliu@quicinc.com/ --- .../media/platform/qcom/camss/camss-csid.c | 18 +- .../media/platform/qcom/camss/camss-csiphy.c | 19 +- drivers/media/platform/qcom/camss/camss.c | 328 ++++++++++++++---- drivers/media/platform/qcom/camss/camss.h | 2 +- 4 files changed, 265 insertions(+), 102 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 5284b5857368..ed1820488c98 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1187,24 +1187,12 @@ int msm_csid_subdev_init(struct camss *camss, struc= t csid_device *csid, =20 /* Regulator */ for (i =3D 0; i < ARRAY_SIZE(res->regulators); i++) { - if (res->regulators[i]) + if (res->regulators[i].supply) csid->num_supplies++; } =20 - if (csid->num_supplies) { - csid->supplies =3D devm_kmalloc_array(camss->dev, - csid->num_supplies, - sizeof(*csid->supplies), - GFP_KERNEL); - if (!csid->supplies) - return -ENOMEM; - } - - for (i =3D 0; i < csid->num_supplies; i++) - csid->supplies[i].supply =3D res->regulators[i]; - - ret =3D devm_regulator_bulk_get(camss->dev, csid->num_supplies, - csid->supplies); + ret =3D devm_regulator_bulk_get_const(camss->dev, csid->num_supplies, + res->regulators, &csid->supplies); if (ret) return ret; =20 diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index a734fb7dde0a..62623393f414 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -695,24 +695,13 @@ int msm_csiphy_subdev_init(struct camss *camss, =20 /* CSIPHY supplies */ for (i =3D 0; i < ARRAY_SIZE(res->regulators); i++) { - if (res->regulators[i]) + if (res->regulators[i].supply) csiphy->num_supplies++; } =20 - if (csiphy->num_supplies) { - csiphy->supplies =3D devm_kmalloc_array(camss->dev, - csiphy->num_supplies, - sizeof(*csiphy->supplies), - GFP_KERNEL); - if (!csiphy->supplies) - return -ENOMEM; - } - - for (i =3D 0; i < csiphy->num_supplies; i++) - csiphy->supplies[i].supply =3D res->regulators[i]; - - ret =3D devm_regulator_bulk_get(camss->dev, csiphy->num_supplies, - csiphy->supplies); + if (csiphy->num_supplies > 0) + ret =3D devm_regulator_bulk_get_const(camss->dev, csiphy->num_supplies, + res->regulators, &csiphy->supplies); return ret; } =20 diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index fcc2b2c3cba0..6cfb71fcd861 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -73,7 +73,9 @@ static const struct camss_subdev_resources csiphy_res_8x1= 6[] =3D { static const struct camss_subdev_resources csid_res_8x16[] =3D { /* CSID0 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 40000 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, .clock_rate =3D { { 0 }, @@ -95,7 +97,9 @@ static const struct camss_subdev_resources csid_res_8x16[= ] =3D { =20 /* CSID1 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 40000 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, .clock_rate =3D { { 0 }, @@ -157,7 +161,9 @@ static const struct camss_subdev_resources vfe_res_8x16= [] =3D { static const struct camss_subdev_resources csiphy_res_8x39[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 40000 } + }, .clock =3D { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, .clock_rate =3D { { 0 }, { 40000000, 80000000 }, @@ -174,7 +180,9 @@ static const struct camss_subdev_resources csiphy_res_8= x39[] =3D { =20 /* CSIPHY1 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 40000 } + }, .clock =3D { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, .clock_rate =3D { { 0 }, { 40000000, 80000000 }, @@ -300,7 +308,9 @@ static const struct camss_subdev_resources vfe_res_8x39= [] =3D { static const struct camss_subdev_resources csid_res_8x53[] =3D { /* CSID0 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 9900 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, .clock_rate =3D { { 0 }, @@ -323,7 +333,9 @@ static const struct camss_subdev_resources csid_res_8x5= 3[] =3D { =20 /* CSID1 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 9900 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, .clock_rate =3D { { 0 }, @@ -346,7 +358,9 @@ static const struct camss_subdev_resources csid_res_8x5= 3[] =3D { =20 /* CSID2 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 9900 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, .clock_rate =3D { { 0 }, @@ -507,7 +521,9 @@ static const struct camss_subdev_resources csiphy_res_8= x96[] =3D { static const struct camss_subdev_resources csid_res_8x96[] =3D { /* CSID0 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 80160 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, .clock_rate =3D { { 0 }, @@ -529,7 +545,9 @@ static const struct camss_subdev_resources csid_res_8x9= 6[] =3D { =20 /* CSID1 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 80160 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, .clock_rate =3D { { 0 }, @@ -551,7 +569,9 @@ static const struct camss_subdev_resources csid_res_8x9= 6[] =3D { =20 /* CSID2 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 80160 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, .clock_rate =3D { { 0 }, @@ -573,7 +593,9 @@ static const struct camss_subdev_resources csid_res_8x9= 6[] =3D { =20 /* CSID3 */ { - .regulators =3D { "vdda" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 80160 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" }, .clock_rate =3D { { 0 }, @@ -661,7 +683,10 @@ static const struct camss_subdev_resources vfe_res_8x9= 6[] =3D { static const struct camss_subdev_resources csiphy_res_2290[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdd-csiphy-1p2", "vdd-csiphy-1p8" }, + .regulators =3D { + { .supply =3D "vdd-csiphy-1p2", .init_load_uA =3D 26700 }, + { .supply =3D "vdd-csiphy-1p8", .init_load_uA =3D 2600 } + }, .clock =3D { "top_ahb", "ahb", "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 0 }, { 0 }, @@ -678,7 +703,10 @@ static const struct camss_subdev_resources csiphy_res_= 2290[] =3D { =20 /* CSIPHY1 */ { - .regulators =3D { "vdd-csiphy-1p2", "vdd-csiphy-1p8" }, + .regulators =3D { + { .supply =3D "vdd-csiphy-1p2", .init_load_uA =3D 26700 }, + { .supply =3D "vdd-csiphy-1p8", .init_load_uA =3D 2600 } + }, .clock =3D { "top_ahb", "ahb", "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 0 }, { 0 }, @@ -854,7 +882,10 @@ static const struct camss_subdev_resources csiphy_res_= 660[] =3D { static const struct camss_subdev_resources csid_res_660[] =3D { /* CSID0 */ { - .regulators =3D { "vdda", "vdd_sec" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 0 }, + { .supply =3D "vdd_sec", .init_load_uA =3D 0 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", "cphy_csid0" }, @@ -879,7 +910,10 @@ static const struct camss_subdev_resources csid_res_66= 0[] =3D { =20 /* CSID1 */ { - .regulators =3D { "vdda", "vdd_sec" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 0 }, + { .supply =3D "vdd_sec", .init_load_uA =3D 0 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", "cphy_csid1" }, @@ -904,7 +938,10 @@ static const struct camss_subdev_resources csid_res_66= 0[] =3D { =20 /* CSID2 */ { - .regulators =3D { "vdda", "vdd_sec" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 0 }, + { .supply =3D "vdd_sec", .init_load_uA =3D 0 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", "cphy_csid2" }, @@ -929,7 +966,10 @@ static const struct camss_subdev_resources csid_res_66= 0[] =3D { =20 /* CSID3 */ { - .regulators =3D { "vdda", "vdd_sec" }, + .regulators =3D { + { .supply =3D "vdda", .init_load_uA =3D 0 }, + { .supply =3D "vdd_sec", .init_load_uA =3D 0 } + }, .clock =3D { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", "cphy_csid3" }, @@ -1026,7 +1066,10 @@ static const struct camss_subdev_resources vfe_res_6= 60[] =3D { static const struct camss_subdev_resources csiphy_res_670[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 42800 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 13900 } + }, .clock =3D { "soc_ahb", "cpas_ahb", "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 0 }, @@ -1044,7 +1087,10 @@ static const struct camss_subdev_resources csiphy_re= s_670[] =3D { =20 /* CSIPHY1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 42800 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 13900 } + }, .clock =3D { "soc_ahb", "cpas_ahb", "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 0 }, @@ -1062,7 +1108,10 @@ static const struct camss_subdev_resources csiphy_re= s_670[] =3D { =20 /* CSIPHY2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 42800 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 13900 } + }, .clock =3D { "soc_ahb", "cpas_ahb", "csiphy2", "csiphy2_timer" }, .clock_rate =3D { { 0 }, @@ -1302,7 +1351,10 @@ static const struct camss_subdev_resources csiphy_re= s_845[] =3D { static const struct camss_subdev_resources csid_res_845[] =3D { /* CSID0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe0", "vfe0_src", "vfe0_cphy_rx", "csi0", @@ -1327,7 +1379,10 @@ static const struct camss_subdev_resources csid_res_= 845[] =3D { =20 /* CSID1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe1", "vfe1_src", "vfe1_cphy_rx", "csi1", @@ -1352,7 +1407,10 @@ static const struct camss_subdev_resources csid_res_= 845[] =3D { =20 /* CSID2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe_lite", "vfe_lite_src", "vfe_lite_cphy_rx", "csi2", @@ -1464,7 +1522,10 @@ static const struct camss_subdev_resources vfe_res_8= 45[] =3D { static const struct camss_subdev_resources csiphy_res_8250[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 17500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 10000 } + }, .clock =3D { "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 400000000 }, { 300000000 } }, @@ -1478,7 +1539,10 @@ static const struct camss_subdev_resources csiphy_re= s_8250[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 17500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 10000 } + }, .clock =3D { "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 400000000 }, { 300000000 } }, @@ -1492,7 +1556,10 @@ static const struct camss_subdev_resources csiphy_re= s_8250[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 17500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 10000 } + }, .clock =3D { "csiphy2", "csiphy2_timer" }, .clock_rate =3D { { 400000000 }, { 300000000 } }, @@ -1506,7 +1573,10 @@ static const struct camss_subdev_resources csiphy_re= s_8250[] =3D { }, /* CSIPHY3 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 17500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 10000 } + }, .clock =3D { "csiphy3", "csiphy3_timer" }, .clock_rate =3D { { 400000000 }, { 300000000 } }, @@ -1520,7 +1590,10 @@ static const struct camss_subdev_resources csiphy_re= s_8250[] =3D { }, /* CSIPHY4 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 17500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 10000 } + }, .clock =3D { "csiphy4", "csiphy4_timer" }, .clock_rate =3D { { 400000000 }, { 300000000 } }, @@ -1534,7 +1607,10 @@ static const struct camss_subdev_resources csiphy_re= s_8250[] =3D { }, /* CSIPHY5 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 17500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 10000 } + }, .clock =3D { "csiphy5", "csiphy5_timer" }, .clock_rate =3D { { 400000000 }, { 300000000 } }, @@ -1748,7 +1824,10 @@ static const struct resources_icc icc_res_sm8250[] = =3D { static const struct camss_subdev_resources csiphy_res_7280[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 16100 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 9000 } + }, =20 .clock =3D { "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 300000000, 400000000 }, @@ -1763,7 +1842,10 @@ static const struct camss_subdev_resources csiphy_re= s_7280[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 16100 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 9000 } + }, =20 .clock =3D { "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 300000000, 400000000 }, @@ -1778,7 +1860,10 @@ static const struct camss_subdev_resources csiphy_re= s_7280[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 16100 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 9000 } + }, =20 .clock =3D { "csiphy2", "csiphy2_timer" }, .clock_rate =3D { { 300000000, 400000000 }, @@ -1793,7 +1878,10 @@ static const struct camss_subdev_resources csiphy_re= s_7280[] =3D { }, /* CSIPHY3 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 16100 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 9000 } + }, =20 .clock =3D { "csiphy3", "csiphy3_timer" }, .clock_rate =3D { { 300000000, 400000000 }, @@ -1808,7 +1896,10 @@ static const struct camss_subdev_resources csiphy_re= s_7280[] =3D { }, /* CSIPHY4 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 16100 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 9000 } + }, =20 .clock =3D { "csiphy4", "csiphy4_timer" }, .clock_rate =3D { { 300000000, 400000000 }, @@ -2121,7 +2212,10 @@ static const struct camss_subdev_resources csiphy_re= s_sc8280xp[] =3D { static const struct camss_subdev_resources csid_res_sc8280xp[] =3D { /* CSID0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2137,7 +2231,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2153,7 +2250,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2169,7 +2269,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID3 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe3_csid", "vfe3_cphy_rx", "vfe3", "vfe3_axi" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2185,7 +2288,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID_LITE0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2201,7 +2307,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID_LITE1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2217,7 +2326,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID_LITE2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe_lite2_csid", "vfe_lite2_cphy_rx", "vfe_lite2" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2233,7 +2345,10 @@ static const struct camss_subdev_resources csid_res_= sc8280xp[] =3D { }, /* CSID_LITE3 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 0 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 0 } + }, .clock =3D { "vfe_lite3_csid", "vfe_lite3_cphy_rx", "vfe_lite3" }, .clock_rate =3D { { 400000000, 480000000, 600000000 }, { 0 }, @@ -2434,7 +2549,10 @@ static const struct resources_icc icc_res_sc8280xp[]= =3D { static const struct camss_subdev_resources csiphy_res_8550[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 32200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18000 } + }, .clock =3D { "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2448,7 +2566,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 32200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18000 } + }, .clock =3D { "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2462,7 +2583,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 32200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18000 } + }, .clock =3D { "csiphy2", "csiphy2_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2476,7 +2600,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY3 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 32200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18000 } + }, .clock =3D { "csiphy3", "csiphy3_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2490,7 +2617,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY4 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 37900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18600 } + }, .clock =3D { "csiphy4", "csiphy4_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2504,7 +2634,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY5 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 32200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18000 } + }, .clock =3D { "csiphy5", "csiphy5_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2518,7 +2651,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY6 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 37900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18600 } + }, .clock =3D { "csiphy6", "csiphy6_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2532,7 +2668,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { }, /* CSIPHY7 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 32200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18000 } + }, .clock =3D { "csiphy7", "csiphy7_timer" }, .clock_rate =3D { { 400000000, 480000000 }, { 400000000 } }, @@ -2763,7 +2902,10 @@ static const struct resources_icc icc_res_sm8550[] = =3D { static const struct camss_subdev_resources csiphy_res_sm8650[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", }, + .regulators =3D { + { .supply =3D "vdd-csiphy01-0p9", .init_load_uA =3D 88000 }, + { .supply =3D "vdd-csiphy01-1p2", .init_load_uA =3D 17800 }, + }, .clock =3D { "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 400000000 }, { 400000000 } }, @@ -2777,7 +2919,10 @@ static const struct camss_subdev_resources csiphy_re= s_sm8650[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", }, + .regulators =3D { + { .supply =3D "vdd-csiphy01-0p9", .init_load_uA =3D 88000 }, + { .supply =3D "vdd-csiphy01-1p2", .init_load_uA =3D 17800 }, + }, .clock =3D { "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 400000000 }, { 400000000 } }, @@ -2791,7 +2936,10 @@ static const struct camss_subdev_resources csiphy_re= s_sm8650[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", }, + .regulators =3D { + { .supply =3D "vdd-csiphy24-0p9", .init_load_uA =3D 147000 }, + { .supply =3D "vdd-csiphy24-1p2", .init_load_uA =3D 24400 }, + }, .clock =3D { "csiphy2", "csiphy2_timer" }, .clock_rate =3D { { 400000000 }, { 400000000 } }, @@ -2805,7 +2953,10 @@ static const struct camss_subdev_resources csiphy_re= s_sm8650[] =3D { }, /* CSIPHY3 */ { - .regulators =3D { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", }, + .regulators =3D { + { .supply =3D "vdd-csiphy35-0p9", .init_load_uA =3D 88000 }, + { .supply =3D "vdd-csiphy35-1p2", .init_load_uA =3D 17800 }, + }, .clock =3D { "csiphy3", "csiphy3_timer" }, .clock_rate =3D { { 400000000 }, { 400000000 } }, @@ -2819,7 +2970,10 @@ static const struct camss_subdev_resources csiphy_re= s_sm8650[] =3D { }, /* CSIPHY4 */ { - .regulators =3D { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", }, + .regulators =3D { + { .supply =3D "vdd-csiphy24-0p9", .init_load_uA =3D 147000 }, + { .supply =3D "vdd-csiphy24-1p2", .init_load_uA =3D 24400 }, + }, .clock =3D { "csiphy4", "csiphy4_timer" }, .clock_rate =3D { { 400000000 }, { 400000000 } }, @@ -2833,7 +2987,10 @@ static const struct camss_subdev_resources csiphy_re= s_sm8650[] =3D { }, /* CSIPHY5 */ { - .regulators =3D { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", }, + .regulators =3D { + { .supply =3D "vdd-csiphy35-0p9", .init_load_uA =3D 88000 }, + { .supply =3D "vdd-csiphy35-1p2", .init_load_uA =3D 17800 }, + }, .clock =3D { "csiphy5", "csiphy5_timer" }, .clock_rate =3D { { 400000000 }, { 400000000 } }, @@ -3074,7 +3231,10 @@ static const struct resources_icc icc_res_sm8650[] = =3D { static const struct camss_subdev_resources csiphy_res_8300[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, =20 .clock =3D { "csiphy_rx", "csiphy0", "csiphy0_timer" }, .clock_rate =3D { @@ -3092,7 +3252,10 @@ static const struct camss_subdev_resources csiphy_re= s_8300[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, =20 .clock =3D { "csiphy_rx", "csiphy1", "csiphy1_timer" }, .clock_rate =3D { @@ -3110,7 +3273,10 @@ static const struct camss_subdev_resources csiphy_re= s_8300[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, =20 .clock =3D { "csiphy_rx", "csiphy2", "csiphy2_timer" }, .clock_rate =3D { @@ -3131,7 +3297,10 @@ static const struct camss_subdev_resources csiphy_re= s_8300[] =3D { static const struct camss_subdev_resources csiphy_res_8775p[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, .clock =3D { "csiphy_rx", "csiphy0", "csiphy0_timer"}, .clock_rate =3D { { 400000000 }, @@ -3148,7 +3317,10 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, .clock =3D { "csiphy_rx", "csiphy1", "csiphy1_timer"}, .clock_rate =3D { { 400000000 }, @@ -3165,7 +3337,10 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, .clock =3D { "csiphy_rx", "csiphy2", "csiphy2_timer"}, .clock_rate =3D { { 400000000 }, @@ -3182,7 +3357,10 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, /* CSIPHY3 */ { - .regulators =3D { "vdda-phy", "vdda-pll" }, + .regulators =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 15900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 8900 } + }, .clock =3D { "csiphy_rx", "csiphy3", "csiphy3_timer"}, .clock_rate =3D { { 400000000 }, @@ -3535,8 +3713,10 @@ static const struct resources_icc icc_res_sa8775p[] = =3D { static const struct camss_subdev_resources csiphy_res_x1e80100[] =3D { /* CSIPHY0 */ { - .regulators =3D { "vdd-csiphy-0p8", - "vdd-csiphy-1p2" }, + .regulators =3D { + { .supply =3D "vdd-csiphy-0p8", .init_load_uA =3D 105000 }, + { .supply =3D "vdd-csiphy-1p2", .init_load_uA =3D 58900 } + }, .clock =3D { "csiphy0", "csiphy0_timer" }, .clock_rate =3D { { 300000000, 400000000, 480000000 }, { 266666667, 400000000 } }, @@ -3550,8 +3730,10 @@ static const struct camss_subdev_resources csiphy_re= s_x1e80100[] =3D { }, /* CSIPHY1 */ { - .regulators =3D { "vdd-csiphy-0p8", - "vdd-csiphy-1p2" }, + .regulators =3D { + { .supply =3D "vdd-csiphy-0p8", .init_load_uA =3D 105000 }, + { .supply =3D "vdd-csiphy-1p2", .init_load_uA =3D 58900 } + }, .clock =3D { "csiphy1", "csiphy1_timer" }, .clock_rate =3D { { 300000000, 400000000, 480000000 }, { 266666667, 400000000 } }, @@ -3565,8 +3747,10 @@ static const struct camss_subdev_resources csiphy_re= s_x1e80100[] =3D { }, /* CSIPHY2 */ { - .regulators =3D { "vdd-csiphy-0p8", - "vdd-csiphy-1p2" }, + .regulators =3D { + { .supply =3D "vdd-csiphy-0p8", .init_load_uA =3D 105000 }, + { .supply =3D "vdd-csiphy-1p2", .init_load_uA =3D 58900 } + }, .clock =3D { "csiphy2", "csiphy2_timer" }, .clock_rate =3D { { 300000000, 400000000, 480000000 }, { 266666667, 400000000 } }, @@ -3580,8 +3764,10 @@ static const struct camss_subdev_resources csiphy_re= s_x1e80100[] =3D { }, /* CSIPHY4 */ { - .regulators =3D { "vdd-csiphy-0p8", - "vdd-csiphy-1p2" }, + .regulators =3D { + { .supply =3D "vdd-csiphy-0p8", .init_load_uA =3D 105000 }, + { .supply =3D "vdd-csiphy-1p2", .init_load_uA =3D 58900 } + }, .clock =3D { "csiphy4", "csiphy4_timer" }, .clock_rate =3D { { 300000000, 400000000, 480000000 }, { 266666667, 400000000 } }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 9d9a62640e25..e34f06b4e153 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -44,7 +44,7 @@ #define CAMSS_INIT_BUF_COUNT 2 =20 struct camss_subdev_resources { - char *regulators[CAMSS_RES_MAX]; + struct regulator_bulk_data regulators[CAMSS_RES_MAX]; char *clock[CAMSS_RES_MAX]; char *clock_for_reset[CAMSS_RES_MAX]; u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX]; --=20 2.34.1