From nobody Tue Feb 10 04:15:27 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF3312F4A1B for ; Fri, 14 Nov 2025 07:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763107145; cv=none; b=rCPPWx4pAY81ybhhFPecbCIpLH+87YN7RlEUC0/LwBqz/+tJGPFYQODa8E0GryVs6+6lE1NlbmbwZGp7CZgQDnpZnHVUv9psfQQgLVHOgWK8I7E5ruZHx7OAEW0P2zsMAbtdUAFMHbkdYqIA4EzbETqePYmOuhzogC4Ob5p4Foo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763107145; c=relaxed/simple; bh=cFLV533h4O3rO3j2a2nEJRzLpD/2ov1h5vOs874CNdY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h/xx7ikp32FtMQxiI4WW8VNke89MJf0lk61MDvMlNkaVlcSy1yxHHcekcFCsVpkxhxaUlW/tW+39ZXBZQOKO4gvqpR2FSmFm2vsevtd7fvlUktueUUPfdEB3MADNvY1xnJ+XIZfzQOhGfzwbq9Cm2VwsK+kLSkAjH4yrzakwOvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UbY4UR20; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UbY4UR20" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4775ae5684fso8555635e9.1 for ; Thu, 13 Nov 2025 23:59:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763107141; x=1763711941; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CkzCeEb3navO40uJNEmomf2mfxM1QxS5KFNp5J+6KA4=; b=UbY4UR20BV5UEFH5beN+v58ejsl7IQrKY6Eq8OAIpGPJSDv1ZBrXleVOvWRSqARQ0v BQukVnxSOISmtME4RuecwXIvlBlUmRstWmOOhW/H6CEkNxFNmy4oB+fXK6hwdoCUISAW 8zaBxXKfsKQUh0RnGfCHGNBdEOdT3oqILqMavQ96NxCtbujAqp1DMbSBA9aGp90Be3sQ NHPhxI2d0MLAJDp1TeRWvrg8qiqkWcNzIiQiX5/T/6VCKXumcS0gAP7rwJhPsvPPSkqP hU9wQyAVHTZr3ETH1FjUjAKn7wjRTxFLaDK8kzYVYrR+a8P2jNgbu3R+bdCycYGKpE4e oxBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763107141; x=1763711941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CkzCeEb3navO40uJNEmomf2mfxM1QxS5KFNp5J+6KA4=; b=B+mrop9fSMDu2LIe5UuziF1yt/CR1hZxJ/9WqHVKgwm7PJWUKMIimiaO/vSTCsXDVx geDZ4krC9NJQOoDhaanm8tsVlfPkGwRqx7hFgtU+YQH6ZTwmzMYAkJDVWAq40oyUXP/B 8m/vF3qDz3MGqfVU0Zqqx+2qD3bJBUMesX0lIGKRqAd17ZQ2wF8VlhTCgf6Kpsb04rn/ H5FklBE3+la7J8lTdJzpTQ+ADutV3+Bux5vJCfMNRDBQWA0BeUIp6atbFqRwV50EvKuX 6AkkK4TqfXFGbiUnraXyco0pzx0yl/U71Uhqb5P4PXjStlUVlFXRCBmts8JNU07pj3dU PT7w== X-Forwarded-Encrypted: i=1; AJvYcCWgUXDG3zFDWQK4q60iwCdJbx2ar2QYmwdl5i/zJV+CMUkKYldQTMGxfrVF6W4VBggQP4BrxsDstNS8pGM=@vger.kernel.org X-Gm-Message-State: AOJu0YwYfVfPkwtbded3CfjO+MWrMkXoMc8X++I3Wgx94yeQV/mk/9n4 CdZLWuL5IGLLcwYhhTOWQuETNX3YnjdCmSPp2hpNJTXBuIcS3SeU0a69hAPoKA== X-Gm-Gg: ASbGnctfzcxWk9UcS0ZN+I/ulMv4laAeVd7obiCq/902HLfMxGqyn/WzryWySIfPmGT GukoDm5uyerhu0y2IBrLD4iifqNjsPbNLVFMOqKBIwapl3J0+Uhd7LO9y2ATG0Tq/FYy4ZkZUfC HHQdmcHCpK6AippQTifplrqKlK3P3wQfI8p/oWcvkgcOf6go+im4T/uY3tVJmh3GFa6Oeab9ygW eJxAIh92DqAVhEF47Db1K2mjx8t1VW6h3n4gRQrm25LEiGq/3ehT/0nGnXTTTMnB7U7kCqE6r5d H2YkIoHlwStK3gnYQnweAF0KlHFOgdbpRywNCN7aJZQCfScHPj3mwRc3nE+JGItT6HiDNWKO7O9 YdSKUP6ixwApQPSWSa8KqEO1keJUo2l0KkxhplEPdKkXyAk/YfEN8kUqnN+wnJwBpWtjTxOkoaz G/gQ4WTotWhqplIsc5AUQ1siGoaPUi/QZKG/bykHt1GqxsXlTf58Mb6QLuT303ZuqET5aOuSwDa 9PhPuXPtD7ia5xW X-Google-Smtp-Source: AGHT+IEVkGZ6INx5GNdqNHodG0mme/hMs8mtdPy04E7Q4DZtbZ697iy8gTURwupoXOgMmgDqFRcb6Q== X-Received: by 2002:a05:600c:a04:b0:46e:4a13:e6c6 with SMTP id 5b1f17b1804b1-4778fe9b384mr19462065e9.19.1763107141038; Thu, 13 Nov 2025 23:59:01 -0800 (PST) Received: from localhost.localdomain (host86-162-200-138.range86-162.btcentralplus.com. [86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4778c847bbasm76347895e9.1.2025.11.13.23.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 23:59:00 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Biju Das , Lad Prabhakar , Kuninori Morimoto , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai Cc: linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Biju Das Subject: [PATCH v2 4/5] ASoC: renesas: rz-ssi: Add support for 24 bits sample width Date: Fri, 14 Nov 2025 07:58:51 +0000 Message-ID: <20251114075856.4751-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114075856.4751-1-biju.das.jz@bp.renesas.com> References: <20251114075856.4751-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for 24 bits sample format width for RZ/G2L SoCs. Signed-off-by: Biju Das --- v1->v2: * Updated rz_ssi_clk_setup() to make ssicr assignment in single line for 24-bit sample width. * Updated rz_ssi_dma_slave_config() to check for 16-bit sample width, that will allow us to support 32-bit smaple width later without any code change. --- sound/soc/renesas/rz-ssi.c | 75 +++++++++++++++++++++++++++++--------- 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/sound/soc/renesas/rz-ssi.c b/sound/soc/renesas/rz-ssi.c index 55aefff8857d..3ec7c9875b43 100644 --- a/sound/soc/renesas/rz-ssi.c +++ b/sound/soc/renesas/rz-ssi.c @@ -38,6 +38,7 @@ #define SSICR_MST BIT(14) #define SSICR_BCKP BIT(13) #define SSICR_LRCKP BIT(12) +#define SSICR_PDTA BIT(9) #define SSICR_CKDV(x) (((x) & 0xf) << 4) #define SSICR_TEN BIT(1) #define SSICR_REN BIT(0) @@ -74,7 +75,7 @@ #define PREALLOC_BUFFER_MAX (SZ_32K) =20 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ -#define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE +#define SSI_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) #define SSI_CHAN_MIN 2 #define SSI_CHAN_MAX 2 #define SSI_FIFO_DEPTH 32 @@ -294,11 +295,24 @@ static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, = unsigned int rate, } =20 /* - * DWL: Data Word Length =3D 16 bits + * DWL: Data Word Length =3D {16, 24} bits * SWL: System Word Length =3D 32 bits */ ssicr |=3D SSICR_CKDV(clk_ckdv); - ssicr |=3D SSICR_DWL(1) | SSICR_SWL(3); + switch (ssi->hw_params_cache.sample_width) { + case 16: + ssicr |=3D SSICR_DWL(1); + break; + case 24: + ssicr |=3D SSICR_DWL(5) | SSICR_PDTA; + break; + default: + dev_err(ssi->dev, "Not support %u data width", + ssi->hw_params_cache.sample_width); + return -EINVAL; + } + + ssicr |=3D SSICR_SWL(3); rz_ssi_reg_writel(ssi, SSICR, ssicr); rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); =20 @@ -455,7 +469,6 @@ static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, str= uct rz_ssi_stream *strm) { struct snd_pcm_substream *substream =3D strm->substream; struct snd_pcm_runtime *runtime; - u16 *buf; int fifo_samples; int frames_left; int samples; @@ -490,12 +503,23 @@ static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, s= truct rz_ssi_stream *strm) break; =20 /* calculate new buffer index */ - buf =3D (u16 *)runtime->dma_area; - buf +=3D strm->buffer_pos * runtime->channels; + if (ssi->hw_params_cache.sample_width =3D=3D 16) { + u16 *buf; =20 - /* Note, only supports 16-bit samples */ - for (i =3D 0; i < samples; i++) - *buf++ =3D (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); + buf =3D (u16 *)runtime->dma_area; + buf +=3D strm->buffer_pos * runtime->channels; + + for (i =3D 0; i < samples; i++) + *buf++ =3D (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); + } else { + u32 *buf; + + buf =3D (u32 *)runtime->dma_area; + buf +=3D strm->buffer_pos * runtime->channels; + + for (i =3D 0; i < samples; i++) + *buf++ =3D rz_ssi_reg_readl(ssi, SSIFRDR); + } =20 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); rz_ssi_pointer_update(strm, samples / runtime->channels); @@ -513,7 +537,6 @@ static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, str= uct rz_ssi_stream *strm) int frames_left; int i; u32 ssifsr; - u16 *buf; =20 if (!rz_ssi_stream_is_valid(ssi, strm)) return -EINVAL; @@ -542,12 +565,23 @@ static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, s= truct rz_ssi_stream *strm) return 0; =20 /* calculate new buffer index */ - buf =3D (u16 *)(runtime->dma_area); - buf +=3D strm->buffer_pos * runtime->channels; + if (ssi->hw_params_cache.sample_width =3D=3D 16) { + u16 *buf; + + buf =3D (u16 *)(runtime->dma_area); + buf +=3D strm->buffer_pos * runtime->channels; + + for (i =3D 0; i < samples; i++) + rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); + } else { + u32 *buf; =20 - /* Note, only supports 16-bit samples */ - for (i =3D 0; i < samples; i++) - rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); + buf =3D (u32 *)(runtime->dma_area); + buf +=3D strm->buffer_pos * runtime->channels; + + for (i =3D 0; i < samples; i++) + rz_ssi_reg_writel(ssi, SSIFTDR, *buf++); + } =20 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); rz_ssi_pointer_update(strm, samples / runtime->channels); @@ -658,8 +692,13 @@ static int rz_ssi_dma_slave_config(struct rz_ssi_priv = *ssi, cfg.direction =3D is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; cfg.dst_addr =3D ssi->phys + SSIFTDR; cfg.src_addr =3D ssi->phys + SSIFRDR; - cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; - cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; + if (ssi->hw_params_cache.sample_width =3D=3D 16) { + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; + } else { + cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + } =20 return dmaengine_slave_config(dma_ch, &cfg); } @@ -977,7 +1016,7 @@ static int rz_ssi_dai_hw_params(struct snd_pcm_substre= am *substream, unsigned int rate =3D params_rate(params); int ret; =20 - if (sample_bits !=3D 16) { + if (!(sample_bits =3D=3D 16 || sample_bits =3D=3D 24)) { dev_err(ssi->dev, "Unsupported sample width: %d\n", sample_bits); return -EINVAL; --=20 2.43.0