From nobody Sat Feb 7 15:40:08 2026 Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4FBF19F137 for ; Fri, 14 Nov 2025 07:12:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.113 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104372; cv=none; b=c52GmwM7G+aQR5JYzOg9mtaMgpyuiUjuaTdgwIi9O2Zwj5v/jybSdmANi2ugf2IfypbIBMUec4uXNEKPc0eoc99lrrw94IYJTvCPCK807wLkmhQmMnCzqH8bf8KJOjX2bNmNlzzj/kR8xHuwrzWKJhgG3P72cS5JaalO5LvoHYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104372; c=relaxed/simple; bh=zTsUYSlTnptpIO0350InXtax5/cXfffVrYgN/vzFsgc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=sgP5uGZyxnwN2s35y29UNB9Lz8h0edcjPBvvpS5dSD0cn+JUAPG0Uj2Sl+XKifBQCB9IjT0lgu2R/UsxIFSKpBc7DjTM9qFW0ktVySi+YpDgKw8rsbKvnlSE85zE0MSIv/5EHvFLmvBI4IYDuxpKf5P9zbOJRzoygiHEHd5oNeA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=LUGUuGcC; arc=none smtp.client-ip=115.124.30.113 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="LUGUuGcC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1763104367; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=YTe9/5FVy2isOVJ9yMK2C0iA7ENJeT01zWGDUBRghpU=; b=LUGUuGcCydi9ot3f048FQO5z2DmTEUijc/w2a36tKlQjz7bmrc86DL2tGZApVn9StaLCmahOYC7QQB6H4t9Sa72E5L2ob20lXGy1lZ9SSW6f9HUG0jGqcNYIXLMerDeNRfLNRi9GFAb2GrleyGo5Jl3G8V4BhO/kdi1D30ucf0g= Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0WsMGLgd_1763104362 cluster:ay36) by smtp.aliyun-inc.com; Fri, 14 Nov 2025 15:12:47 +0800 From: cp0613@linux.alibaba.com To: anup@brainfault.org, atish.patra@linux.dev, pjw@kernel.org, haibo1.xu@intel.com, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chen Pei Subject: [PATCH] tools: riscv: Fixed misalignment of CSR related definitions Date: Fri, 14 Nov 2025 15:12:15 +0800 Message-ID: <20251114071215.816-1-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Pei The file tools/arch/riscv/include/asm/csr.h borrows from arch/riscv/include/asm/csr.h, and subsequent modifications related to CSR should maintain consistency. Fixes: 16b0bde9a37c ("RISC-V: KVM: Add perf sampling support for guests") Fixes: d1927f64e0e1 ("RISC-V: Fix the typo in Scountovf CSR name") Signed-off-by: Chen Pei --- drivers/perf/riscv_pmu_sbi.c | 2 +- tools/arch/riscv/include/asm/csr.h | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index e255c1b069ec..7dd282da67ce 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1109,7 +1109,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) /* compute hardware counter index */ hidx =3D info->csr - CSR_CYCLE; =20 - /* check if the corresponding bit is set in sscountovf or overflow mask = in shmem */ + /* check if the corresponding bit is set in scountovf or overflow mask i= n shmem */ if (!(overflow & BIT(hidx))) continue; =20 diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/= asm/csr.h index 56d7367ee344..21d8cee04638 100644 --- a/tools/arch/riscv/include/asm/csr.h +++ b/tools/arch/riscv/include/asm/csr.h @@ -167,7 +167,8 @@ #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ (_AC(1, UL) << IRQ_S_TIMER) | \ - (_AC(1, UL) << IRQ_S_EXT)) + (_AC(1, UL) << IRQ_S_EXT) | \ + (_AC(1, UL) << IRQ_PMU_OVF)) =20 /* AIA CSR bits */ #define TOPI_IID_SHIFT 16 @@ -280,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f =20 -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 =20 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 --=20 2.50.1