From nobody Sun Feb 8 06:56:03 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4DA22127E for ; Fri, 14 Nov 2025 00:36:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763080603; cv=none; b=i80bhGQplAbBi/PvJVm/KIb3tCw2AXtGF59kZlKNkqCblLM5QbWID7DhzkQqcsKm854LwiBqwQ98yH9/BsPa3sDzrS2LPpZnOb386bXVYRxNXC1auhe+Yf5NaRbce7KvYCXjTKfBB4CHTKzJfENuuswjZw8iGgEa2BreGQ1p/6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763080603; c=relaxed/simple; bh=9xtrLqirKICH3+v4PSPZR/caXGl7ApwY7DfyxgB1iz8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gMlj0sd1oUtSGkqAMA3Zhjk/YqUf8kFcyUKMWwc6//lwnZql/+/FMfDowHSoo7oDmLCxkrLYPEV4ABUyVipV4SBsVplr/Bcz8QkJ39GwlY74qGaf7Tud+T9Yoe3ZpSG8IbdBzR9v54EmrrM+vanDYNKwpegFHRcfn5KpaFTtqlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=Wx1sKbQp; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Wx1sKbQp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763080600; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QMzO+M2E3B8XBgrzfunENWfEm+Ikh/b2200X6CIHXBc=; b=Wx1sKbQpNPyr4O3ujedSY307/YdxRPpNnS7debh+FEnFU1g45aIwejcLWNsVw1F8z1vkFY VD8lmr0bMdJ7jb5zF2MQ6R3muqfLuUgcnxYOVXXAXl3IB/nJkvvsCy6k/OFFyzT3nTBk7w R76V2QhjqMqkNMZuLCmKb+5E+bMn+IE= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-509-sOEPT50fPD-k9dX9liDM6g-1; Thu, 13 Nov 2025 19:36:36 -0500 X-MC-Unique: sOEPT50fPD-k9dX9liDM6g-1 X-Mimecast-MFC-AGG-ID: sOEPT50fPD-k9dX9liDM6g_1763080595 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id AD7E4180045C; Fri, 14 Nov 2025 00:36:35 +0000 (UTC) Received: from virtlab1023.lab.eng.rdu2.redhat.com (virtlab1023.lab.eng.rdu2.redhat.com [10.8.1.187]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0B2D719560B9; Fri, 14 Nov 2025 00:36:34 +0000 (UTC) From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: kbusch@kernel.org, chang.seok.bae@intel.com Subject: [PATCH 01/10] KVM: emulate: add MOVNTDQA Date: Thu, 13 Nov 2025 19:36:24 -0500 Message-ID: <20251114003633.60689-2-pbonzini@redhat.com> In-Reply-To: <20251114003633.60689-1-pbonzini@redhat.com> References: <20251114003633.60689-1-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" MOVNTDQA is a simple MOV instruction, in fact it has the same characteristics as 0F E7 (MOVNTDQ) other than the aligned-address requirement. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 4e3da5b497b8..43ae4fcb2137 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -4133,7 +4133,7 @@ static const struct gprefix pfx_0f_28_0f_29 =3D { I(Aligned, em_mov), I(Aligned, em_mov), N, N, }; =20 -static const struct gprefix pfx_0f_e7 =3D { +static const struct gprefix pfx_0f_e7_0f_38_2a =3D { N, I(Sse, em_mov), N, N, }; =20 @@ -4431,7 +4431,7 @@ static const struct opcode twobyte_table[256] =3D { /* 0xD0 - 0xDF */ N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, /* 0xE0 - 0xEF */ - N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), + N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7_0f_38_2= a), N, N, N, N, N, N, N, N, /* 0xF0 - 0xFF */ N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N @@ -4458,8 +4458,13 @@ static const struct gprefix three_byte_0f_38_f1 =3D { * byte. */ static const struct opcode opcode_map_0f_38[256] =3D { - /* 0x00 - 0x7f */ - X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), + /* 0x00 - 0x1f */ + X16(N), X16(N), + /* 0x20 - 0x2f */ + X8(N), + X2(N), GP(SrcReg | DstMem | ModRM | Mov | Aligned, &pfx_0f_e7_0f_38_2a), = N, N, N, N, N, + /* 0x30 - 0x7f */ + X16(N), X16(N), X16(N), X16(N), X16(N), /* 0x80 - 0xef */ X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), /* 0xf0 - 0xf1 */ --=20 2.43.5 From nobody Sun Feb 8 06:56:03 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7214221F29 for ; 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charset="utf-8" An irresistible microoptimization (changing accesses to Src2 to just an AND :)) that also frees a bit for AVX in the low flags word. This makes it closer to SSE since both of them can access XMM registers, pointlessly shaving another clock cycle or two (maybe). No functional change intended. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 43ae4fcb2137..57799b5d9da2 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -147,7 +147,7 @@ #define PageTable (1 << 29) /* instruction used to write page table */ #define NotImpl (1 << 30) /* instruction is not implemented */ /* Source 2 operand type */ -#define Src2Shift (31) +#define Src2Shift (32) /* bits 32-36 */ #define Src2None (OpNone << Src2Shift) #define Src2Mem (OpMem << Src2Shift) #define Src2CL (OpCL << Src2Shift) @@ -161,6 +161,7 @@ #define Src2FS (OpFS << Src2Shift) #define Src2GS (OpGS << Src2Shift) #define Src2Mask (OpMask << Src2Shift) +/* free: 37-39 */ #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ #define AlignMask ((u64)7 << 41) #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ --=20 2.43.5 From nobody Sun Feb 8 06:56:03 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98AB7231829 for ; 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Thu, 13 Nov 2025 19:36:38 -0500 X-MC-Unique: CjyF-IB3Nw2iFO67UbPPfQ-1 X-Mimecast-MFC-AGG-ID: CjyF-IB3Nw2iFO67UbPPfQ_1763080597 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 196E0180048E; Fri, 14 Nov 2025 00:36:37 +0000 (UTC) Received: from virtlab1023.lab.eng.rdu2.redhat.com (virtlab1023.lab.eng.rdu2.redhat.com [10.8.1.187]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 815BD19560B9; Fri, 14 Nov 2025 00:36:36 +0000 (UTC) From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: kbusch@kernel.org, chang.seok.bae@intel.com Subject: [PATCH 03/10] KVM: emulate: improve formatting of flags table Date: Thu, 13 Nov 2025 19:36:26 -0500 Message-ID: <20251114003633.60689-4-pbonzini@redhat.com> In-Reply-To: <20251114003633.60689-1-pbonzini@redhat.com> References: <20251114003633.60689-1-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" Align a little better the comments on the right side and list explicitly the bits used by multi-bit fields. No functional change intended. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 57799b5d9da2..28f81346878e 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -81,9 +81,8 @@ */ =20 /* Operand sizes: 8-bit operands or specified/overridden size. */ -#define ByteOp (1<<0) /* 8-bit operands. */ -/* Destination operand type. */ -#define DstShift 1 +#define ByteOp (1<<0) /* 8-bit operands. */ +#define DstShift 1 /* Destination operand type at bits 1-5 */ #define ImplicitOps (OpImplicit << DstShift) #define DstReg (OpReg << DstShift) #define DstMem (OpMem << DstShift) @@ -95,8 +94,7 @@ #define DstDX (OpDX << DstShift) #define DstAccLo (OpAccLo << DstShift) #define DstMask (OpMask << DstShift) -/* Source operand type. */ -#define SrcShift 6 +#define SrcShift 6 /* Source operand type at bits 6-10 */ #define SrcNone (OpNone << SrcShift) #define SrcReg (OpReg << SrcShift) #define SrcMem (OpMem << SrcShift) @@ -119,10 +117,10 @@ #define SrcAccHi (OpAccHi << SrcShift) #define SrcMask (OpMask << SrcShift) #define BitOp (1<<11) -#define MemAbs (1<<12) /* Memory operand is absolute displacemen= t */ +#define MemAbs (1<<12) /* Memory operand is absolute displacement= */ #define String (1<<13) /* String instruction (rep capable) */ #define Stack (1<<14) /* Stack instruction (push/pop) */ -#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms= */ +#define GroupMask (7<<15) /* Group mechanisms, at bits 15-17 */ #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ #define GroupDual (2<<15) /* Alternate decoding of mod =3D=3D 3 */ #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix= */ @@ -131,11 +129,8 @@ #define InstrDual (6<<15) /* Alternate instruction decoding of mod = =3D=3D 3 */ #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ #define Sse (1<<18) /* SSE Vector instruction */ -/* Generic ModRM decode. */ -#define ModRM (1<<19) -/* Destination is only written; never read. */ -#define Mov (1<<20) -/* Misc flags */ +#define ModRM (1<<19) /* Generic ModRM decode. */ +#define Mov (1<<20) /* Destination is only written; never read= . */ #define Prot (1<<21) /* instruction generates #UD if not in prot-mo= de */ #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ @@ -143,11 +138,10 @@ #define Undefined (1<<25) /* No Such Instruction */ #define Lock (1<<26) /* lock prefix is allowed for the instruction = */ #define Priv (1<<27) /* instruction generates #GP if current CPL != =3D 0 */ -#define No64 (1<<28) +#define No64 (1<<28) /* Instruction generates #UD in 64-bit mod= e */ #define PageTable (1 << 29) /* instruction used to write page table */ #define NotImpl (1 << 30) /* instruction is not implemented */ -/* Source 2 operand type */ -#define Src2Shift (32) /* bits 32-36 */ +#define Src2Shift (32) /* Source 2 operand type at bits 32-36 */ #define Src2None (OpNone << Src2Shift) #define Src2Mem (OpMem << Src2Shift) #define Src2CL (OpCL << Src2Shift) @@ -163,11 +157,12 @@ #define Src2Mask (OpMask << Src2Shift) /* free: 37-39 */ #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ -#define AlignMask ((u64)7 << 41) +#define AlignMask ((u64)7 << 41) /* Memory alignment requirement at bit= s 41-43 */ #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) = */ #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. F= XSAVE) */ +/* free: 44 */ #define NoWrite ((u64)1 << 45) /* No writeback */ #define SrcWrite ((u64)1 << 46) /* Write back src operand */ #define NoMod ((u64)1 << 47) /* Mod field is ignored */ --=20 2.43.5 From nobody Sun Feb 8 06:56:03 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3FB722157B for ; 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charset="utf-8" VEX decode will need to set it based on the "pp" bits, so make it a field in the struct rather than a local variable. No functional change intended. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 8 ++++---- arch/x86/kvm/kvm_emulate.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 28f81346878e..7ef791407dbc 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -4761,7 +4761,6 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int int rc =3D X86EMUL_CONTINUE; int mode =3D ctxt->mode; int def_op_bytes, def_ad_bytes, goffset, simd_prefix; - bool op_prefix =3D false; bool has_seg_override =3D false; struct opcode opcode; u16 dummy; @@ -4813,7 +4812,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int for (;;) { switch (ctxt->b =3D insn_fetch(u8, ctxt)) { case 0x66: /* operand-size override */ - op_prefix =3D true; + ctxt->op_prefix =3D true; /* switch between 2/4 bytes */ ctxt->op_bytes =3D def_op_bytes ^ 6; break; @@ -4920,9 +4919,9 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int opcode =3D opcode.u.group[goffset]; break; case Prefix: - if (ctxt->rep_prefix && op_prefix) + if (ctxt->rep_prefix && ctxt->op_prefix) return EMULATION_FAILED; - simd_prefix =3D op_prefix ? 0x66 : ctxt->rep_prefix; + simd_prefix =3D ctxt->op_prefix ? 0x66 : ctxt->rep_prefix; switch (simd_prefix) { case 0x00: opcode =3D opcode.u.gprefix->pfx_no; break; case 0x66: opcode =3D opcode.u.gprefix->pfx_66; break; @@ -5140,6 +5139,7 @@ void init_decode_cache(struct x86_emulate_ctxt *ctxt) ctxt->rip_relative =3D false; ctxt->rex_prefix =3D 0; ctxt->lock_prefix =3D 0; + ctxt->op_prefix =3D false; ctxt->rep_prefix =3D 0; ctxt->regs_valid =3D 0; ctxt->regs_dirty =3D 0; diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 7b5ddb787a25..83af019620e3 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -348,6 +348,7 @@ struct x86_emulate_ctxt { u8 opcode_len; u8 b; u8 intercept; + bool op_prefix; u8 op_bytes; u8 ad_bytes; union { --=20 2.43.5 From nobody Sun Feb 8 06:56:03 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2731C2571A5 for ; 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charset="utf-8" Remove all duplicate handling of register operands, including picking the right register class and fetching it, by extracting a new function that can be used for both REG and MODRM operands. Centralize setting op->orig_val =3D op->val in fetch_register_operand() as well. No functional change intended. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 49 +++++++++++++++--------------------------- 1 file changed, 17 insertions(+), 32 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 7ef791407dbc..6c8d3f786e74 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -1026,6 +1026,7 @@ static void fetch_register_operand(struct operand *op) op->val =3D *(u64 *)op->addr.reg; break; } + op->orig_val =3D op->val; } =20 static int em_fninit(struct x86_emulate_ctxt *ctxt) @@ -1071,16 +1072,9 @@ static int em_fnstsw(struct x86_emulate_ctxt *ctxt) return X86EMUL_CONTINUE; } =20 -static void decode_register_operand(struct x86_emulate_ctxt *ctxt, - struct operand *op) +static void __decode_register_operand(struct x86_emulate_ctxt *ctxt, + struct operand *op, int reg) { - unsigned int reg; - - if (ctxt->d & ModRM) - reg =3D ctxt->modrm_reg; - else - reg =3D (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); - if (ctxt->d & Sse) { op->type =3D OP_XMM; op->bytes =3D 16; @@ -1099,9 +1093,20 @@ static void decode_register_operand(struct x86_emula= te_ctxt *ctxt, op->type =3D OP_REG; op->bytes =3D (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; op->addr.reg =3D decode_register(ctxt, reg, ctxt->d & ByteOp); - fetch_register_operand(op); - op->orig_val =3D op->val; +} + +static void decode_register_operand(struct x86_emulate_ctxt *ctxt, + struct operand *op) +{ + unsigned int reg; + + if (ctxt->d & ModRM) + reg =3D ctxt->modrm_reg; + else + reg =3D (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); + + __decode_register_operand(ctxt, op, reg); } =20 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) @@ -1128,24 +1133,7 @@ static int decode_modrm(struct x86_emulate_ctxt *ctx= t, ctxt->modrm_seg =3D VCPU_SREG_DS; =20 if (ctxt->modrm_mod =3D=3D 3 || (ctxt->d & NoMod)) { - op->type =3D OP_REG; - op->bytes =3D (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; - op->addr.reg =3D decode_register(ctxt, ctxt->modrm_rm, - ctxt->d & ByteOp); - if (ctxt->d & Sse) { - op->type =3D OP_XMM; - op->bytes =3D 16; - op->addr.xmm =3D ctxt->modrm_rm; - kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val); - return rc; - } - if (ctxt->d & Mmx) { - op->type =3D OP_MM; - op->bytes =3D 8; - op->addr.mm =3D ctxt->modrm_rm & 7; - return rc; - } - fetch_register_operand(op); + __decode_register_operand(ctxt, op, ctxt->modrm_rm); return rc; } =20 @@ -4619,14 +4607,12 @@ static int decode_operand(struct x86_emulate_ctxt *= ctxt, struct operand *op, op->bytes =3D (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; op->addr.reg =3D reg_rmw(ctxt, VCPU_REGS_RAX); fetch_register_operand(op); - op->orig_val =3D op->val; break; case OpAccLo: op->type =3D OP_REG; op->bytes =3D (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; op->addr.reg =3D reg_rmw(ctxt, VCPU_REGS_RAX); fetch_register_operand(op); - op->orig_val =3D op->val; break; case OpAccHi: if (ctxt->d & ByteOp) { @@ -4637,7 +4623,6 @@ static int decode_operand(struct x86_emulate_ctxt *ct= xt, struct operand *op, op->bytes =3D ctxt->op_bytes; op->addr.reg =3D reg_rmw(ctxt, VCPU_REGS_RDX); fetch_register_operand(op); - op->orig_val =3D op->val; break; case OpDI: op->type =3D OP_MEM; --=20 2.43.5 From nobody Sun Feb 8 06:56:03 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C4FD258ECA for ; Fri, 14 Nov 2025 00:36:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763080606; cv=none; b=X/PNE43/npA9MdNiPdRn5V5COqa0VGv359m7akNgYAmWBFqAvwIr0AsVFmaBGjoE8fe8dUSFbc0lfqp/b+/+kmOnANWMEDb/591hXHoERCXwoMXrLswyJiwxLXsrDUBoaZFwdh8ghKngCKuV11bWMBiJXyblu1SsGxSG5T0o+cw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763080606; c=relaxed/simple; bh=o/pGAoGbIVp+fh4K/ZWEnQNrfi8awnyaiB1MiJypuD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TAi8FJjwvJuTuEzzz+0mC3+BwJQjIbkfkJIRzmF5XuW+4MdSzC95SjA+UEXMZ1b/G3sL9sIucEpfmGmi9jPkFYjxjg/xLiCzQg+kQJ1tnw9fPuYBe6pXLYcdvHwE9JCzgprqE55Vvh1qzxuUk8/zqWdW0SODNCPlVyq2QPtxLLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=WXB5F9+5; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="WXB5F9+5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763080603; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zm/zWVFRQtJEXVqjp0si12SzgJsoQe9GWB6V5sFDnSU=; b=WXB5F9+5KBAbV6kXHtt3nt0SvaRXiugo6nDCahfqCItdOsgqzRE02p/kYVzHmqDTFyMaKQ 2JlXvwzGWi4xCCSPbRaF78LUXaomUYZ1M9jFcUqsISUdBiAJkxuOMyOCite8TpyEP8WaXK yZ6NEfqsZQzpkUye2Fyit9XxewuYf/o= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-73-ETaiBloaPA6mz-JP1GSweA-1; Thu, 13 Nov 2025 19:36:40 -0500 X-MC-Unique: ETaiBloaPA6mz-JP1GSweA-1 X-Mimecast-MFC-AGG-ID: ETaiBloaPA6mz-JP1GSweA_1763080599 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 53EEC180045C; Fri, 14 Nov 2025 00:36:39 +0000 (UTC) Received: from virtlab1023.lab.eng.rdu2.redhat.com (virtlab1023.lab.eng.rdu2.redhat.com [10.8.1.187]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id AE65C19560B9; Fri, 14 Nov 2025 00:36:38 +0000 (UTC) From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: kbusch@kernel.org, chang.seok.bae@intel.com Subject: [PATCH 06/10] KVM: emulate: add get_xcr callback Date: Thu, 13 Nov 2025 19:36:29 -0500 Message-ID: <20251114003633.60689-7-pbonzini@redhat.com> In-Reply-To: <20251114003633.60689-1-pbonzini@redhat.com> References: <20251114003633.60689-1-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" This will be necessary in order to check whether AVX is enabled. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/kvm_emulate.h | 1 + arch/x86/kvm/x86.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 83af019620e3..5f9d69c64cd5 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -237,6 +237,7 @@ struct x86_emulate_ops { bool (*is_smm)(struct x86_emulate_ctxt *ctxt); int (*leave_smm)(struct x86_emulate_ctxt *ctxt); void (*triple_fault)(struct x86_emulate_ctxt *ctxt); + int (*get_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 *xcr); int (*set_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr); =20 gva_t (*get_untagged_addr)(struct x86_emulate_ctxt *ctxt, gva_t addr, diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c9c2aa6f4705..cfce7c120215 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -8842,6 +8842,14 @@ static void emulator_triple_fault(struct x86_emulate= _ctxt *ctxt) kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 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charset="utf-8" Prepare struct operand for hosting AVX registers. Remove the existing, incomplete code that placed the Avx flag in the operand alignment field, and repurpose the name for a separate bit that indicates: - after decode, whether an instruction supports the VEX prefix; - before writeback, that the instruction did have the VEX prefix and therefore 1) it can have op_bytes =3D=3D 32; 2) t should clear high bytes of XMM registers. Right now the bit will never be set and the patch has no intended functional change. However, this is actually more vexing than the decoder changes itself, and therefore worth separating. Co-developed-by: Keith Busch Signed-off-by: Keith Busch Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 58 ++++++++++++++++++++++++++--------- arch/x86/kvm/fpu.h | 62 ++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/kvm_emulate.h | 7 +++-- 3 files changed, 110 insertions(+), 17 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 6c8d3f786e74..94dc8a61965b 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -141,6 +141,7 @@ #define No64 (1<<28) /* Instruction generates #UD in 64-bit mod= e */ #define PageTable (1 << 29) /* instruction used to write page table */ #define NotImpl (1 << 30) /* instruction is not implemented */ +#define Avx ((u64)1 << 31) /* Instruction uses VEX prefix */ #define Src2Shift (32) /* Source 2 operand type at bits 32-36 */ #define Src2None (OpNone << Src2Shift) #define Src2Mem (OpMem << Src2Shift) @@ -157,12 +158,11 @@ #define Src2Mask (OpMask << Src2Shift) /* free: 37-39 */ #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ -#define AlignMask ((u64)7 << 41) /* Memory alignment requirement at bit= s 41-43 */ +#define AlignMask ((u64)3 << 41) /* Memory alignment requirement at bit= s 41-42 */ #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) = */ -#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ -#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. F= XSAVE) */ -/* free: 44 */ +#define Aligned16 ((u64)3 << 41) /* Aligned to 16 byte boundary (e.g. F= XSAVE) */ +/* free: 43-44 */ #define NoWrite ((u64)1 << 45) /* No writeback */ #define SrcWrite ((u64)1 << 46) /* Write back src operand */ #define NoMod ((u64)1 << 47) /* Mod field is ignored */ @@ -618,7 +618,6 @@ static unsigned insn_alignment(struct x86_emulate_ctxt = *ctxt, unsigned size) =20 switch (alignment) { case Unaligned: - case Avx: return 1; case Aligned16: return 16; @@ -1075,7 +1074,14 @@ static int em_fnstsw(struct x86_emulate_ctxt *ctxt) static void __decode_register_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, int reg) { - if (ctxt->d & Sse) { + if ((ctxt->d & Avx) && ctxt->op_bytes =3D=3D 32) { + op->type =3D OP_YMM; + op->bytes =3D 32; + op->addr.xmm =3D reg; + kvm_read_avx_reg(reg, &op->vec_val2); + return; + } + if (ctxt->d & (Avx|Sse)) { op->type =3D OP_XMM; op->bytes =3D 16; op->addr.xmm =3D reg; @@ -1767,7 +1773,15 @@ static int writeback(struct x86_emulate_ctxt *ctxt, = struct operand *op) op->data, op->bytes * op->count); case OP_XMM: - kvm_write_sse_reg(op->addr.xmm, &op->vec_val); + if (!(ctxt->d & Avx)) { + kvm_write_sse_reg(op->addr.xmm, &op->vec_val); + break; + } + /* full YMM write but with high bytes cleared */ + memset(op->valptr + 16, 0, 16); + fallthrough; + case OP_YMM: + kvm_write_avx_reg(op->addr.xmm, &op->vec_val2); break; case OP_MM: kvm_write_mmx_reg(op->addr.mm, &op->mm_val); @@ -4861,9 +4875,8 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int ctxt->op_bytes =3D 8; /* REX.W */ =20 /* Opcode byte(s). */ - opcode =3D opcode_table[ctxt->b]; - /* Two-byte opcode? */ if (ctxt->b =3D=3D 0x0f) { + /* Two- or three-byte opcode */ ctxt->opcode_len =3D 2; ctxt->b =3D insn_fetch(u8, ctxt); opcode =3D twobyte_table[ctxt->b]; @@ -4874,6 +4887,9 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int ctxt->b =3D insn_fetch(u8, ctxt); opcode =3D opcode_map_0f_38[ctxt->b]; } + } else { + /* Opcode byte(s). */ + opcode =3D opcode_table[ctxt->b]; } ctxt->d =3D opcode.flags; =20 @@ -5022,7 +5038,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int ctxt->op_bytes =3D 4; =20 if (ctxt->d & Sse) - ctxt->op_bytes =3D 16; + ctxt->op_bytes =3D 16, ctxt->d &=3D ~Avx; else if (ctxt->d & Mmx) ctxt->op_bytes =3D 8; } @@ -5154,20 +5170,34 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt,= bool check_intercepts) } =20 if (unlikely(ctxt->d & - (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { + (No64|Undefined|Avx|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String)))= { if ((ctxt->mode =3D=3D X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || (ctxt->d & Undefined)) { rc =3D emulate_ud(ctxt); goto done; } =20 - if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) - || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { + if ((ctxt->d & (Avx|Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) { rc =3D emulate_ud(ctxt); goto done; } =20 - if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { + if (ctxt->d & Avx) { + u64 xcr =3D 0; + if (!(ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE) + || ops->get_xcr(ctxt, 0, &xcr) + || !(xcr & XFEATURE_MASK_YMM)) { + rc =3D emulate_ud(ctxt); + goto done; + } + } else if (ctxt->d & Sse) { + if (!(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR)) { + rc =3D emulate_ud(ctxt); + goto done; + } + } + + if ((ctxt->d & (Avx|Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { rc =3D emulate_nm(ctxt); goto done; } diff --git a/arch/x86/kvm/fpu.h b/arch/x86/kvm/fpu.h index 3ba12888bf66..9bc08c3c53f5 100644 --- a/arch/x86/kvm/fpu.h +++ b/arch/x86/kvm/fpu.h @@ -15,6 +15,54 @@ typedef u32 __attribute__((vector_size(16))) sse128_t; #define sse128_l3(x) ({ __sse128_u t; t.vec =3D x; t.as_u32[3]; }) #define sse128(lo, hi) ({ __sse128_u t; t.as_u64[0] =3D lo; t.as_u64[1] = =3D hi; t.vec; }) =20 +typedef u32 __attribute__((vector_size(32))) avx256_t; + +static inline void _kvm_read_avx_reg(int reg, avx256_t *data) +{ + switch (reg) { + case 0: asm("vmovdqa %%ymm0, %0" : "=3Dm"(*data)); break; + case 1: asm("vmovdqa %%ymm1, %0" : "=3Dm"(*data)); break; + case 2: asm("vmovdqa %%ymm2, %0" : "=3Dm"(*data)); break; + case 3: asm("vmovdqa %%ymm3, %0" : "=3Dm"(*data)); break; + case 4: asm("vmovdqa %%ymm4, %0" : "=3Dm"(*data)); break; + case 5: asm("vmovdqa %%ymm5, %0" : "=3Dm"(*data)); break; + case 6: asm("vmovdqa %%ymm6, %0" : "=3Dm"(*data)); break; + case 7: asm("vmovdqa %%ymm7, %0" : "=3Dm"(*data)); break; + case 8: asm("vmovdqa %%ymm8, %0" : "=3Dm"(*data)); break; + case 9: asm("vmovdqa %%ymm9, %0" : "=3Dm"(*data)); break; + case 10: asm("vmovdqa %%ymm10, %0" : "=3Dm"(*data)); break; + case 11: asm("vmovdqa %%ymm11, %0" : "=3Dm"(*data)); break; + case 12: asm("vmovdqa %%ymm12, %0" : "=3Dm"(*data)); break; + case 13: asm("vmovdqa %%ymm13, %0" : "=3Dm"(*data)); break; + case 14: asm("vmovdqa %%ymm14, %0" : "=3Dm"(*data)); break; + case 15: asm("vmovdqa %%ymm15, %0" : "=3Dm"(*data)); break; + default: BUG(); + } +} + +static inline void _kvm_write_avx_reg(int reg, const avx256_t *data) +{ + switch (reg) { + case 0: asm("vmovdqa %0, %%ymm0" : : "m"(*data)); break; + case 1: asm("vmovdqa %0, %%ymm1" : : "m"(*data)); break; + case 2: asm("vmovdqa %0, %%ymm2" : : "m"(*data)); break; + case 3: asm("vmovdqa %0, %%ymm3" : : "m"(*data)); break; + case 4: asm("vmovdqa %0, %%ymm4" : : "m"(*data)); break; + case 5: asm("vmovdqa %0, %%ymm5" : : "m"(*data)); break; + case 6: asm("vmovdqa %0, %%ymm6" : : "m"(*data)); break; + case 7: asm("vmovdqa %0, %%ymm7" : : "m"(*data)); break; + case 8: asm("vmovdqa %0, %%ymm8" : : "m"(*data)); break; + case 9: asm("vmovdqa %0, %%ymm9" : : "m"(*data)); break; + case 10: asm("vmovdqa %0, %%ymm10" : : "m"(*data)); break; + case 11: asm("vmovdqa %0, %%ymm11" : : "m"(*data)); break; + case 12: asm("vmovdqa %0, %%ymm12" : : "m"(*data)); break; + case 13: asm("vmovdqa %0, %%ymm13" : : "m"(*data)); break; + case 14: asm("vmovdqa %0, %%ymm14" : : "m"(*data)); break; + case 15: asm("vmovdqa %0, %%ymm15" : : "m"(*data)); break; + default: BUG(); + } +} + static inline void _kvm_read_sse_reg(int reg, sse128_t *data) { switch (reg) { @@ -109,6 +157,20 @@ static inline void kvm_fpu_put(void) fpregs_unlock(); } =20 +static inline void kvm_read_avx_reg(int reg, avx256_t *data) +{ + kvm_fpu_get(); + _kvm_read_avx_reg(reg, data); + kvm_fpu_put(); +} + +static inline void kvm_write_avx_reg(int reg, const avx256_t *data) +{ + kvm_fpu_get(); + _kvm_write_avx_reg(reg, data); + kvm_fpu_put(); +} + static inline void kvm_read_sse_reg(int reg, sse128_t *data) { kvm_fpu_get(); diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 5f9d69c64cd5..c526f46f5595 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -249,7 +249,7 @@ struct x86_emulate_ops { =20 /* Type, address-of, and value of an instruction's operand. */ struct operand { - enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_MM, OP_NONE } type; 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Fri, 14 Nov 2025 00:36:40 +0000 (UTC) Received: from virtlab1023.lab.eng.rdu2.redhat.com (virtlab1023.lab.eng.rdu2.redhat.com [10.8.1.187]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 2602419560B9; Fri, 14 Nov 2025 00:36:40 +0000 (UTC) From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: kbusch@kernel.org, chang.seok.bae@intel.com Subject: [PATCH 08/10] KVM: x86: Refactor REX prefix handling in instruction emulation Date: Thu, 13 Nov 2025 19:36:31 -0500 Message-ID: <20251114003633.60689-9-pbonzini@redhat.com> In-Reply-To: <20251114003633.60689-1-pbonzini@redhat.com> References: <20251114003633.60689-1-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" From: "Chang S. Bae" Restructure how to represent and interpret REX fields, preparing for handling of both REX2 and VEX. REX uses the upper four bits of a single byte as a fixed identifier, and the lower four bits containing the data. VEX and REX2 extends this so that the first byte identifies the prefix and the rest encode additional bits; and while VEX only has the same four data bits as REX, eight zero bits are a valid value for the data bits of REX2. So, stop storing the REX byte as-is. Instead, store only the low bits of the REX prefix and track separately whether a REX-like prefix was used. No functional changes intended. Signed-off-by: Chang S. Bae Message-ID: <20251110180131.28264-11-chang.seok.bae@intel.com> [Extracted from APX series; removed bitfields and REX2-specific default. - = Paolo] Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 33 +++++++++++++++++++++------------ arch/x86/kvm/kvm_emulate.h | 11 ++++++++++- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 94dc8a61965b..643f0ebadf9c 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -239,6 +239,13 @@ enum x86_transfer_type { X86_TRANSFER_TASK_SWITCH, }; =20 +enum { + REX_B =3D 1, + REX_X =3D 2, + REX_R =3D 4, + REX_W =3D 8, +}; + static void writeback_registers(struct x86_emulate_ctxt *ctxt) { unsigned long dirty =3D ctxt->regs_dirty; @@ -919,7 +926,7 @@ static void *decode_register(struct x86_emulate_ctxt *c= txt, u8 modrm_reg, int byteop) { void *p; - int highbyte_regs =3D (ctxt->rex_prefix =3D=3D 0) && byteop; + int highbyte_regs =3D (ctxt->rex_prefix =3D=3D REX_NONE) && byteop; =20 if (highbyte_regs && modrm_reg >=3D 4 && modrm_reg < 8) p =3D (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; @@ -1110,7 +1117,7 @@ static void decode_register_operand(struct x86_emulat= e_ctxt *ctxt, if (ctxt->d & ModRM) reg =3D ctxt->modrm_reg; else - reg =3D (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); + reg =3D (ctxt->b & 7) | (ctxt->rex_bits & REX_B ? 8 : 0); =20 __decode_register_operand(ctxt, op, reg); } @@ -1129,9 +1136,9 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt, int rc =3D X86EMUL_CONTINUE; ulong modrm_ea =3D 0; =20 - ctxt->modrm_reg =3D ((ctxt->rex_prefix << 1) & 8); /* REX.R */ - index_reg =3D (ctxt->rex_prefix << 2) & 8; /* REX.X */ - base_reg =3D (ctxt->rex_prefix << 3) & 8; /* REX.B */ + ctxt->modrm_reg =3D (ctxt->rex_bits & REX_R ? 8 : 0); + index_reg =3D (ctxt->rex_bits & REX_X ? 8 : 0); + base_reg =3D (ctxt->rex_bits & REX_B ? 8 : 0); =20 ctxt->modrm_mod =3D (ctxt->modrm & 0xc0) >> 6; ctxt->modrm_reg |=3D (ctxt->modrm & 0x38) >> 3; @@ -2464,7 +2471,7 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt) =20 setup_syscalls_segments(&cs, &ss); =20 - if ((ctxt->rex_prefix & 0x8) !=3D 0x0) + if (ctxt->rex_bits & REX_W) usermode =3D X86EMUL_MODE_PROT64; else usermode =3D X86EMUL_MODE_PROT32; @@ -4850,7 +4857,8 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int case 0x40 ... 0x4f: /* REX */ if (mode !=3D X86EMUL_MODE_PROT64) goto done_prefixes; - ctxt->rex_prefix =3D ctxt->b; + ctxt->rex_prefix =3D REX_PREFIX; + ctxt->rex_bits =3D ctxt->b & 0xf; continue; case 0xf0: /* LOCK */ ctxt->lock_prefix =3D 1; @@ -4864,15 +4872,15 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, = void *insn, int insn_len, int } =20 /* Any legacy prefix after a REX prefix nullifies its effect. */ - - ctxt->rex_prefix =3D 0; + ctxt->rex_prefix =3D REX_NONE; + ctxt->rex_bits =3D 0; } =20 done_prefixes: =20 /* REX prefix. */ - if (ctxt->rex_prefix & 8) - ctxt->op_bytes =3D 8; /* REX.W */ + if (ctxt->rex_bits & REX_W) + ctxt->op_bytes =3D 8; =20 /* Opcode byte(s). */ if (ctxt->b =3D=3D 0x0f) { @@ -5138,7 +5146,8 @@ void init_decode_cache(struct x86_emulate_ctxt *ctxt) { /* Clear fields that are set conditionally but read without a guard. */ ctxt->rip_relative =3D false; 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charset="utf-8" After all the changes done in the previous patches, the only thing left to support AVX moves is to expand the VEX prefix into the appropriate REX, 66/F3/F2 and map prefixes. Three-operand instructions are not supported. The Avx bit in this case is not cleared, in fact it is used as the sign that the instruction does support VEX encoding. Until it is added to any instruction, however, the only functional change is to change some not-implemented instructions to #UD if they correspond to a VEX prefix with an invalid map. Co-developed-by: Keith Busch Signed-off-by: Keith Busch Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 123 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 113 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 643f0ebadf9c..1e17043a6304 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -3963,6 +3963,8 @@ static int check_perm_out(struct x86_emulate_ctxt *ct= xt) I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) =20 +static const struct opcode ud =3D I(SrcNone, emulate_ud); + static const struct opcode group7_rm0[] =3D { N, I(SrcNone | Priv | EmulateOnUD, em_hypercall), @@ -4762,11 +4765,87 @@ static int decode_operand(struct x86_emulate_ctxt *= ctxt, struct operand *op, return rc; } =20 +static int x86_decode_avx(struct x86_emulate_ctxt *ctxt, + u8 vex_1st, u8 vex_2nd, struct opcode *opcode) +{ + u8 vex_3rd, map, pp, l, v; + int rc =3D X86EMUL_CONTINUE; + + if (ctxt->rep_prefix || ctxt->op_prefix || ctxt->rex_prefix) + goto ud; + + if (vex_1st =3D=3D 0xc5) { + /* Expand RVVVVlpp to VEX3 format */ + vex_3rd =3D vex_2nd & ~0x80; /* VVVVlpp from VEX2, w=3D0 */ + vex_2nd =3D (vex_2nd & 0x80) | 0x61; /* R from VEX2, X=3D1 B=3D1 mmmmm= =3D00001 */ + } else { + vex_3rd =3D insn_fetch(u8, ctxt); + } + + /* vex_2nd =3D RXBmmmmm, vex_3rd =3D wVVVVlpp. Fix polarity */ + vex_2nd ^=3D 0xE0; /* binary 11100000 */ + vex_3rd ^=3D 0x78; /* binary 01111000 */ + + ctxt->rex_prefix =3D REX_PREFIX; + ctxt->rex_bits =3D (vex_2nd & 0xE0) >> 5; /* RXB */ + ctxt->rex_bits |=3D (vex_3rd & 0x80) >> 4; /* w */ + if (ctxt->rex_bits && ctxt->mode !=3D X86EMUL_MODE_PROT64) + goto ud; + + map =3D vex_2nd & 0x1f; + v =3D (vex_3rd >> 3) & 0xf; + l =3D vex_3rd & 0x4; + pp =3D vex_3rd & 0x3; + + ctxt->b =3D insn_fetch(u8, ctxt); + switch (map) { + case 1: + ctxt->opcode_len =3D 2; + *opcode =3D twobyte_table[ctxt->b]; + break; + case 2: + ctxt->opcode_len =3D 3; + *opcode =3D opcode_map_0f_38[ctxt->b]; + break; + case 3: + /* no 0f 3a instructions are supported yet */ + return X86EMUL_UNHANDLEABLE; + default: + goto ud; + } + + /* + * No three operand instructions are supported yet; those that + * *are* marked with the Avx flag reserve the VVVV flag. + */ + if (v) + goto ud; + + if (l) + ctxt->op_bytes =3D 32; + else + ctxt->op_bytes =3D 16; + + switch (pp) { + case 0: break; + case 1: ctxt->op_prefix =3D true; break; + case 2: ctxt->rep_prefix =3D 0xf3; break; + case 3: ctxt->rep_prefix =3D 0xf2; break; + } + +done: + return rc; +ud: + *opcode =3D ud; + return rc; +} + int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_le= n, int emulation_type) { int rc =3D X86EMUL_CONTINUE; int mode =3D ctxt->mode; int def_op_bytes, def_ad_bytes, goffset, simd_prefix; + bool vex_prefix =3D false; bool has_seg_override =3D false; struct opcode opcode; u16 dummy; @@ -4883,7 +4962,21 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, v= oid *insn, int insn_len, int ctxt->op_bytes =3D 8; =20 /* Opcode byte(s). */ - if (ctxt->b =3D=3D 0x0f) { + if (ctxt->b =3D=3D 0xc4 || ctxt->b =3D=3D 0xc5) { + /* VEX or LDS/LES */ + u8 vex_2nd =3D insn_fetch(u8, ctxt); + if (mode !=3D X86EMUL_MODE_PROT64 && (vex_2nd & 0xc0) !=3D 0xc0) { + opcode =3D opcode_table[ctxt->b]; + ctxt->modrm =3D vex_2nd; + /* the Mod/RM byte has been fetched already! */ + goto done_modrm; + } + + vex_prefix =3D true; + rc =3D x86_decode_avx(ctxt, ctxt->b, vex_2nd, &opcode); + if (rc !=3D X86EMUL_CONTINUE) + goto done; + } else if (ctxt->b =3D=3D 0x0f) { /* Two- or three-byte opcode */ ctxt->opcode_len =3D 2; ctxt->b =3D insn_fetch(u8, ctxt); @@ -4899,17 +4992,12 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, = void *insn, int insn_len, int /* Opcode byte(s). */ opcode =3D opcode_table[ctxt->b]; } - ctxt->d =3D opcode.flags; =20 - if (ctxt->d & ModRM) + if (opcode.flags & ModRM) ctxt->modrm =3D insn_fetch(u8, ctxt); =20 - /* vex-prefix instructions are not implemented */ - if (ctxt->opcode_len =3D=3D 1 && (ctxt->b =3D=3D 0xc5 || ctxt->b =3D=3D 0= xc4) && - (mode =3D=3D X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) =3D=3D 0xc0)= ) { - ctxt->d =3D NotImpl; - } - +done_modrm: + ctxt->d =3D opcode.flags; while (ctxt->d & GroupMask) { switch (ctxt->d & GroupMask) { case Group: @@ -4975,6 +5063,19 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, v= oid *insn, int insn_len, int if (ctxt->d =3D=3D 0) return EMULATION_FAILED; =20 + if (unlikely(vex_prefix)) { + /* + * Only specifically marked instructions support VEX. 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Whenever the guest OS tries to do that, an illegal instruction exception or emulation failure is triggered. Add the Avx flag to move instructions: - (66) 0f 10 - MOVUPS/MOVUPD from memory - (66) 0f 11 - MOVUPS/MOVUPD to memory - 66 0f 6f - MOVDQA from memory - 66 0f 7f - MOVDQA to memory - f3 0f 6f - MOVDQU from memory - f3 0f 7f - MOVDQU to memory - (66) 0f 28 - MOVAPS/MOVAPD from memory - (66) 0f 29 - MOVAPS/MOVAPD to memory - (66) 0f 2b - MOVNTPS/MOVNTPD to memory - 66 0f e7 - MOVNTDQ to memory - 66 0f 38 2a - MOVNTDQA to memory Co-developed-by: Keith Busch Signed-off-by: Keith Busch Link: https://lore.kernel.org/kvm/BD108C42-0382-4B17-B601-434A4BD038E7@fb.c= om/T/ Signed-off-by: Paolo Bonzini --- arch/x86/kvm/emulate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 1e17043a6304..75619bdc600f 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -4122,7 +4122,7 @@ static const struct group_dual group15 =3D { { } }; =20 static const struct gprefix pfx_0f_6f_0f_7f =3D { - I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), + I(Mmx, em_mov), I(Sse | Avx | Aligned, em_mov), N, I(Sse | Avx | Unaligne= d, em_mov), }; =20 static const struct instr_dual instr_dual_0f_2b =3D { @@ -4142,7 +4142,7 @@ static const struct gprefix pfx_0f_28_0f_29 =3D { }; =20 static const struct gprefix pfx_0f_e7_0f_38_2a =3D { - N, I(Sse, em_mov), N, N, + N, I(Sse | Avx, em_mov), N, N, }; =20 static const struct escape escape_d9 =3D { { @@ -4355,8 +4355,8 @@ static const struct opcode twobyte_table[256] =3D { DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, /* 0x10 - 0x1F */ - GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), - GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), + GP(ModRM | DstReg | SrcMem | Mov | Sse | Avx, &pfx_0f_10_0f_11), + GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_10_0f_11), N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserve= d NOP */ D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, @@ -4372,9 +4372,9 @@ static const struct opcode twobyte_table[256] =3D { IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, check_dr_write), N, N, N, N, - GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), - GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), - N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), + GP(ModRM | DstReg | SrcMem | Mov | Sse | Avx, &pfx_0f_28_0f_29), + GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_28_0f_29), + N, GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_2b), N, N, N, N, /* 0x30 - 0x3F */ II(ImplicitOps | Priv, em_wrmsr, wrmsr), --=20 2.43.5