From nobody Tue Feb 10 19:53:14 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BFCD2C21F5; Fri, 14 Nov 2025 17:53:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763142820; cv=none; b=eVCJVVIjdL1Kks5oioFXkvz41pOLCaLV0hXhU1iNN/Q0nyFEq2QesdhFqzNfHHT7lsJmKxYoKsPRzlSAoKSm/ONe2Vf2x5bbyg6rExg5KHrynTPxjyg0A3/ENq0GUKzv0eLa+BzAvCHgGv/68wfOuBdG+6olNxLoiDFTwKUSDLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763142820; c=relaxed/simple; bh=Rps2rVf1iBkCo+7yL4ZRaaLTkd/NueQxdvnXQ0JtEww=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MYD7opDNrB/mIXT8zdvIAdZDWEzQrz4QXlFa0CM3JoqGVbYAClQCchFJU0gwtO9TP0b5EGyFRr6SADxOhtY/pYBDGm25znhnI5n9ifBbyFcm0v83ezxBfsvRcJsVnxeXnPV+xOLikEfS5VFSmYRNERo6YxZvzOEY+6BGaMcyjJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=P34ptUBH; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="P34ptUBH" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 9C5004E416B8; Fri, 14 Nov 2025 17:53:35 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6DC726060E; Fri, 14 Nov 2025 17:53:35 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id AECFD103719A5; Fri, 14 Nov 2025 18:53:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1763142814; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=y/WeeXtRbXR7iq7YMUsDfUK2bl94kyFbQtNORKsntUA=; b=P34ptUBHyEzPqiVlqXNQY1uDiSCnHX+Ve20zAwtwsVx1ksZrzkBjxNY26CaKjDYO9DAFD9 LhvgKl5s+hMH874t2S5ZF+m13apiAwd0zxtwsS/NTFG1uJ7HtPJYd/MIMJuzwlbKg/etWi kQwVprg9+3JL6slT0PRqaVxH28/RXQIHQg9yon3vNMaiEDHsqsvFstFHBwhipCPa6rNk8u IKxhukFaFbR+a0T105TU/IgB+v4l2sFmen4+egzpab9qCVl60Eumo1cDQCZ6n/+2yLYfyD PE3KyilnkWmJzzP5fZ79ui3DYrFFZ7tRiCbqnSvYQEqX6i/oF7sGU+LQpEZQog== From: Miquel Raynal Date: Fri, 14 Nov 2025 18:53:09 +0100 Subject: [PATCH 08/19] mtd: spi-nor: swp: Use a pointer for SR instead of a single byte Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-winbond-v6-18-rc1-spi-nor-swp-v1-8-487bc7129931@bootlin.com> References: <20251114-winbond-v6-18-rc1-spi-nor-swp-v1-0-487bc7129931@bootlin.com> In-Reply-To: <20251114-winbond-v6-18-rc1-spi-nor-swp-v1-0-487bc7129931@bootlin.com> To: Tudor Ambarus , Pratyush Yadav , Michael Walle , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 At this stage, the Status Register is most often seen as a single byte. This is subject to change when we will need to read the CMP bit which is located in the Control Register (kind of secondary status register). Both will need to be carried. Change a few prototypes to carry a u8 pointer. This way it also makes it very clear where we access the first register, and where we will access the second. There is no functional change. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 48 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 350fb8cd67dbafa3c62201c8c06bff7131143c04..bac07287ada036f49c25237549e= 4900f76a0247d 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -53,13 +53,13 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_no= r *nor) return sector_size; } =20 -static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t= *ofs, +static void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr,= loff_t *ofs, u64 *len) { u64 min_prot_len; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr & mask; + u8 bp, val =3D sr[0] & mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -79,7 +79,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, u8 sr, loff_t *ofs, if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) + if (nor->flags & SNOR_F_HAS_SR_TB && sr[0] & tb_mask) *ofs =3D 0; else *ofs =3D nor->params->size - *len; @@ -90,7 +90,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, u8 sr, loff_t *ofs, * (if @locked is false); false otherwise. */ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, - u64 len, u8 sr, bool locked) + u64 len, const u8 *sr, bool locked) { loff_t lock_offs, lock_offs_max, offs_max; u64 lock_len; @@ -111,13 +111,13 @@ static bool spi_nor_check_lock_status_sr(struct spi_n= or *nor, loff_t ofs, return (ofs >=3D lock_offs_max) || (offs_max <=3D lock_offs); } =20 -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= u8 sr) +static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= const u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } =20 static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 le= n, - u8 sr) + const u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } @@ -158,7 +158,8 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor,= loff_t ofs, u64 len, static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len; - int ret, status_old, status_new; + int ret; + u8 status_old[1] =3D {}, status_new[1] =3D {}; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; @@ -170,7 +171,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) if (ret) return ret; =20 - status_old =3D nor->bouncebuf[0]; + status_old[0] =3D nor->bouncebuf[0]; =20 /* If nothing in our range is unlocked, we don't need to do anything */ if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) @@ -215,7 +216,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return -EINVAL; } =20 - status_new =3D (status_old & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -223,20 +224,20 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) * WP# pin hard strapped to GND can be a valid use case. */ if (!(nor->flags & SNOR_F_NO_WP)) - status_new |=3D SR_SRWD; + status_new[0] |=3D SR_SRWD; =20 if (!use_top) - status_new |=3D tb_mask; + status_new[0] |=3D tb_mask; =20 /* Don't bother if they're the same */ - if (status_new =3D=3D status_old) + if (status_new[0] =3D=3D status_old[0]) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new & mask) < (status_old & mask)) + if ((status_new[0] & mask) < (status_old[0] & mask)) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new); + return spi_nor_write_sr_and_check(nor, status_new[0]); } =20 /* @@ -247,7 +248,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len; - int ret, status_old, status_new; + int ret; + u8 status_old[1], status_new[1]; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; @@ -259,7 +261,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) if (ret) return ret; =20 - status_old =3D nor->bouncebuf[0]; + status_old[0] =3D nor->bouncebuf[0]; =20 /* If nothing in our range is locked, we don't need to do anything */ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) @@ -303,24 +305,24 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) return -EINVAL; } =20 - status_new =3D (status_old & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) - status_new &=3D ~SR_SRWD; + status_new[0] &=3D ~SR_SRWD; =20 if (!use_top) - status_new |=3D tb_mask; + status_new[0] |=3D tb_mask; =20 /* Don't bother if they're the same */ - if (status_new =3D=3D status_old) + if (status_new[0] =3D=3D status_old[0]) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new & mask) > (status_old & mask)) + if ((status_new[0] & mask) > (status_old[0] & mask)) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new); + return spi_nor_write_sr_and_check(nor, status_new[0]); } =20 /* @@ -338,7 +340,7 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, lo= ff_t ofs, u64 len) if (ret) return ret; =20 - return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); + return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf); } =20 /* --=20 2.51.0