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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 08:43:19.7611 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a4143c5-b7ea-45a9-fed2-08de2359dce5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4063 The capabilities of getting and setting VRAM carveout size are exposed in the ATCS mask. Parse and store these capabilities for future use. Co-developed-by: Mario Limonciello (AMD) Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher Signed-off-by: Yo-Jung Leo Lin (AMD) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 ++++ drivers/gpu/drm/amd/include/amd_acpi.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_acpi.c index 6c62e27b9800..0743fd8620e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -116,7 +116,9 @@ struct amdgpu_atcs_functions { bool pcie_perf_req; bool pcie_dev_rdy; bool pcie_bus_width; + bool get_uma_size; bool power_shift_control; + bool set_uma_allocation_size; }; =20 struct amdgpu_atcs { @@ -588,7 +590,9 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_a= tcs_functions *f, u32 mas f->pcie_perf_req =3D mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED; f->pcie_dev_rdy =3D mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED; f->pcie_bus_width =3D mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED; + f->get_uma_size =3D mask & ACPI_ATCS_GET_UMA_SIZE_SUPPORTED; f->power_shift_control =3D mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED; + f->set_uma_allocation_size =3D mask & ACPI_ATCS_SET_UMA_ALLOCATION_SIZE_S= UPPORTED; } =20 /** diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/i= nclude/amd_acpi.h index 06badbf0c5b9..e582339e8e8e 100644 --- a/drivers/gpu/drm/amd/include/amd_acpi.h +++ b/drivers/gpu/drm/amd/include/amd_acpi.h @@ -427,7 +427,9 @@ struct atcs_pwr_shift_input { # define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1) # define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2) # define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3) -# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7) +# define ACPI_ATCS_GET_UMA_SIZE_SUPPORTED (1 << 5) +# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7) +# define ACPI_ATCS_SET_UMA_ALLOCATION_SIZE_SUPPORTED (1 << 9) #define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1 /* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE * ARG1: none --=20 2.43.0 From nobody Mon Feb 9 07:44:15 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010066.outbound.protection.outlook.com [52.101.85.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D6EA3002A9; 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Fri, 14 Nov 2025 00:43:19 -0800 From: "Yo-Jung Leo Lin (AMD)" Date: Fri, 14 Nov 2025 16:42:22 +0800 Subject: [PATCH v2 2/5] drm/amdgpu: add helper to read UMA carveout info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251114-vram-carveout-tuning-for-upstream-v2-2-4f6bdd48030d@amd.com> References: <20251114-vram-carveout-tuning-for-upstream-v2-0-4f6bdd48030d@amd.com> In-Reply-To: <20251114-vram-carveout-tuning-for-upstream-v2-0-4f6bdd48030d@amd.com> To: Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet CC: , , , , "Tsao, Anson" , "Mario Limonciello (AMD) (kernel.org)" , "Yo-Jung Leo Lin (AMD)" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6135; i=Leo.Lin@amd.com; h=from:subject:message-id; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 08:43:23.0968 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05e43b5b-0d6d-460d-6034-08de2359dee2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4067 Currently, the available UMA allocation configs in the integrated system information table have not been parsed. Add a helper function to retrieve and store these configs. Co-developed-by: Mario Limonciello (AMD) Signed-off-by: Mario Limonciello (AMD) Signed-off-by: Yo-Jung Leo Lin (AMD) Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 32 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 73 ++++++++++++++++++++= ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 + 4 files changed, 109 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index a5574e84694b..2c1123291577 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1675,6 +1675,38 @@ struct amdgpu_numa_info { int nid; }; =20 +#define MAX_UMA_OPTION_NAME 28 +#define MAX_UMA_OPTION_ENTRIES 19 + +#define AMDGPU_UMA_FLAG_AUTO BIT(1) +#define AMDGPU_UMA_FLAG_CUSTOM BIT(0) + +/** + * struct amdgpu_uma_carveut_option - single UMA carveout option + * @name: Name of the carveout option + * @memory_carved: Amount of memory carved + * @flags: ATCS flags supported by this option + */ +struct amdgpu_uma_carveout_option { + char name[MAX_UMA_OPTION_NAME]; + uint8_t memory_carved; + uint8_t flags; +}; + +/** + * struct amdgpu_uma_carveut_info - table of available UMA carveout options + * @num_entries: Number of available options + * @uma_option_index: The index of the option currently applied + * @update_lock: Lock to serialize changes to the option + * @entries: The array of carveout options + */ +struct amdgpu_uma_carveout_info { + uint8_t num_entries; + uint8_t uma_option_index; + struct mutex update_lock; + struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; +}; + /* ATCS Device/Driver State */ #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_acpi.c index 0743fd8620e4..d442dc442d34 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -38,6 +38,7 @@ #include "amdgpu_display.h" #include "amd_acpi.h" #include "atom.h" +#include "amdgpu_atomfirmware.h" =20 /* Declare GUID for AMD _DSM method for XCCs */ static const guid_t amd_xcc_dsm_guid =3D GUID_INIT(0x8267f5d5, 0xa556, 0x4= 4f2, @@ -125,6 +126,7 @@ struct amdgpu_atcs { acpi_handle handle; =20 struct amdgpu_atcs_functions functions; + struct amdgpu_uma_carveout_info uma_info; }; =20 static struct amdgpu_acpi_priv { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu= /drm/amd/amdgpu/amdgpu_atomfirmware.c index 636385c80f64..b1463bb594aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -296,6 +296,79 @@ static int convert_atom_mem_type_to_vram_type(struct a= mdgpu_device *adev, return vram_type; } =20 +static int amdgpu_atomfirmware_get_uma_carveout_info_v2_3(struct amdgpu_de= vice *adev, + union igp_info *igp_info, + struct amdgpu_uma_carveout_info *uma_info) +{ + struct uma_carveout_option *opts; + uint8_t nr_uma_options; + int i; + + nr_uma_options =3D igp_info->v23.UMACarveoutIndexMax; + + if (!nr_uma_options) + return -ENODEV; + + if (nr_uma_options > MAX_UMA_OPTION_ENTRIES) { + drm_dbg(adev_to_drm(adev), + "Number of UMA options exceeds max table size. Options will not be pars= ed"); + return -EINVAL; + } + + uma_info->num_entries =3D nr_uma_options; + uma_info->uma_option_index =3D igp_info->v23.UMACarveoutIndex; + + opts =3D igp_info->v23.UMASizeControlOption; + + for (i =3D 0; i < nr_uma_options; i++) { + uma_info->entries[i].memory_carved =3D opts[i].memoryCarvedGb; + uma_info->entries[i].flags =3D opts[i].uma_carveout_option_flags.all8; + strscpy(uma_info->entries[i].name, opts[i].optionName, MAX_UMA_OPTION_NA= ME); + } + + return 0; +} + +int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, + struct amdgpu_uma_carveout_info *uma_info) +{ + struct amdgpu_mode_info *mode_info =3D &adev->mode_info; + union igp_info *igp_info; + u16 data_offset, size; + u8 frev, crev; + int index; + + if (!(adev->flags & AMD_IS_APU)) + return -ENODEV; + + index =3D get_index_into_master_table(atom_master_list_of_data_tables_v2_= 1, + integratedsysteminfo); + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, + index, &size, + &frev, &crev, &data_offset)) { + return -EINVAL; + } + + igp_info =3D (union igp_info *) + (mode_info->atom_context->bios + data_offset); + + switch (frev) { + case 2: + switch (crev) { + case 3: + return amdgpu_atomfirmware_get_uma_carveout_info_v2_3(adev, igp_info, u= ma_info); + break; + default: + break; + } + break; + default: + break; + } + return -ENODEV; +} + int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu= /drm/amd/amdgpu/amdgpu_atomfirmware.h index 649b5530d8ae..67c8d105729b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h @@ -32,6 +32,8 @@ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_= device *adev); int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev); int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor); +int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, + struct amdgpu_uma_carveout_info *uma_info); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 08:43:26.6277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d2bacb5-7bdf-4725-3b04-08de2359e0fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPFE5ACC0FD2 On some platforms, UMA allocation size can be set using the ATCS methods. Add helper functions to interact with this functionality. Co-developed-by: Mario Limonciello (AMD) Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher Signed-off-by: Yo-Jung Leo Lin (AMD) --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 43 ++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/amd/include/amd_acpi.h | 30 ++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index 2c1123291577..ac5e4fb17ff5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1718,12 +1718,14 @@ int amdgpu_acpi_init(struct amdgpu_device *adev); void amdgpu_acpi_fini(struct amdgpu_device *adev); bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_devic= e *adev); bool amdgpu_acpi_is_power_shift_control_supported(void); +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, u8 perf_req, bool advertise); int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state); int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, enum amdgpu_ss ss_state); +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 ind= ex, u8 type); int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, u64 *tmr_size); @@ -1752,6 +1754,7 @@ static inline bool amdgpu_acpi_should_gpu_reset(struc= t amdgpu_device *adev) { re static inline void amdgpu_acpi_detect(void) { } static inline void amdgpu_acpi_release(void) { } static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { re= turn false; } +static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) = { return false; } static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *ad= ev, u8 dev_state, bool drv_state) { return 0; } static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *ade= v, @@ -1759,6 +1762,10 @@ static inline int amdgpu_acpi_smart_shift_update(str= uct amdgpu_device *adev, { return 0; } +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 ind= ex, u8 type) +{ + return -EINVAL; +} static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlig= ht_caps *caps) { } #endif =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_acpi.c index d442dc442d34..444ab4102168 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -671,6 +671,11 @@ bool amdgpu_acpi_is_power_shift_control_supported(void) return amdgpu_acpi_priv.atcs.functions.power_shift_control; } =20 +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) +{ + return amdgpu_acpi_priv.atcs.functions.set_uma_allocation_size; +} + /** * amdgpu_acpi_pcie_notify_device_ready * @@ -911,6 +916,44 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_i= nfo(uint32_t pxm) } #endif =20 +/** + * amdgpu_acpi_set_uma_allocation_size - Set Unified Memory Architecture a= llocation size via ACPI + * @adev: Pointer to the amdgpu_device structure + * @index: Index specifying the UMA allocation + * @type: Type of UMA allocation + * + * This function configures the UMA allocation size for the specified devi= ce + * using ACPI methods. The allocation is determined by the provided index = and type. + * Returns 0 on success or a negative error code on failure. + */ +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 ind= ex, u8 type) +{ + struct atcs_set_uma_allocation_size_input atcs_input; + struct amdgpu_atcs *atcs =3D &amdgpu_acpi_priv.atcs; + struct acpi_buffer params; + union acpi_object *info; + + if (!amdgpu_acpi_is_set_uma_allocation_size_supported()) + return -EINVAL; + + atcs_input.size =3D sizeof(struct atcs_set_uma_allocation_size_input); + atcs_input.uma_size_index =3D index; + atcs_input.uma_size_type =3D type; + + params.length =3D sizeof(struct atcs_set_uma_allocation_size_input); + params.pointer =3D &atcs_input; + + info =3D amdgpu_atcs_call(atcs, ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE, &p= arams); + if (!info) { + drm_err(adev_to_drm(adev), "ATCS UMA allocation size update failed\n"); + return -EIO; + } + + kfree(info); + + return 0; +} + /** * amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amd= gpu * acpi device handle diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/i= nclude/amd_acpi.h index e582339e8e8e..84933c07f720 100644 --- a/drivers/gpu/drm/amd/include/amd_acpi.h +++ b/drivers/gpu/drm/amd/include/amd_acpi.h @@ -24,6 +24,8 @@ #ifndef AMD_ACPI_H #define AMD_ACPI_H =20 +#include + #define ACPI_AC_CLASS "ac_adapter" =20 struct atif_verify_interface { @@ -112,6 +114,17 @@ struct atcs_pwr_shift_input { u8 drv_state; /* 0 =3D operational, 1 =3D not operational */ } __packed; =20 +struct atcs_get_uma_size_output { + u16 size; /* structure size in bytes (includes size field) */ + u32 uma_size_mb; /* allocated UMA size in MB */ +} __packed; + +struct atcs_set_uma_allocation_size_input { + u16 size; /* structure size in bytes (includes size field) */ + u8 uma_size_index; /* UMA size index */ + u8 uma_size_type; /* UMA size type */ +} __packed; + /* AMD hw uses four ACPI control methods: * 1. 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Fri, 14 Nov 2025 00:43:26 -0800 From: "Yo-Jung Leo Lin (AMD)" Date: Fri, 14 Nov 2025 16:42:24 +0800 Subject: [PATCH v2 4/5] drm/amdgpu: add UMA allocation interfaces to sysfs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251114-vram-carveout-tuning-for-upstream-v2-4-4f6bdd48030d@amd.com> References: <20251114-vram-carveout-tuning-for-upstream-v2-0-4f6bdd48030d@amd.com> In-Reply-To: <20251114-vram-carveout-tuning-for-upstream-v2-0-4f6bdd48030d@amd.com> To: Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet CC: , , , , "Tsao, Anson" , "Mario Limonciello (AMD) (kernel.org)" , "Yo-Jung Leo Lin (AMD)" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5146; i=Leo.Lin@amd.com; h=from:subject:message-id; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 08:43:30.1413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfa96c94-79af-4176-4c3b-08de2359e315 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5623 Add two sysfs files as interfaces to inspect or change UMA carveout size. These files are: - uma_carveout_options: a read-only file listing all the available UMA allocation options and their index. - uma_carveout: a file that is both readable and writable. On read, it shows the index of the current setting. Writing a valid index into this file allows users to change the UMA carveout size to that option on the next boot. Co-developed-by: Mario Limonciello (AMD) Signed-off-by: Mario Limonciello (AMD) Signed-off-by: Yo-Jung Leo Lin (AMD) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 127 +++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_acpi.c index 444ab4102168..b9378f34eb79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include =20 @@ -1247,6 +1248,125 @@ int amdgpu_acpi_get_mem_info(struct amdgpu_device *= adev, int xcc_id, return -ENOENT; } =20 +static ssize_t uma_carveout_options_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_uma_carveout_info *uma_info =3D &amdgpu_acpi_priv.atcs.uma_= info; + ssize_t size =3D 0; + + if (!uma_info || !uma_info->num_entries) + return -ENODEV; + + for (int i =3D 0; i < uma_info->num_entries; i++) { + size +=3D sysfs_emit_at(buf, size, "%d: %s (%u GB)\n", + i, + uma_info->entries[i].name, + uma_info->entries[i].memory_carved); + } + + return size; +} +static DEVICE_ATTR_RO(uma_carveout_options); + +static ssize_t uma_carveout_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sysfs_emit(buf, "%u\n", amdgpu_acpi_priv.atcs.uma_info.uma_option_= index); +} + +static ssize_t uma_carveout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct amdgpu_uma_carveout_info *uma_info =3D &amdgpu_acpi_priv.atcs.uma_= info; + struct drm_device *ddev =3D dev_get_drvdata(dev); + struct amdgpu_device *adev =3D drm_to_adev(ddev); + struct amdgpu_uma_carveout_option *opt; + unsigned long val; + uint8_t flags; + int r; + + r =3D kstrtoul(buf, 10, &val); + if (r) + return r; + + if (val >=3D uma_info->num_entries) + return -EINVAL; + + opt =3D &uma_info->entries[val]; + + if (!(opt->flags & AMDGPU_UMA_FLAG_AUTO) && + !(opt->flags & AMDGPU_UMA_FLAG_CUSTOM)) { + drm_err_once(ddev, "Option %ul not supported due to lack of Custom/Auto = flag", r); + return -EINVAL; + } + + flags =3D opt->flags; + flags &=3D ~((flags & AMDGPU_UMA_FLAG_AUTO) >> 1); + + guard(mutex)(&uma_info->update_lock); + + r =3D amdgpu_acpi_set_uma_allocation_size(adev, val, flags); + if (r) + return r; + + uma_info->uma_option_index =3D val; + + return count; +} +static DEVICE_ATTR_RW(uma_carveout); + +static struct attribute *amdgpu_uma_attrs[] =3D { + &dev_attr_uma_carveout.attr, + &dev_attr_uma_carveout_options.attr, + NULL +}; + +const struct attribute_group amdgpu_uma_attr_group =3D { + .attrs =3D amdgpu_uma_attrs +}; + +static int amdgpu_acpi_uma_option_init(struct amdgpu_device *adev) +{ + struct amdgpu_atcs *atcs =3D &amdgpu_acpi_priv.atcs; + int rc; + + if (!atcs->functions.set_uma_allocation_size) + return -ENODEV; + + rc =3D amdgpu_atomfirmware_get_uma_carveout_info(adev, &atcs->uma_info); + if (rc) { + drm_dbg(adev_to_drm(adev), + "Failed to parse UMA carveout info from VBIOS: %d\n", rc); + goto out_info; + } + + mutex_init(&atcs->uma_info.update_lock); + + rc =3D devm_device_add_group(adev->dev, &amdgpu_uma_attr_group); + if (rc) { + drm_dbg(adev_to_drm(adev), "Failed to add UMA carveout sysfs interfaces = %d\n", rc); + goto out_attr; + } + + return 0; + +out_attr: + mutex_destroy(&atcs->uma_info.update_lock); +out_info: + return rc; +} + +static void amdgpu_acpi_uma_option_fini(void) +{ + struct amdgpu_uma_carveout_info *uma_info =3D &amdgpu_acpi_priv.atcs.uma_= info; + + mutex_destroy(&uma_info->update_lock); + uma_info->num_entries =3D 0; +} + /** * amdgpu_acpi_event - handle notify events * @@ -1291,6 +1411,12 @@ static int amdgpu_acpi_event(struct notifier_block *= nb, int amdgpu_acpi_init(struct amdgpu_device *adev) { struct amdgpu_atif *atif =3D &amdgpu_acpi_priv.atif; + int rc; + + rc =3D amdgpu_acpi_uma_option_init(adev); + + if (rc) + drm_dbg(adev_to_drm(adev), "Not creating uma carveout interfaces: %d", r= c); =20 if (atif->notifications.brightness_change) { if (adev->dc_enabled) { @@ -1343,6 +1469,7 @@ void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_= backlight_caps *caps) void amdgpu_acpi_fini(struct amdgpu_device *adev) { unregister_acpi_notifier(&adev->acpi_nb); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 08:43:33.6402 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f87391a-8b68-4937-8fd6-08de2359e52a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8530 Add documentation for the uma_carveout_options and uma_carveout attributes in sysfs Signed-off-by: Yo-Jung Leo Lin (AMD) Reviewed-by: Mario Limonciello (AMD) > --- --- Documentation/gpu/amdgpu/driver-misc.rst | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/Documentation/gpu/amdgpu/driver-misc.rst b/Documentation/gpu/a= mdgpu/driver-misc.rst index 25b0c857816e..afefab4fa0ac 100644 --- a/Documentation/gpu/amdgpu/driver-misc.rst +++ b/Documentation/gpu/amdgpu/driver-misc.rst @@ -128,3 +128,29 @@ smartshift_bias =20 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c :doc: smartshift_bias + +UMA Carveout +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Some versions of Atom ROM expose available options for the VRAM carveout s= izes, +and allow changes to the carveout size via the ATCS function code 0xA on s= upported +BIOS implementations. + +For those platforms, users can use the following file to set the carveout = size, +in a way similar to what Windows users can do in the "Tuning" tab in AMD +Adrenalin. + +Note that for BIOS implementations that don't support this, these files wi= ll not +be created at all. + +uma_carveout_options +-------------------- + +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c + :doc: uma_carveout_options + +uma_carveout +-------------------- + +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c + :doc: uma_carveout diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_acpi.c index b9378f34eb79..10cc6bf28a0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1248,6 +1248,24 @@ int amdgpu_acpi_get_mem_info(struct amdgpu_device *a= dev, int xcc_id, return -ENOENT; } =20 +/** + * DOC: uma_carveout_options + * + * This is a read-only file that lists all available UMA allocation + * options and their corresponding indices. Example output:: + * + * $ cat uma_carveout_options + * 0: Minimum (0 GB) + * 1: (1 GB) + * 2: (2 GB) + * 3: (4 GB) + * 4: (6 GB) + * 5: (8 GB) + * 6: (12 GB) + * 7: Medium (16 GB) + * 8: (24 GB) + * 9: High (32 GB) + */ static ssize_t uma_carveout_options_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -1269,6 +1287,17 @@ static ssize_t uma_carveout_options_show(struct devi= ce *dev, } static DEVICE_ATTR_RO(uma_carveout_options); =20 +/** + * DOC: uma_carveout + * + * This file is both readable and writable. When read, it shows the + * index of the current setting. Writing a valid index to this file + * allows users to change the UMA carveout size to the selected option + * on the next boot. + * + * The available options and their corresponding indices can be read + * from the uma_carveout_options file. + */ static ssize_t uma_carveout_show(struct device *dev, struct device_attribute *attr, char *buf) --=20 2.43.0