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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 17:26:10.9867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78ee245d-21ca-46b9-5963-08de23a2e7a1 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028CFC.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR10MB9656 X-Proofpoint-ORIG-GUID: aRj6LLo6cNgS9PagUEyIF_KzG2VrlnLa X-Authority-Analysis: v=2.4 cv=DPqCIiNb c=1 sm=1 tr=0 ts=69176636 cx=c_pps a=jcIAchfDan2QaPLKFZfxcQ==:117 a=d6reE3nDawwanmLcZTMRXA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=XWp4PHTOCikA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=8b9GpE9nAAAA:8 a=fTQ55MeeFdhIrGqxLO4A:9 a=QEXdDO2ut3YA:10 a=T3LWEMljR5ZiDmsYVIUa:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDE0MCBTYWx0ZWRfX642Znr+hRdpN qaJegSgw97oHw/VLFpAYMMsEJWJQ8D3wokSx+SDgV/o1xI1p+4g4uj2qogI54N7uHZy81mZeYhd GWiSruNioLtzd+fe9W1ZGxsJ10NIF4mm2JyKlCQo9iKAaZkcY0zSd6ZfyOzZPiiwqnn0ZzOfkD+ pe/zS80Ro9Km8Q44pSI53x1hR3Zs2vcCIgsopSUynxC1AzaF5isGGSLcWBs9KjzVylhNgppV/ok 6RC9g/e20K9GL3CObDxMD+loTi9o2K1j0QfbdWS0w2JtKS9JE31qH1mzgUsT/F0QElCQle4ZR1L O21qMy1CnUL/CDaV1zjdLXKrd+9j7WrfOEjG2aL7FT06D3LZB6JsFXwntOhokU4XNO0ECAbT9GF 0cJQ32iArvdCd2vrslirIY1NyIVkxA== X-Proofpoint-GUID: aRj6LLo6cNgS9PagUEyIF_KzG2VrlnLa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_05,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140140 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 ++++++++++ arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 11 +++++++++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 12 ++++++++++++ arch/arm/boot/dts/st/stm32f746.dtsi | 5 +++++ arch/arm/boot/dts/st/stm32f769-disco.dts | 12 ++++++++++++ 5 files changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st= /stm32746g-eval.dts index e9ac37b6eca0..26c5796a81fb 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -213,6 +213,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/= st/stm32f7-pinctrl.dtsi index 97fc3fb5a9ca..6b01c3c84272 100644 --- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -24,6 +24,7 @@ gpioa: gpio@40020000 { reg =3D <0x0 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name =3D "GPIOA"; + bootph-all; }; =20 gpiob: gpio@40020400 { @@ -34,6 +35,7 @@ gpiob: gpio@40020400 { reg =3D <0x400 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name =3D "GPIOB"; + bootph-all; }; =20 gpioc: gpio@40020800 { @@ -44,6 +46,7 @@ gpioc: gpio@40020800 { reg =3D <0x800 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name =3D "GPIOC"; + bootph-all; }; =20 gpiod: gpio@40020c00 { @@ -54,6 +57,7 @@ gpiod: gpio@40020c00 { reg =3D <0xc00 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name =3D "GPIOD"; + bootph-all; }; =20 gpioe: gpio@40021000 { @@ -64,6 +68,7 @@ gpioe: gpio@40021000 { reg =3D <0x1000 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name =3D "GPIOE"; + bootph-all; }; =20 gpiof: gpio@40021400 { @@ -74,6 +79,7 @@ gpiof: gpio@40021400 { reg =3D <0x1400 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name =3D "GPIOF"; + bootph-all; }; =20 gpiog: gpio@40021800 { @@ -84,6 +90,7 @@ gpiog: gpio@40021800 { reg =3D <0x1800 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name =3D "GPIOG"; + bootph-all; }; =20 gpioh: gpio@40021c00 { @@ -94,6 +101,7 @@ gpioh: gpio@40021c00 { reg =3D <0x1c00 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name =3D "GPIOH"; + bootph-all; }; =20 gpioi: gpio@40022000 { @@ -104,6 +112,7 @@ gpioi: gpio@40022000 { reg =3D <0x2000 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name =3D "GPIOI"; + bootph-all; }; =20 gpioj: gpio@40022400 { @@ -114,6 +123,7 @@ gpioj: gpio@40022400 { reg =3D <0x2400 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name =3D "GPIOJ"; + bootph-all; }; =20 gpiok: gpio@40022800 { @@ -124,6 +134,7 @@ gpiok: gpio@40022800 { reg =3D <0x2800 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name =3D "GPIOK"; + bootph-all; }; =20 cec_pins_a: cec-0 { diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/s= t/stm32f746-disco.dts index b57dbdce2f40..9545b14d77c3 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -169,6 +169,7 @@ touchscreen@38 { <dc { pinctrl-0 =3D <<dc_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; =20 port { @@ -207,6 +208,17 @@ &usart1 { status =3D "okay"; }; =20 + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm= 32f746.dtsi index 208f8c6dfc9d..b0f012de759c 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -54,6 +54,7 @@ clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; =20 clk-lse { @@ -76,6 +77,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; =20 soc { + bootph-all; timers2: timers@40000000 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -149,6 +151,7 @@ timers5: timers@40000c00 { reg =3D <0x40000C00 0x400>; clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; clock-names =3D "int"; + bootph-all; status =3D "disabled"; =20 pwm { @@ -645,6 +648,7 @@ ltdc: display-controller@40016800 { pwrcfg: power-config@40007000 { compatible =3D "st,stm32-power-config", "syscon"; reg =3D <0x40007000 0x400>; + bootph-all; }; =20 crc: crc@40023000 { @@ -663,6 +667,7 @@ rcc: rcc@40023800 { st,syscfg =3D <&pwrcfg>; assigned-clocks =3D <&rcc 1 CLK_HSE_RTC>; assigned-clock-rates =3D <1000000>; + bootph-all; }; =20 dma1: dma-controller@40026000 { diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index 535cfdc4681c..539517c7991e 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -133,6 +133,7 @@ &clk_hse { &dsi { #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 ports { @@ -178,6 +179,7 @@ &i2c1 { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -221,6 +223,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; --=20 2.43.0