From nobody Tue Feb 10 18:57:59 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 129BD308F36 for ; Fri, 14 Nov 2025 09:31:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763112681; cv=none; b=ODrxMgetvq0qIczOG7uv6vcKa8TiTXl474QHnvE3Ms8GzeaK1Y1///4T4sVrQLVwjtpyh99Z2/d7kfDES5Wjg/S0ube3RSYr9dPpWDXVQglNaofWF1K2KmjIaFaIVZrPy+QL9G4wQgy1eDK0OC/zQso4NLyqgNOIo+wYtnuHeE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763112681; c=relaxed/simple; bh=T6YuXb734/ygf+0vM/phTPDFUm5FVnnNeVk/SsxUKbg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DROkd7pNfjAwpAdexKC0C4ivX+CnW85W1Ad6WCyXQeCSvnLyD2IUn5BEuA2W/XfDrlT4PknS6L9LZIxW2jo5XPM42vSapTuW2JpRfXD7M/Fj29ieSh7Mi8Oo4RJ79Vwbao0O+GOGlXm6ZLHoYpX/S6/bgW556JCVXOFsjd/MJBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=3HI3a97Y; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="3HI3a97Y" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-b734fcbf1e3so267176666b.3 for ; Fri, 14 Nov 2025 01:31:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1763112677; x=1763717477; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=e5R21p9Vq6BqN2XMtSXYRBpypTUAovOSUjdiGreLgok=; b=3HI3a97YM9oNekOjNn6s8LSKvdVnERY7BUt3nU8Fn+iJ/T0+mxEHiSSMB2WIg4k2PT YzM2BUqzAV5RaRfyMcCF/Xj/Gr5jymdPA7dsHv+D6LE5Wjki6ddjLji3KqMJksfSlx5X 9IRIl+Brziy19GldNzSi2IgaVtKSnx8HHjDVN8y3PPfPI8mhLTwi2zegQwtZL1F+nFBQ PDLTII3O6tK6LpWdjq/HdrnlEccyEbA3BBe4eSV0ffjYyeHRm5a3mN47CrwAS28Lgf7r S0fk89awhtKYg3fPslhRM1KRx5Srq9yGM6tT4gs30FLKemVrhP/Mu+okUXwInhHYFx5v v8Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763112677; x=1763717477; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=e5R21p9Vq6BqN2XMtSXYRBpypTUAovOSUjdiGreLgok=; b=eTqVflzGdesc0j7Pk1HfOzKAh8gyzVS05XmZgNWLhuaHBto/qlrW4elwXlGzVA8TnG ogyCz9iHM/s8UkKu+4jhc/oSl9gXzJsPrfQ4XRmmxzyLZ9mm+A1JJ8h0d9BxUr3x1N/M qB2JlQAPi7oOKUj4d8oznykQuRBt0AuajCvU8ByF4A969P5l+RGKD8OBCYwR6svth3+z I2rUL4Gl6qYRWIUfPG4YoTyf5WARCJwUNsEuqBENshnMpwAtXKb96dCNaVBM/AGaHgIo lJ4qmDzn4jVgrOBMi/TN3s3Xds96+Vv28PSSSaqJ0QrQHAOMOQROUrsRMN+HNKHQBvGI eawA== X-Forwarded-Encrypted: i=1; AJvYcCWYXjdyQ3ul8DDZdYhRkUPbV52QbL2iNABzJGodXunGxiIC89AZDlfE+P19jlO2LMMGHf6sVNMXiFICL/8=@vger.kernel.org X-Gm-Message-State: AOJu0YzGo0jRvTVhvUaOM3l9LGtAhHykujoOH3o2F6zt6j48azfd7Sui NF7rnXlN7Ms5atal9/uiOphO2dgoL/6IxvZMGvFTm3S2CgITj0T+Qbol6UFJdkmDZSw= X-Gm-Gg: ASbGncuxb7rkAfV6t6YL+wCauInvg/qKDgIhjN5nIzBhTEnWrx2C0Snl1+X0rFRaYZd Bo4+ySBdOpLrtpBMxr7EfemOcsQ0BC+flv5nJTizyfMr6gYJhm3/y0VZginriu9knloj2K/YXtB v5rcI9RdU2Ixp5VHScTCROjsdJSKhmZ5zAWMOsT4venDgHcBlWmzcXmX6Qn3gG56mWc9wqomXqC p89ttuoGXT8JYAE6FRSS4rP9rNqYQ8BueilOVKKsfoRUpq0Fr6g+3mGQeK3JRnYfLoNdumft4Xd VSvg+zZme0VUtKNpoWhi+h/bPZL18kROievFVilM45010dRfE/76+w3bEvkKRy/dv/h3rUsFjPE emXEskAeYomnMe8JTOSdrU89wUIwJ+/dbz9KLqLVSOtWNJqCfps7Bwa9UXac+WfIs281umtzedZ 092wjsFm1AwBN/wZy4qCifWTFXQ2gD1xFSC9xeaNZ0EasOw4eXePwnHqi/jIMkV+MDtaViJOGEV jRpqkQILFojDGA0Kz0clu7MX1sfg93lKA== X-Google-Smtp-Source: AGHT+IHv+zVA9CAHVMA5Y+PURmSek6BBWv4SIg7yr9zgsWTKPeHzlLdjTuVq7uNp92wbkneltu4w9w== X-Received: by 2002:a17:907:a41:b0:b73:3af7:b6e5 with SMTP id a640c23a62f3a-b73678d2b45mr239348866b.15.1763112677287; Fri, 14 Nov 2025 01:31:17 -0800 (PST) Received: from [192.168.101.179] (2001-1c04-0509-ec01-156d-fa6e-7f19-0b67.cable.dynamic.v6.ziggo.nl. [2001:1c04:509:ec01:156d:fa6e:7f19:b67]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fd80841sm352104366b.41.2025.11.14.01.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 01:31:16 -0800 (PST) From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:12 +0100 Subject: [PATCH v2 4/5] interconnect: qcom: sm6350: enable QoS configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-sm6350-icc-qos-v2-4-6af348cb9c69@fairphone.com> References: <20251114-sm6350-icc-qos-v2-0-6af348cb9c69@fairphone.com> In-Reply-To: <20251114-sm6350-icc-qos-v2-0-6af348cb9c69@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763112672; l=15166; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=T6YuXb734/ygf+0vM/phTPDFUm5FVnnNeVk/SsxUKbg=; b=0rr2TTujwI8WIVZUuf2lQzNvsuDWnCIPjQfsRi8bVimMZWw3REMj6HZrlevLNSiYuSGVp7IEl xdAbGD5fqUNDpw5IwM95ipZbSfHM7gRKA975nHq1GZJFbgcVe3he+MG X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Enable QoS configuration for master ports with predefined values for priority and urgency forwarding. While this does require some "clocks" to be specified in devicetree to work correctly, thanks to ".qos_requires_clocks =3D true," this is backwards compatible with old DT as QoS programming will be skipped for aggre1_noc and aggre2_noc when clocks are not provided. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss --- drivers/interconnect/qcom/sm6350.c | 288 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 288 insertions(+) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index 246549cb761e..d96bec1cbb26 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -150,26 +150,50 @@ static struct qcom_icc_node qhm_a1noc_cfg =3D { .link_nodes =3D { &srvc_aggre1_noc }, }; =20 +static struct qcom_icc_qosbox qhm_qup_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qhm_qup_0 =3D { .name =3D "qhm_qup_0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qup_0_qos, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_emmc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_emmc_qos, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x8000 }, + .prio =3D 4, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_ufs_mem_qos, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -182,58 +206,113 @@ static struct qcom_icc_node qhm_a2noc_cfg =3D { .link_nodes =3D { &srvc_aggre2_noc }, }; =20 +static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox qhm_qup_1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; static struct qcom_icc_node qhm_qup_1 =3D { .name =3D "qhm_qup_1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qup_1_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox qxm_crypto_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x6000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox qxm_ipa_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_ipa_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_qdss_etr_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_qdss_etr_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_sdc2_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_sdc2_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_usb3_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -278,18 +357,34 @@ static struct qcom_icc_node qup1_core_master =3D { .link_nodes =3D { &qup1_core_slave }, }; =20 +static struct qcom_icc_qosbox qnm_npu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0xf000, 0x11000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_npu_qos, .num_links =3D 1, .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 +static struct qcom_icc_qosbox qxm_npu_dsp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_npu_dsp =3D { .name =3D "qxm_npu_dsp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_npu_dsp_qos, .num_links =3D 1, .link_nodes =3D { &qns_cdsp_gemnoc }, }; @@ -401,19 +496,35 @@ static struct qcom_icc_node qhm_cnoc_dc_noc =3D { &qhs_gemnoc }, }; =20 +static struct qcom_icc_qosbox acm_apps_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x2f100, 0x2f000 }, + .prio =3D 0, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &acm_apps_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox acm_sys_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x35000 }, + .prio =3D 6, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &acm_sys_tcu_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, @@ -429,53 +540,101 @@ static struct qcom_icc_node qhm_gemnoc_cfg =3D { &qhs_mdsp_ms_mpu_cfg }, }; =20 +static struct qcom_icc_qosbox qnm_cmpnoc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x2e000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_cmpnoc_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x30000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x34000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox qnm_snoc_gc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x32000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_snoc_gc_qos, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; =20 +static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x31000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; =20 +static struct qcom_icc_qosbox qxm_gpu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x33000, 0x33080 }, + .prio =3D 0, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qxm_gpu_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, @@ -497,50 +656,98 @@ static struct qcom_icc_node qhm_mnoc_cfg =3D { .link_nodes =3D { &srvc_mnoc }, }; =20 +static struct qcom_icc_qosbox qnm_video0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_video0_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qnm_video_cvp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 5, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_video_cvp_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qxm_camnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0xa000, 0xb000 }, + .prio =3D 3, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_camnoc_hf =3D { .name =3D "qxm_camnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qxm_camnoc_hf_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; =20 +static struct qcom_icc_qosbox qxm_camnoc_icp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 5, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_camnoc_icp =3D { .name =3D "qxm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_camnoc_icp_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qxm_camnoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 3, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qxm_camnoc_sf_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qxm_mdp0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 3, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qxm_mdp0_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -616,19 +823,35 @@ static struct qcom_icc_node qnm_gemnoc =3D { &xs_qdss_stm }, }; =20 +static struct qcom_icc_qosbox qxm_pimem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_pimem_qos, .num_links =3D 2, .link_nodes =3D { &qns_gemnoc_gc, &qxs_imem }, }; =20 +static struct qcom_icc_qosbox xm_gic_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 3, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_gic_qos, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -1388,11 +1611,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_SERVICE_A1NOC] =3D &srvc_aggre1_noc, }; =20 +static const struct regmap_config sm6350_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x15080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_aggre1_noc =3D { + .config =3D &sm6350_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1413,11 +1646,21 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_SERVICE_A2NOC] =3D &srvc_aggre2_noc, }; =20 +static const struct regmap_config sm6350_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f880, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_aggre2_noc =3D { + .config =3D &sm6350_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1459,7 +1702,16 @@ static struct qcom_icc_node * const compute_noc_node= s[] =3D { [SLAVE_CDSP_GEM_NOC] =3D &qns_cdsp_gemnoc, }; =20 +static const struct regmap_config sm6350_compute_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f880, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_compute_noc =3D { + .config =3D &sm6350_compute_noc_regmap_config, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1532,7 +1784,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_LLCC_CFG] =3D &qhs_llcc, }; =20 +static const struct regmap_config sm6350_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_dc_noc =3D { + .config =3D &sm6350_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1561,7 +1822,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_SERVICE_GEM_NOC] =3D &srvc_gemnoc, }; =20 +static const struct regmap_config sm6350_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3e200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_gem_noc =3D { + .config =3D &sm6350_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1588,7 +1858,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, }; =20 +static const struct regmap_config sm6350_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c100, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_mmss_noc =3D { + .config =3D &sm6350_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1643,7 +1922,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config sm6350_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_system_noc =3D { + .config =3D &sm6350_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, --=20 2.51.2