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[2001:1c04:509:ec01:156d:fa6e:7f19:b67]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fedb91bsm366887766b.70.2025.11.14.03.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 03:28:25 -0800 (PST) From: Luca Weiss Date: Fri, 14 Nov 2025 12:15:25 +0100 Subject: [PATCH v2 2/3] media: qcom: camss: Add SM6350 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-sm6350-camss-v2-2-d1ff67da33b6@fairphone.com> References: <20251114-sm6350-camss-v2-0-d1ff67da33b6@fairphone.com> In-Reply-To: <20251114-sm6350-camss-v2-0-d1ff67da33b6@fairphone.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763119703; l=15891; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=gZ6RM7I7LMS7N4TaJM+UaMiCicFfzV9gRmHs9P09fTM=; b=qIBI/b3jUToxQZ1nwi3vgj/W4tukRyQoHQPFSabXkfD5mJowFjnjsiXAdoQnn7JbfR3wXzXA6 s+X0nMio/5ZCSiZAM5pyR0cuZH6nhLq0InKqRVTW/4X5OJBFdJ9ahOk X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the necessary support for CAMSS on the SM6350 SoC. Signed-off-by: Luca Weiss --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 125 +++++++++++ drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 249 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 377 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index a229ba04b158..3e44b0c8298d 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -398,6 +398,126 @@ csiphy_lane_regs lane_regs_sm8250[] =3D { {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.2.3 2PH */ +static const struct +csiphy_lane_regs lane_regs_sm6350[] =3D { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0260, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x065C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0660, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, +}; + /* 14nm 2PH v 2.0.1 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_qcm2290[] =3D { @@ -908,6 +1028,7 @@ static bool csiphy_is_gen2(u32 version) =20 switch (version) { case CAMSS_2290: + case CAMSS_6350: case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: @@ -999,6 +1120,10 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_qcm2290[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); break; + case CAMSS_6350: + regs->lane_regs =3D &lane_regs_sm6350[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); + break; case CAMSS_7280: case CAMSS_8250: regs->lane_regs =3D &lane_regs_sm8250[0]; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index dff8d0a1e8c2..336838b1340b 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -339,6 +339,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, return sink_code; } break; + case CAMSS_6350: case CAMSS_660: case CAMSS_2290: case CAMSS_7280: @@ -1989,6 +1990,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) int ret =3D 8; =20 switch (vfe->camss->res->version) { + case CAMSS_6350: case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2fbcd0e343aa..270f5a1341c6 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1318,6 +1318,241 @@ static const struct camss_subdev_resources vfe_res_= 845[] =3D { } }; =20 +static const struct camss_subdev_resources csiphy_res_6350[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { "vdd-csiphy-0p9", "vdd-csiphy-1p25" }, + .clock =3D { "csiphy0", "csiphy0_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { "vdd-csiphy-0p9", "vdd-csiphy-1p25" }, + .clock =3D { "csiphy1", "csiphy1_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { "vdd-csiphy-0p9", "vdd-csiphy-1p25" }, + .clock =3D { "csiphy2", "csiphy2_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { "vdd-csiphy-0p9", "vdd-csiphy-1p25" }, + .clock =3D { "csiphy3", "csiphy3_timer" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + } +}; + +static const struct camss_subdev_resources csid_res_6350[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "vfe0_csid", "vfe0_cphy_rx", "vfe0" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "vfe1_csid", "vfe1_cphy_rx", "vfe1" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "vfe2_csid", "vfe2_cphy_rx", "vfe2" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite" }, + .clock_rate =3D { { 300000000, 384000000, 400000000 }, + { 0 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite" }, + .interrupt =3D { "csid_lite" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen2, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + } +}; + +static const struct camss_subdev_resources vfe_res_6350[] =3D { + /* VFE0 */ + { + .regulators =3D {}, + .clock =3D { "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "vfe0", "vfe0_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000, 80000000 }, + { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators =3D {}, + .clock =3D { "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "vfe1", "vfe1_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000, 80000000 }, + { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 */ + { + .regulators =3D {}, + .clock =3D { "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "vfe2", "vfe2_axi", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000, 80000000 }, + { 19200000 }, + { 0 }, + { 320000000, 404000000, 480000000, 600000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "vfe_lite", "cam_axi", "soc_ahb" }, + .clock_rate =3D { { 19200000, 80000000 }, + { 19200000 }, + { 0 }, + { 400000000, 480000000 }, + { 0 } }, + .reg =3D { "vfe_lite" }, + .interrupt =3D { "vfe_lite" }, + .vfe =3D { + .is_lite =3D true, + .line_num =3D 4, + .hw_ops =3D &vfe_ops_170, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + +static const struct resources_icc icc_res_sm6350[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 0, + .icc_bw_tbl.peak =3D 300000, + }, + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_icp_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, +}; + static const struct camss_subdev_resources csiphy_res_8250[] =3D { /* CSIPHY0 */ { @@ -4398,6 +4633,19 @@ static const struct camss_resources sdm845_resources= =3D { .vfe_num =3D ARRAY_SIZE(vfe_res_845), }; =20 +static const struct camss_resources sm6350_resources =3D { + .version =3D CAMSS_6350, + .pd_name =3D "top", + .csiphy_res =3D csiphy_res_6350, + .csid_res =3D csid_res_6350, + .vfe_res =3D vfe_res_6350, + .icc_res =3D icc_res_sm6350, + .icc_path_num =3D ARRAY_SIZE(icc_res_sm6350), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_6350), + .csid_num =3D ARRAY_SIZE(csid_res_6350), + .vfe_num =3D ARRAY_SIZE(vfe_res_6350), +}; + static const struct camss_resources sm8250_resources =3D { .version =3D CAMSS_8250, .pd_name =3D "top", @@ -4478,6 +4726,7 @@ static const struct of_device_id camss_dt_match[] =3D= { { .compatible =3D "qcom,sdm660-camss", .data =3D &sdm660_resources }, { .compatible =3D "qcom,sdm670-camss", .data =3D &sdm670_resources }, { .compatible =3D "qcom,sdm845-camss", .data =3D &sdm845_resources }, + { .compatible =3D "qcom,sm6350-camss", .data =3D &sm6350_resources }, { .compatible =3D "qcom,sm8250-camss", .data =3D &sm8250_resources }, { .compatible =3D "qcom,sm8550-camss", .data =3D &sm8550_resources }, { .compatible =3D "qcom,x1e80100-camss", .data =3D &x1e80100_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index a70fbc78ccc3..ae456ff4e612 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -77,6 +77,7 @@ enum pm_domain { }; =20 enum camss_version { + CAMSS_6350, CAMSS_660, CAMSS_2290, CAMSS_7280, --=20 2.51.2