From nobody Mon Feb 9 01:47:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2185B423157; Tue, 20 Jan 2026 12:22:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768911752; cv=none; b=CKL0WaImyyxAFR1aPSozgbxCaK6gigXGdzFYd6mNwvy8PzHdbZ7N7WrmdRt/hb+DecTHpCRbGBh6+VAcgpI4QklFON5bg1Dl78np7V2nYVlZ6vGTZpuBTQ8rX+KhTlf9cJmHAi2/31ARU+n8RmKUeSQfw/r/S2JpNtIepX9recI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768911752; c=relaxed/simple; bh=LJP01ZDiMZk6OcQI+p5HVN1PTrgvKnmv0e2XRGu7cI4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QkyHKM4LkrgJ9tK0asMTKVpohn2S3d4hGqOU7j8WVBbCDMtqRot39Mczz53bBvfIn5PK0XdM/AbhT/ZNMfjipjaeiCYoPzoWlSjkweRwP/F98t+ILiy0VZ3PG1AkJjMnad6VSeIdJxvOPFHleUXcu79Nk4kYM9AGB0pd/y90nMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QTkHf0IO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QTkHf0IO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 89413C2BC86; Tue, 20 Jan 2026 12:22:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768911751; bh=LJP01ZDiMZk6OcQI+p5HVN1PTrgvKnmv0e2XRGu7cI4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QTkHf0IOyDMlOQRoTPhWUShVu0H1j6YEWpOY8hstim23YvxfeawPY45jlhAHSASIF bOqHkus1q5AYKcggrvXb5q9A/sIOU6MFsC2x4PHHhlRDrkiIVOY06NkVjETM+HFeOX kb4ZmzPyPiIlMDTiY/U5enf9Wv+nHeTYAwfQGiHzQEgp80cwxcS0FOVRi7ISqoRwWL kTsddlKEKTEwnXPhoM90taRc9ZUKFsotTqoGmdCB7i6XAVTaZY0jOxgvF5XufGGNpR aY6DiOLTJtWqszPCRCC/7yj2A9apYNTEctigPZNEBBFDZdZ3Xxk+GjdHGOG0adyKUB 2CXMX+Zg9d8yw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E864D2ED12; Tue, 20 Jan 2026 12:22:31 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 20 Jan 2026 13:22:27 +0100 Subject: [PATCH v8 1/3] media: dt-bindings: add rockchip mipi csi-2 receiver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-rockchip-mipi-receiver-v8-1-bd1cf5cb9588@collabora.com> References: <20251114-rockchip-mipi-receiver-v8-0-bd1cf5cb9588@collabora.com> In-Reply-To: <20251114-rockchip-mipi-receiver-v8-0-bd1cf5cb9588@collabora.com> To: Michael Riesch , Chaoyi Chen , Kever Yang , Frank Li , Mehdi Djait , Bryan O'Donoghue , Laurent Pinchart , Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Nicolas Dufresne , Collabora Kernel Team , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768911749; l=5160; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=OgKl9RHS2qISqL1jKo3kMI1uxI5UDgx/C4nCyULXhQo=; b=HC8IXy/NfVcDmjyGbQyK6E6NH7m9+XrfZjZi8IPQ548SYdQB9wllPuBBkvFYTtYYyxyDfiQCM P42JtzCp86OBP4YXFCoNtp0frc1D/XfZDrv2xIcWqp/KTkNmjrk6cFO X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add documentation for the Rockchip MIPI CSI-2 Receiver. Signed-off-by: Michael Riesch Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michael Riesch --- .../bindings/media/rockchip,rk3568-mipi-csi2.yaml | 141 +++++++++++++++++= ++++ MAINTAINERS | 6 + 2 files changed, 147 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-c= si2.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi= 2.yaml new file mode 100644 index 000000000000..2c2bd87582eb --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,rk3568-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip MIPI CSI-2 Receiver + +maintainers: + - Michael Riesch + +description: + The Rockchip MIPI CSI-2 Receiver is a CSI-2 bridge with one input port a= nd + one output port. It receives the data with the help of an external MIPI = PHY + (C-PHY or D-PHY) and passes it to the Rockchip Video Capture (VICAP) blo= ck. + +properties: + compatible: + enum: + - rockchip,rk3568-mipi-csi2 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt that signals changes in CSI2HOST_ERR1. + - description: Interrupt that signals changes in CSI2HOST_ERR2. + + interrupt-names: + items: + - const: err1 + - const: err2 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + description: MIPI C-PHY or D-PHY. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port node. Connect to e.g., a MIPI CSI-2 image = sensor. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - bus-type + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output port connected to a Rockchip VICAP port. + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - phys + - ports + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + csi: csi@fdfb0000 { + compatible =3D "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdfb0000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI2HOST1>; + phys =3D <&csi_dphy>; + power-domains =3D <&power RK3568_PD_VI>; + resets =3D <&cru SRST_P_CSI2HOST1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi_in: port@0 { + reg =3D <0>; + + csi_input: endpoint { + bus-type =3D ; + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&imx415_output>; + }; + }; + + csi_out: port@1 { + reg =3D <1>; + + csi_output: endpoint { + remote-endpoint =3D <&vicap_mipi_input>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5560da0deb71..1d1589feaf95 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25364,6 +25364,12 @@ S: Maintained F: drivers/i2c/busses/i2c-designware-amdisp.c F: include/linux/soc/amd/isp4_misc.h =20 +SYNOPSYS DESIGNWARE MIPI CSI-2 RECEIVER DRIVER +M: Michael Riesch +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml + SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER M: Jaehoon Chung M: Shawn Lin --=20 2.39.5 From nobody Mon Feb 9 01:47:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25B4F42315A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-rockchip-mipi-receiver-v8-2-bd1cf5cb9588@collabora.com> References: <20251114-rockchip-mipi-receiver-v8-0-bd1cf5cb9588@collabora.com> In-Reply-To: <20251114-rockchip-mipi-receiver-v8-0-bd1cf5cb9588@collabora.com> To: Michael Riesch , Chaoyi Chen , Kever Yang , Frank Li , Mehdi Djait , Bryan O'Donoghue , Laurent Pinchart , Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Nicolas Dufresne , Collabora Kernel Team , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768911749; l=22249; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=5lkoTgjwEJ1CqpLbjkI9WNG/JACfxfDcBdgf93wdlnY=; b=Uf8UIYyrvdo+YjJLH0rmPayG7jZP6w6mYHJXbDbjXkcTb79OrbfMp8tSUMn87eyA89xDNOxsf eUEWQy4W5J9AhRQZpRhH81bKzexOwL1ZZbGrpV6BWqCho0wK7n7Uhoo X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Synopsys DesignWare MIPI CSI-2 Receiver is a CSI-2 bridge with one input port and one output port. It receives the data with the help of an external MIPI PHY (C-PHY or D-PHY) and passes it to e.g., the Rockchip Video Capture (VICAP) block on recent Rockchip SoCs. Add a V4L2 subdevice driver for this unit. Signed-off-by: Michael Riesch Reviewed-by: Bryan O'Donoghue Reviewed-by: Mehdi Djait Signed-off-by: Michael Riesch Reviewed-by: Frank Li --- MAINTAINERS | 1 + drivers/media/platform/synopsys/Kconfig | 18 + drivers/media/platform/synopsys/Makefile | 2 + drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 726 +++++++++++++++++++= ++++ 4 files changed, 747 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1d1589feaf95..62ccdc72384d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25369,6 +25369,7 @@ M: Michael Riesch L: linux-media@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml +F: drivers/media/platform/synopsys/dw-mipi-csi2rx.c =20 SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER M: Jaehoon Chung diff --git a/drivers/media/platform/synopsys/Kconfig b/drivers/media/platfo= rm/synopsys/Kconfig index 4fd521f78425..e798ec00b189 100644 --- a/drivers/media/platform/synopsys/Kconfig +++ b/drivers/media/platform/synopsys/Kconfig @@ -1,3 +1,21 @@ # SPDX-License-Identifier: GPL-2.0-only =20 source "drivers/media/platform/synopsys/hdmirx/Kconfig" + +config VIDEO_DW_MIPI_CSI2RX + tristate "Synopsys DesignWare MIPI CSI-2 Receiver" + depends on VIDEO_DEV + depends on V4L_PLATFORM_DRIVERS + depends on PM && COMMON_CLK + select MEDIA_CONTROLLER + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + help + The Synopsys DesignWare MIPI CSI-2 Receiver is a CSI-2 bridge with + one input port and one output port. It receives the data with the + help of an external MIPI PHY (C-PHY or D-PHY) and passes it to e.g., + the Rockchip Video Capture (VICAP) block on recent Rockchip SoCs. + This is a driver for this unit. + + To compile this driver as a module, choose M here: the module + will be called dw-mipi-csi2rx. diff --git a/drivers/media/platform/synopsys/Makefile b/drivers/media/platf= orm/synopsys/Makefile index 3b12c574dd67..e0232ee23304 100644 --- a/drivers/media/platform/synopsys/Makefile +++ b/drivers/media/platform/synopsys/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D hdmirx/ + +obj-$(CONFIG_VIDEO_DW_MIPI_CSI2RX) +=3D dw-mipi-csi2rx.o diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/med= ia/platform/synopsys/dw-mipi-csi2rx.c new file mode 100644 index 000000000000..29119a1a8d38 --- /dev/null +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare MIPI CSI-2 Receiver Driver + * + * Copyright (C) 2019 Rockchip Electronics Co., Ltd. + * Copyright (C) 2025 Michael Riesch + * Copyright (C) 2026 Collabora, Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define DW_MIPI_CSI2RX_N_LANES 0x04 +#define DW_MIPI_CSI2RX_RESETN 0x10 +#define DW_MIPI_CSI2RX_PHY_STATE 0x14 +#define DW_MIPI_CSI2RX_ERR1 0x20 +#define DW_MIPI_CSI2RX_ERR2 0x24 +#define DW_MIPI_CSI2RX_MSK1 0x28 +#define DW_MIPI_CSI2RX_MSK2 0x2c +#define DW_MIPI_CSI2RX_CONTROL 0x40 + +#define SW_CPHY_EN(x) ((x) << 0) +#define SW_DSI_EN(x) ((x) << 4) +#define SW_DATATYPE_FS(x) ((x) << 8) +#define SW_DATATYPE_FE(x) ((x) << 14) +#define SW_DATATYPE_LS(x) ((x) << 20) +#define SW_DATATYPE_LE(x) ((x) << 26) + +#define DW_MIPI_CSI2RX_CLKS_MAX 1 + +enum { + DW_MIPI_CSI2RX_PAD_SINK, + DW_MIPI_CSI2RX_PAD_SRC, + DW_MIPI_CSI2RX_PAD_MAX, +}; + +struct dw_mipi_csi2rx_format { + u32 code; + u8 depth; + u8 csi_dt; +}; + +struct dw_mipi_csi2rx_device { + struct device *dev; + + void __iomem *base_addr; + struct clk_bulk_data *clks; + unsigned int clks_num; + struct phy *phy; + struct reset_control *reset; + + const struct dw_mipi_csi2rx_format *formats; + unsigned int formats_num; + + struct media_pad pads[DW_MIPI_CSI2RX_PAD_MAX]; + struct v4l2_async_notifier notifier; + struct v4l2_subdev sd; + + enum v4l2_mbus_type bus_type; + u32 lanes_num; +}; + +static const struct v4l2_mbus_framefmt default_format =3D { + .width =3D 3840, + .height =3D 2160, + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_RAW, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_FULL_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_NONE, +}; + +static const struct dw_mipi_csi2rx_format formats[] =3D { + /* YUV formats */ + { + .code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + { + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + { + .code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + { + .code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .depth =3D 16, + .csi_dt =3D MIPI_CSI2_DT_YUV422_8B, + }, + /* RGB formats */ + { + .code =3D MEDIA_BUS_FMT_RGB888_1X24, + .depth =3D 24, + .csi_dt =3D MIPI_CSI2_DT_RGB888, + }, + { + .code =3D MEDIA_BUS_FMT_BGR888_1X24, + .depth =3D 24, + .csi_dt =3D MIPI_CSI2_DT_RGB888, + }, + /* Bayer formats */ + { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .depth =3D 8, + .csi_dt =3D MIPI_CSI2_DT_RAW8, + }, + { + .code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .depth =3D 10, + .csi_dt =3D MIPI_CSI2_DT_RAW10, + }, + { + .code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .depth =3D 12, + .csi_dt =3D MIPI_CSI2_DT_RAW12, + }, +}; + +static inline struct dw_mipi_csi2rx_device *to_csi2(struct v4l2_subdev *sd) +{ + return container_of(sd, struct dw_mipi_csi2rx_device, sd); +} + +static inline void dw_mipi_csi2rx_write(struct dw_mipi_csi2rx_device *csi2, + unsigned int addr, u32 val) +{ + writel(val, csi2->base_addr + addr); +} + +static inline u32 dw_mipi_csi2rx_read(struct dw_mipi_csi2rx_device *csi2, + unsigned int addr) +{ + return readl(csi2->base_addr + addr); +} + +static const struct dw_mipi_csi2rx_format * +dw_mipi_csi2rx_find_format(struct dw_mipi_csi2rx_device *csi2, u32 mbus_co= de) +{ + WARN_ON(csi2->formats_num =3D=3D 0); + + for (unsigned int i =3D 0; i < csi2->formats_num; i++) { + const struct dw_mipi_csi2rx_format *format =3D &csi2->formats[i]; + + if (format->code =3D=3D mbus_code) + return format; + } + + return NULL; +} + +static int dw_mipi_csi2rx_start(struct dw_mipi_csi2rx_device *csi2) +{ + struct media_pad *source_pad; + union phy_configure_opts opts; + u32 lanes =3D csi2->lanes_num; + u32 control =3D 0; + s64 link_freq; + int ret; + + if (lanes < 1 || lanes > 4) + return -EINVAL; + + source_pad =3D media_pad_remote_pad_unique( + &csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]); + if (IS_ERR(source_pad)) + return PTR_ERR(source_pad); + + /* set mult and div to 0, thus completely rely on V4L2_CID_LINK_FREQ */ + link_freq =3D v4l2_get_link_freq(source_pad, 0, 0); + if (link_freq < 0) + return link_freq; + + switch (csi2->bus_type) { + case V4L2_MBUS_CSI2_DPHY: + struct phy_configure_opts_mipi_dphy *cfg =3D &opts.mipi_dphy; + + ret =3D phy_mipi_dphy_get_default_config_for_hsclk(link_freq * 2, + lanes, cfg); + if (ret) + return ret; + + ret =3D phy_set_mode(csi2->phy, PHY_MODE_MIPI_DPHY); + if (ret) + return ret; + + ret =3D phy_configure(csi2->phy, &opts); + if (ret) + return ret; + + control |=3D SW_CPHY_EN(0); + break; + + case V4L2_MBUS_CSI2_CPHY: + /* TODO: implement CPHY configuration */ + return -EOPNOTSUPP; + default: + return -EINVAL; + } + + control |=3D SW_DATATYPE_FS(0x00) | SW_DATATYPE_FE(0x01) | + SW_DATATYPE_LS(0x02) | SW_DATATYPE_LE(0x03); + + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_N_LANES, lanes - 1); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_CONTROL, control); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 1); + + return phy_power_on(csi2->phy); +} + +static void dw_mipi_csi2rx_stop(struct dw_mipi_csi2rx_device *csi2) +{ + phy_power_off(csi2->phy); + + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK1, ~0); + dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK2, ~0); +} + +static const struct media_entity_operations dw_mipi_csi2rx_media_ops =3D { + .link_validate =3D v4l2_subdev_link_validate, +}; + +static int +dw_mipi_csi2rx_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct dw_mipi_csi2rx_device *csi2 =3D to_csi2(sd); + + switch (code->pad) { + case DW_MIPI_CSI2RX_PAD_SRC: + const struct v4l2_mbus_framefmt *sink_fmt; + + if (code->index) + return -EINVAL; + + sink_fmt =3D v4l2_subdev_state_get_format( + sd_state, DW_MIPI_CSI2RX_PAD_SINK); + code->code =3D sink_fmt->code; + + return 0; + case DW_MIPI_CSI2RX_PAD_SINK: + if (code->index > csi2->formats_num) + return -EINVAL; + + code->code =3D csi2->formats[code->index].code; + return 0; + default: + return -EINVAL; + } +} + +static int dw_mipi_csi2rx_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *format) +{ + struct dw_mipi_csi2rx_device *csi2 =3D to_csi2(sd); + const struct dw_mipi_csi2rx_format *fmt; + struct v4l2_mbus_framefmt *sink, *src; + + /* the format on the source pad always matches the sink pad */ + if (format->pad =3D=3D DW_MIPI_CSI2RX_PAD_SRC) + return v4l2_subdev_get_fmt(sd, state, format); + + sink =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); + if (!sink) + return -EINVAL; + + fmt =3D dw_mipi_csi2rx_find_format(csi2, format->format.code); + if (!fmt) + format->format =3D default_format; + + *sink =3D format->format; + + /* propagate the format to the source pad */ + src =3D v4l2_subdev_state_get_opposite_stream_format(state, format->pad, + format->stream); + if (!src) + return -EINVAL; + + *src =3D *sink; + + return 0; +} + +static int dw_mipi_csi2rx_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + int ret; + + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); + if (ret) + return ret; + + return v4l2_subdev_set_routing_with_fmt(sd, state, routing, + &default_format); +} + +static int dw_mipi_csi2rx_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct dw_mipi_csi2rx_device *csi2 =3D to_csi2(sd); + struct v4l2_subdev *remote_sd; + struct media_pad *sink_pad, *remote_pad; + struct device *dev =3D csi2->dev; + u64 mask; + int ret; + + sink_pad =3D &sd->entity.pads[DW_MIPI_CSI2RX_PAD_SINK]; + remote_pad =3D media_pad_remote_pad_first(sink_pad); + remote_sd =3D media_entity_to_v4l2_subdev(remote_pad->entity); + + mask =3D v4l2_subdev_state_xlate_streams(state, DW_MIPI_CSI2RX_PAD_SINK, + DW_MIPI_CSI2RX_PAD_SRC, + &streams_mask); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + goto err; + + ret =3D dw_mipi_csi2rx_start(csi2); + if (ret) { + dev_err(dev, "failed to enable CSI hardware\n"); + goto err_pm_runtime_put; + } + + ret =3D v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask); + if (ret) + goto err_csi_stop; + + return 0; + +err_csi_stop: + dw_mipi_csi2rx_stop(csi2); +err_pm_runtime_put: + pm_runtime_put(dev); +err: + return ret; +} + +static int dw_mipi_csi2rx_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct dw_mipi_csi2rx_device *csi2 =3D to_csi2(sd); + struct v4l2_subdev *remote_sd; + struct media_pad *sink_pad, *remote_pad; + struct device *dev =3D csi2->dev; + u64 mask; + int ret; + + sink_pad =3D &sd->entity.pads[DW_MIPI_CSI2RX_PAD_SINK]; + remote_pad =3D media_pad_remote_pad_first(sink_pad); + remote_sd =3D media_entity_to_v4l2_subdev(remote_pad->entity); + + mask =3D v4l2_subdev_state_xlate_streams(state, DW_MIPI_CSI2RX_PAD_SINK, + DW_MIPI_CSI2RX_PAD_SRC, + &streams_mask); + + ret =3D v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); + + dw_mipi_csi2rx_stop(csi2); + + pm_runtime_put(dev); + + return ret; +} + +static const struct v4l2_subdev_pad_ops dw_mipi_csi2rx_pad_ops =3D { + .enum_mbus_code =3D dw_mipi_csi2rx_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D dw_mipi_csi2rx_set_fmt, + .set_routing =3D dw_mipi_csi2rx_set_routing, + .enable_streams =3D dw_mipi_csi2rx_enable_streams, + .disable_streams =3D dw_mipi_csi2rx_disable_streams, +}; + +static const struct v4l2_subdev_ops dw_mipi_csi2rx_ops =3D { + .pad =3D &dw_mipi_csi2rx_pad_ops, +}; + +static int dw_mipi_csi2rx_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_subdev_route routes[] =3D { + { + .sink_pad =3D DW_MIPI_CSI2RX_PAD_SINK, + .sink_stream =3D 0, + .source_pad =3D DW_MIPI_CSI2RX_PAD_SRC, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, + }, + }; + struct v4l2_subdev_krouting routing =3D { + .len_routes =3D ARRAY_SIZE(routes), + .num_routes =3D ARRAY_SIZE(routes), + .routes =3D routes, + }; + + return v4l2_subdev_set_routing_with_fmt(sd, state, &routing, + &default_format); +} + +static const struct v4l2_subdev_internal_ops dw_mipi_csi2rx_internal_ops = =3D { + .init_state =3D dw_mipi_csi2rx_init_state, +}; + +static int dw_mipi_csi2rx_notifier_bound(struct v4l2_async_notifier *notif= ier, + struct v4l2_subdev *sd, + struct v4l2_async_connection *asd) +{ + struct dw_mipi_csi2rx_device *csi2 =3D + container_of(notifier, struct dw_mipi_csi2rx_device, notifier); + struct media_pad *sink_pad =3D &csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]; + int ret; + + ret =3D v4l2_create_fwnode_links_to_pad(sd, sink_pad, + MEDIA_LNK_FL_ENABLED); + if (ret) { + dev_err(csi2->dev, "failed to link source pad of %s\n", + sd->name); + return ret; + } + + return 0; +} + +static const struct v4l2_async_notifier_operations dw_mipi_csi2rx_notifier= _ops =3D { + .bound =3D dw_mipi_csi2rx_notifier_bound, +}; + +static int dw_mipi_csi2rx_register_notifier(struct dw_mipi_csi2rx_device *= csi2) +{ + struct v4l2_async_connection *asd; + struct v4l2_async_notifier *ntf =3D &csi2->notifier; + struct v4l2_fwnode_endpoint vep; + struct v4l2_subdev *sd =3D &csi2->sd; + struct device *dev =3D csi2->dev; + int ret; + + struct fwnode_handle *ep __free(fwnode_handle) =3D + fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); + if (!ep) + return dev_err_probe(dev, -ENODEV, "failed to get endpoint\n"); + + vep.bus_type =3D V4L2_MBUS_UNKNOWN; + ret =3D v4l2_fwnode_endpoint_parse(ep, &vep); + if (ret) + return dev_err_probe(dev, ret, "failed to parse endpoint\n"); + + if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY && + vep.bus_type !=3D V4L2_MBUS_CSI2_CPHY) + return dev_err_probe(dev, -EINVAL, + "invalid bus type of endpoint\n"); + + csi2->bus_type =3D vep.bus_type; + csi2->lanes_num =3D vep.bus.mipi_csi2.num_data_lanes; + + v4l2_async_subdev_nf_init(ntf, sd); + ntf->ops =3D &dw_mipi_csi2rx_notifier_ops; + + asd =3D v4l2_async_nf_add_fwnode_remote(ntf, ep, + struct v4l2_async_connection); + if (IS_ERR(asd)) { + ret =3D PTR_ERR(asd); + goto err_nf_cleanup; + } + + ret =3D v4l2_async_nf_register(ntf); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to register notifier\n"); + goto err_nf_cleanup; + } + + return 0; + +err_nf_cleanup: + v4l2_async_nf_cleanup(ntf); + + return ret; +} + +static int dw_mipi_csi2rx_register(struct dw_mipi_csi2rx_device *csi2) +{ + struct media_pad *pads =3D csi2->pads; + struct v4l2_subdev *sd =3D &csi2->sd; + int ret; + + ret =3D dw_mipi_csi2rx_register_notifier(csi2); + if (ret) + goto err; + + v4l2_subdev_init(sd, &dw_mipi_csi2rx_ops); + sd->dev =3D csi2->dev; + sd->entity.ops =3D &dw_mipi_csi2rx_media_ops; + sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; + sd->internal_ops =3D &dw_mipi_csi2rx_internal_ops; + snprintf(sd->name, sizeof(sd->name), "dw-mipi-csi2rx %s", + dev_name(csi2->dev)); + + pads[DW_MIPI_CSI2RX_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK | + MEDIA_PAD_FL_MUST_CONNECT; + pads[DW_MIPI_CSI2RX_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + ret =3D media_entity_pads_init(&sd->entity, DW_MIPI_CSI2RX_PAD_MAX, pads); + if (ret) + goto err_notifier_unregister; + + ret =3D v4l2_subdev_init_finalize(sd); + if (ret) + goto err_entity_cleanup; + + ret =3D v4l2_async_register_subdev(sd); + if (ret) { + dev_err(sd->dev, "failed to register CSI-2 subdev\n"); + goto err_subdev_cleanup; + } + + return 0; + +err_subdev_cleanup: + v4l2_subdev_cleanup(sd); +err_entity_cleanup: + media_entity_cleanup(&sd->entity); +err_notifier_unregister: + v4l2_async_nf_unregister(&csi2->notifier); + v4l2_async_nf_cleanup(&csi2->notifier); +err: + return ret; +} + +static void dw_mipi_csi2rx_unregister(struct dw_mipi_csi2rx_device *csi2) +{ + struct v4l2_subdev *sd =3D &csi2->sd; + + v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); + media_entity_cleanup(&sd->entity); + v4l2_async_nf_unregister(&csi2->notifier); + v4l2_async_nf_cleanup(&csi2->notifier); +} + +static const struct of_device_id dw_mipi_csi2rx_of_match[] =3D { + { + .compatible =3D "rockchip,rk3568-mipi-csi2", + }, + {} +}; +MODULE_DEVICE_TABLE(of, dw_mipi_csi2rx_of_match); + +static int dw_mipi_csi2rx_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dw_mipi_csi2rx_device *csi2; + int ret; + + csi2 =3D devm_kzalloc(dev, sizeof(*csi2), GFP_KERNEL); + if (!csi2) + return -ENOMEM; + csi2->dev =3D dev; + dev_set_drvdata(dev, csi2); + + csi2->base_addr =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(csi2->base_addr)) + return PTR_ERR(csi2->base_addr); + + ret =3D devm_clk_bulk_get_all(dev, &csi2->clks); + if (ret !=3D DW_MIPI_CSI2RX_CLKS_MAX) + return dev_err_probe(dev, -ENODEV, "failed to get clocks\n"); + csi2->clks_num =3D ret; + + csi2->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(csi2->phy)) + return dev_err_probe(dev, PTR_ERR(csi2->phy), + "failed to get MIPI CSI-2 PHY\n"); + + csi2->reset =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(csi2->reset)) + return dev_err_probe(dev, PTR_ERR(csi2->reset), + "failed to get reset\n"); + + csi2->formats =3D formats; + csi2->formats_num =3D ARRAY_SIZE(formats); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to enable pm runtime\n"); + + ret =3D phy_init(csi2->phy); + if (ret) + return dev_err_probe(dev, ret, + "failed to initialize MIPI CSI-2 PHY\n"); + + ret =3D dw_mipi_csi2rx_register(csi2); + if (ret) + goto err_phy_exit; + + return 0; + +err_phy_exit: + phy_exit(csi2->phy); + + return ret; +} + +static void dw_mipi_csi2rx_remove(struct platform_device *pdev) +{ + struct dw_mipi_csi2rx_device *csi2 =3D platform_get_drvdata(pdev); + + dw_mipi_csi2rx_unregister(csi2); + phy_exit(csi2->phy); +} + +static int dw_mipi_csi2rx_runtime_suspend(struct device *dev) +{ + struct dw_mipi_csi2rx_device *csi2 =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(csi2->clks_num, csi2->clks); + + return 0; +} + +static int dw_mipi_csi2rx_runtime_resume(struct device *dev) +{ + struct dw_mipi_csi2rx_device *csi2 =3D dev_get_drvdata(dev); + int ret; + + reset_control_assert(csi2->reset); + udelay(5); + reset_control_deassert(csi2->reset); + + ret =3D clk_bulk_prepare_enable(csi2->clks_num, csi2->clks); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + return 0; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(dw_mipi_csi2rx_pm_ops, + dw_mipi_csi2rx_runtime_suspend, + dw_mipi_csi2rx_runtime_resume, NULL); + +static struct platform_driver dw_mipi_csi2rx_drv =3D { + .driver =3D { + .name =3D "dw-mipi-csi2rx", + .of_match_table =3D dw_mipi_csi2rx_of_match, + .pm =3D pm_ptr(&dw_mipi_csi2rx_pm_ops), + }, + .probe =3D dw_mipi_csi2rx_probe, + .remove =3D dw_mipi_csi2rx_remove, +}; +module_platform_driver(dw_mipi_csi2rx_drv); + +MODULE_DESCRIPTION("Synopsys DesignWare MIPI CSI-2 Receiver platform drive= r"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Mon Feb 9 01:47:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25C7F42316D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-rockchip-mipi-receiver-v8-3-bd1cf5cb9588@collabora.com> References: <20251114-rockchip-mipi-receiver-v8-0-bd1cf5cb9588@collabora.com> In-Reply-To: <20251114-rockchip-mipi-receiver-v8-0-bd1cf5cb9588@collabora.com> To: Michael Riesch , Chaoyi Chen , Kever Yang , Frank Li , Mehdi Djait , Bryan O'Donoghue , Laurent Pinchart , Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Nicolas Dufresne , Collabora Kernel Team , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768911749; l=786; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=4/e4J7LessS5jdywMTVpeb4iDs9BMTFRupZRi4shvqg=; b=vM+9GvcUuupfbEtXCVYeCqoIhDdyKGXeBgK5EHF4Y7GG0wfQPK5IhDW3ee+Q8DGNb9+HqRDbd cXR5vbU9VxTCsLddpvbjSWg4A95nbSX+dQKQNM2sHkwQtLb5lkuN4Pw X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Synopsys DesignWare MIPI CSI-2 Receiver is integrated into recent Rockchip SoCs, such as the RK3568 and the RK3588. Enable the driver for it in the default configuration. Signed-off-by: Michael Riesch --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 45288ec9eaf7..58bda738819a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -873,6 +873,7 @@ CONFIG_SDR_PLATFORM_DRIVERS=3Dy CONFIG_V4L_MEM2MEM_DRIVERS=3Dy CONFIG_VIDEO_AMPHION_VPU=3Dm CONFIG_VIDEO_CADENCE_CSI2RX=3Dm +CONFIG_VIDEO_DW_MIPI_CSI2RX=3Dm CONFIG_VIDEO_MEDIATEK_JPEG=3Dm CONFIG_VIDEO_MEDIATEK_VCODEC=3Dm CONFIG_VIDEO_WAVE_VPU=3Dm --=20 2.39.5