From nobody Tue Feb 10 00:00:33 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2F2D33ADB7; Fri, 14 Nov 2025 16:54:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763139291; cv=pass; b=HCY9VJK2RZDO8CjLrvxzVD+yVgIoEo4ymy8bulnk0sk/AUQtCTTUXUBkT/LZLfVXKi80Agp/+WrCu+2jI1kf3xjM8135e6YOXZE6+IlwfXNyQuGeVqLbILhtO1SI36FJHe4w/z2c3gAFu+tiu73s29VcMPF8ssd0cpMEkXjRQbI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763139291; c=relaxed/simple; bh=H4ZhbC3gBtzfywWyAW8iuSFKyQzDsTFOmJ4qSfXuic4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qSomPCW0Nuca0H9fwvULCU0rbgbisP7Zemwfprz8K5ZHlLjwrSYSg9ZxNtFtwYlOec9IsvzpXjTxHrDDl8W9nS8etacnrd7OlaxdUvEsXiNYovSfBBR442M4NfZrhoeWbrD8MUUTC3PkR3nrC198UcwuXGBO8KFdAHOifUz9MhM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=Hj7lZ+Tm; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="Hj7lZ+Tm" ARC-Seal: i=1; a=rsa-sha256; t=1763139276; cv=none; d=zohomail.com; s=zohoarc; b=ZigYjCfDM6h5xQfXG+EzUQvjuSI5tBwGuNRs+6/3xrllqLcVbB6AVWXAd6as2JNo+Ljcg2h5FwY4UFjnB9yLtU+CE11hSPJg6xAbGXUwZICgmXC5pO6DXAMQJ/g4jDFG0IzySSK7lh4xbi/b1Ln9TZQV3FF89ygHWhDqcAsscqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1763139276; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=slpXXrUFzI9UcxqwpKnOSQb/CTXf+9m4NyR1Ck9WvZI=; b=XAM/WfvFmBxZC5jiqFiJDTqm9407QH1QM/TssXr6gKRc1P4LhYtxb0O9zjyEceQB6WprHiIOWDx/C7FkpPuEJ/3p76nV0VRJ3bCCE5m9hzN9FUy81YenhSEgNvP1laZZA6jatrxEfHtPy+mzeOzd1ZtSjUxLrbW2YXJUmXnaJc4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1763139276; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=slpXXrUFzI9UcxqwpKnOSQb/CTXf+9m4NyR1Ck9WvZI=; b=Hj7lZ+TmRxae/llDob4p/X+ZnWjRWFJumSSSpwNURAiIkTZZaNmAOyAkCmVENXzT AiUwrPMcCL4u+h1TUEl1suigT7vzL69lJi/glT6UqOBQknG6u030NtEdiCxYi9qubi+ E9Hww4VzfKlc1oK07G1EZNJnWhZVDnsEid4iKOPs= Received: by mx.zohomail.com with SMTPS id 1763139274999909.8349499369342; Fri, 14 Nov 2025 08:54:34 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 14 Nov 2025 17:54:02 +0100 Subject: [PATCH 08/13] soc: mediatek: mtk-dvfsrc: Add support for DVFSRCv4 and MT8196 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-mt8196-dvfsrc-v1-8-b956d4631468@collabora.com> References: <20251114-mt8196-dvfsrc-v1-0-b956d4631468@collabora.com> In-Reply-To: <20251114-mt8196-dvfsrc-v1-0-b956d4631468@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Henry Chen , Georgi Djakov Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 From: AngeloGioacchino Del Regno Add support for the DVFSRC Version 4 by adding new functions for vcore/dram levels (in v4, called gears instead), and for readout of pre-programmed dvfsrc_opp entries, corresponding to each gear. In the probe function, for v4, the curr_opps is initialized from the get_hw_opps() function instead of platform data. In order to make use of the new DVFSRCv4 code, also add support for the MediaTek MT8196 SoC. Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-dvfsrc.c | 248 ++++++++++++++++++++++++++++++++++= +++- 1 file changed, 247 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-d= vfsrc.c index bf0e7b01d255..3a83fd4baf54 100644 --- a/drivers/soc/mediatek/mtk-dvfsrc.c +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -15,11 +15,17 @@ #include #include =20 +/* DVFSRC_BASIC_CONTROL */ +#define DVFSRC_V4_BASIC_CTRL_OPP_COUNT GENMASK(26, 20) + /* DVFSRC_LEVEL */ #define DVFSRC_V1_LEVEL_TARGET_LEVEL GENMASK(15, 0) #define DVFSRC_TGT_LEVEL_IDLE 0x00 #define DVFSRC_V1_LEVEL_CURRENT_LEVEL GENMASK(31, 16) =20 +#define DVFSRC_V4_LEVEL_TARGET_LEVEL GENMASK(15, 8) +#define DVFSRC_V4_LEVEL_TARGET_PRESENT BIT(16) + /* DVFSRC_SW_REQ, DVFSRC_SW_REQ2 */ #define DVFSRC_V1_SW_REQ2_DRAM_LEVEL GENMASK(1, 0) #define DVFSRC_V1_SW_REQ2_VCORE_LEVEL GENMASK(3, 2) @@ -27,9 +33,23 @@ #define DVFSRC_V2_SW_REQ_DRAM_LEVEL GENMASK(3, 0) #define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4) =20 +#define DVFSRC_V4_SW_REQ_EMI_LEVEL GENMASK(3, 0) +#define DVFSRC_V4_SW_REQ_DRAM_LEVEL GENMASK(15, 12) + /* DVFSRC_VCORE */ #define DVFSRC_V2_VCORE_REQ_VSCP_LEVEL GENMASK(14, 12) =20 +/* DVFSRC_TARGET_GEAR */ +#define DVFSRC_V4_GEAR_TARGET_DRAM GENMASK(7, 0) +#define DVFSRC_V4_GEAR_TARGET_VCORE GENMASK(15, 8) + +/* DVFSRC_GEAR_INFO */ +#define DVFSRC_V4_GEAR_INFO_REG_WIDTH 0x4 +#define DVFSRC_V4_GEAR_INFO_REG_LEVELS 64 +#define DVFSRC_V4_GEAR_INFO_VCORE GENMASK(3, 0) +#define DVFSRC_V4_GEAR_INFO_EMI GENMASK(7, 4) +#define DVFSRC_V4_GEAR_INFO_DRAM GENMASK(15, 12) + #define DVFSRC_POLL_TIMEOUT_US 1000 #define STARTUP_TIME_US 1 =20 @@ -52,6 +72,7 @@ struct dvfsrc_bw_constraints { struct dvfsrc_opp { u32 vcore_opp; u32 dram_opp; + u32 emi_opp; }; =20 struct dvfsrc_opp_desc { @@ -72,6 +93,7 @@ struct mtk_dvfsrc { =20 struct dvfsrc_soc_data { const int *regs; + const u8 *bw_units; const bool has_emi_ddr; const struct dvfsrc_opp_desc *opps_desc; u32 (*calc_dram_bw)(struct mtk_dvfsrc *dvfsrc, int type, u64 bw); @@ -79,6 +101,8 @@ struct dvfsrc_soc_data { u32 (*get_current_level)(struct mtk_dvfsrc *dvfsrc); u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc); u32 (*get_vscp_level)(struct mtk_dvfsrc *dvfsrc); + u32 (*get_opp_count)(struct mtk_dvfsrc *dvfsrc); + int (*get_hw_opps)(struct mtk_dvfsrc *dvfsrc); void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); void (*set_dram_hrt_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); @@ -101,6 +125,7 @@ static void dvfsrc_writel(struct mtk_dvfsrc *dvfs, u32 = offset, u32 val) } =20 enum dvfsrc_regs { + DVFSRC_BASIC_CONTROL, DVFSRC_SW_REQ, DVFSRC_SW_REQ2, DVFSRC_LEVEL, @@ -110,6 +135,9 @@ enum dvfsrc_regs { DVFSRC_SW_HRT_BW, DVFSRC_SW_EMI_BW, DVFSRC_VCORE, + DVFSRC_TARGET_GEAR, + DVFSRC_GEAR_INFO_L, + DVFSRC_GEAR_INFO_H, DVFSRC_REGS_MAX, }; =20 @@ -130,6 +158,22 @@ static const int dvfsrc_mt8195_regs[] =3D { [DVFSRC_TARGET_LEVEL] =3D 0xd48, }; =20 +static const int dvfsrc_mt8196_regs[] =3D { + [DVFSRC_BASIC_CONTROL] =3D 0x0, + [DVFSRC_SW_REQ] =3D 0x18, + [DVFSRC_VCORE] =3D 0x80, + [DVFSRC_GEAR_INFO_L] =3D 0xfc, + [DVFSRC_SW_BW] =3D 0x1e8, + [DVFSRC_SW_PEAK_BW] =3D 0x1f4, + [DVFSRC_SW_HRT_BW] =3D 0x20c, + [DVFSRC_LEVEL] =3D 0x5f0, + [DVFSRC_TARGET_LEVEL] =3D 0x5f0, + [DVFSRC_SW_REQ2] =3D 0x604, + [DVFSRC_SW_EMI_BW] =3D 0x60c, + [DVFSRC_TARGET_GEAR] =3D 0x6ac, + [DVFSRC_GEAR_INFO_H] =3D 0x6b0, +}; + static const struct dvfsrc_opp *dvfsrc_get_current_opp(struct mtk_dvfsrc *= dvfsrc) { u32 level =3D dvfsrc->dvd->get_current_level(dvfsrc); @@ -137,6 +181,20 @@ static const struct dvfsrc_opp *dvfsrc_get_current_opp= (struct mtk_dvfsrc *dvfsrc return &dvfsrc->curr_opps->opps[level]; } =20 +static u32 dvfsrc_get_current_target_vcore_gear(struct mtk_dvfsrc *dvfsrc) +{ + u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_TARGET_GEAR); + + return FIELD_GET(DVFSRC_V4_GEAR_TARGET_VCORE, val); +} + +static u32 dvfsrc_get_current_target_dram_gear(struct mtk_dvfsrc *dvfsrc) +{ + u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_TARGET_GEAR); + + return FIELD_GET(DVFSRC_V4_GEAR_TARGET_DRAM, val); +} + static bool dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc) { if (!dvfsrc->dvd->get_target_level) @@ -193,6 +251,24 @@ static int dvfsrc_wait_for_opp_level_v2(struct mtk_dvf= src *dvfsrc, u32 level) return 0; } =20 +static int dvfsrc_wait_for_vcore_level_v4(struct mtk_dvfsrc *dvfsrc, u32 l= evel) +{ + u32 val; + + return readx_poll_timeout_atomic(dvfsrc_get_current_target_vcore_gear, + dvfsrc, val, val >=3D level, + STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US); +} + +static int dvfsrc_wait_for_opp_level_v4(struct mtk_dvfsrc *dvfsrc, u32 lev= el) +{ + u32 val; + + return readx_poll_timeout_atomic(dvfsrc_get_current_target_dram_gear, + dvfsrc, val, val >=3D level, + STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US); +} + static u32 dvfsrc_get_target_level_v1(struct mtk_dvfsrc *dvfsrc) { u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_LEVEL); @@ -226,6 +302,27 @@ static u32 dvfsrc_get_current_level_v2(struct mtk_dvfs= rc *dvfsrc) return 0; } =20 +static u32 dvfsrc_get_target_level_v4(struct mtk_dvfsrc *dvfsrc) +{ + u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_TARGET_LEVEL); + + if (val & DVFSRC_V4_LEVEL_TARGET_PRESENT) + return FIELD_GET(DVFSRC_V4_LEVEL_TARGET_LEVEL, val) + 1; + return 0; +} + +static u32 dvfsrc_get_current_level_v4(struct mtk_dvfsrc *dvfsrc) +{ + u32 level =3D dvfsrc_readl(dvfsrc, DVFSRC_LEVEL) + 1; + + /* Valid levels */ + if (level < dvfsrc->curr_opps->num_opp) + return dvfsrc->curr_opps->num_opp - level; + + /* Zero for level 0 or invalid level */ + return 0; +} + static u32 dvfsrc_get_vcore_level_v1(struct mtk_dvfsrc *dvfsrc) { u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ2); @@ -277,11 +374,30 @@ static void dvfsrc_set_vscp_level_v2(struct mtk_dvfsr= c *dvfsrc, u32 level) dvfsrc_writel(dvfsrc, DVFSRC_VCORE, val); } =20 +static u32 dvfsrc_get_opp_count_v4(struct mtk_dvfsrc *dvfsrc) +{ + u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_BASIC_CONTROL); + + return FIELD_GET(DVFSRC_V4_BASIC_CTRL_OPP_COUNT, val) + 1; +} + static u32 dvfsrc_calc_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, int type, u64= bw) { return (u32)div_u64(bw, 100 * 1000); } =20 +static u32 dvfsrc_calc_dram_bw_v4(struct mtk_dvfsrc *dvfsrc, int type, u64= bw) +{ + u8 bw_unit =3D dvfsrc->dvd->bw_units[type]; + u64 bw_mbps; + + if (type < DVFSRC_BW_AVG || type >=3D DVFSRC_BW_MAX) + return 0; + + bw_mbps =3D div_u64(bw, 1000); + return (u32)div_u64((bw_mbps + bw_unit - 1), bw_unit); +} + static void __dvfsrc_set_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, u32 reg, int type, u16 max_bw, u16 min_bw, u64 bw) { @@ -333,6 +449,100 @@ static void dvfsrc_set_opp_level_v1(struct mtk_dvfsrc= *dvfsrc, u32 level) dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ, val); } =20 +static u32 dvfsrc_get_opp_gear(struct mtk_dvfsrc *dvfsrc, u8 level) +{ + u32 reg_ofst, val; + u8 idx; + + /* Calculate register offset and index for requested gear */ + if (level < DVFSRC_V4_GEAR_INFO_REG_LEVELS) { + reg_ofst =3D dvfsrc->dvd->regs[DVFSRC_GEAR_INFO_L]; + idx =3D level; + } else { + reg_ofst =3D dvfsrc->dvd->regs[DVFSRC_GEAR_INFO_H]; + idx =3D level - DVFSRC_V4_GEAR_INFO_REG_LEVELS; + } + reg_ofst +=3D DVFSRC_V4_GEAR_INFO_REG_WIDTH * (level / 2); + + /* Read the corresponding gear register */ + val =3D readl(dvfsrc->regs + reg_ofst); + + /* Each register contains two sets of data, 16 bits per gear */ + val >>=3D 16 * (idx % 2); + + return val; +} + +static int dvfsrc_get_hw_opps_v4(struct mtk_dvfsrc *dvfsrc) +{ + struct dvfsrc_opp *dvfsrc_opps; + struct dvfsrc_opp_desc *desc; + u32 num_opps, gear_info; + u8 num_vcore, num_dram; + u8 num_emi; + int i; + + num_opps =3D dvfsrc_get_opp_count_v4(dvfsrc); + if (num_opps =3D=3D 0) { + dev_err(dvfsrc->dev, "No OPPs programmed in DVFSRC MCU.\n"); + return -EINVAL; + } + + /* + * The first 16 bits set in the gear info table says how many OPPs + * and how many vcore, dram and emi table entries are available. + */ + gear_info =3D dvfsrc_readl(dvfsrc, DVFSRC_GEAR_INFO_L); + if (gear_info =3D=3D 0) { + dev_err(dvfsrc->dev, "No gear info in DVFSRC MCU.\n"); + return -EINVAL; + } + + num_vcore =3D FIELD_GET(DVFSRC_V4_GEAR_INFO_VCORE, gear_info) + 1; + num_dram =3D FIELD_GET(DVFSRC_V4_GEAR_INFO_DRAM, gear_info) + 1; + num_emi =3D FIELD_GET(DVFSRC_V4_GEAR_INFO_EMI, gear_info) + 1; + dev_info(dvfsrc->dev, + "Discovered %u gears and %u vcore, %u dram, %u emi table entries.\n", + num_opps, num_vcore, num_dram, num_emi); + + /* Allocate everything now as anything else after that cannot fail */ + desc =3D devm_kzalloc(dvfsrc->dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + dvfsrc_opps =3D devm_kcalloc(dvfsrc->dev, num_opps + 1, + sizeof(*dvfsrc_opps), GFP_KERNEL); + if (!dvfsrc_opps) + return -ENOMEM; + + /* Read the OPP table gear indices */ + for (i =3D 0; i <=3D num_opps; i++) { + gear_info =3D dvfsrc_get_opp_gear(dvfsrc, num_opps - i); + dvfsrc_opps[i].vcore_opp =3D FIELD_GET(DVFSRC_V4_GEAR_INFO_VCORE, gear_i= nfo); + dvfsrc_opps[i].dram_opp =3D FIELD_GET(DVFSRC_V4_GEAR_INFO_DRAM, gear_inf= o); + dvfsrc_opps[i].emi_opp =3D FIELD_GET(DVFSRC_V4_GEAR_INFO_EMI, gear_info); + }; + desc->num_opp =3D num_opps + 1; + desc->opps =3D dvfsrc_opps; + + /* Assign to main structure now that everything is done! */ + dvfsrc->curr_opps =3D desc; + + return 0; +} + +static void dvfsrc_set_dram_level_v4(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + u32 val =3D dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ); + + val &=3D ~DVFSRC_V4_SW_REQ_DRAM_LEVEL; + val |=3D FIELD_PREP(DVFSRC_V4_SW_REQ_DRAM_LEVEL, level); + + dev_dbg(dvfsrc->dev, "%s level=3D%u\n", __func__, level); + + dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ, val); +} + int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data) { struct mtk_dvfsrc *dvfsrc =3D dev_get_drvdata(dev); @@ -448,7 +658,14 @@ static int mtk_dvfsrc_probe(struct platform_device *pd= ev) dvfsrc->dram_type =3D ares.a1; dev_dbg(&pdev->dev, "DRAM Type: %d\n", dvfsrc->dram_type); =20 - dvfsrc->curr_opps =3D &dvfsrc->dvd->opps_desc[dvfsrc->dram_type]; + /* Newer versions of the DVFSRC MCU have pre-programmed gear tables */ + if (dvfsrc->dvd->get_hw_opps) { + ret =3D dvfsrc->dvd->get_hw_opps(dvfsrc); + if (ret) + return ret; + } else { + dvfsrc->curr_opps =3D &dvfsrc->dvd->opps_desc[dvfsrc->dram_type]; + } platform_set_drvdata(pdev, dvfsrc); =20 ret =3D devm_of_platform_populate(&pdev->dev); @@ -576,10 +793,39 @@ static const struct dvfsrc_soc_data mt8195_data =3D { .bw_constraints =3D &dvfsrc_bw_constr_v2, }; =20 +static const u8 mt8196_bw_units[] =3D { + [DVFSRC_BW_AVG] =3D 64, + [DVFSRC_BW_PEAK] =3D 64, + [DVFSRC_BW_HRT] =3D 30, +}; + +static const struct dvfsrc_soc_data mt8196_data =3D { + .regs =3D dvfsrc_mt8196_regs, + .bw_units =3D mt8196_bw_units, + .has_emi_ddr =3D true, + .get_target_level =3D dvfsrc_get_target_level_v4, + .get_current_level =3D dvfsrc_get_current_level_v4, + .get_vcore_level =3D dvfsrc_get_vcore_level_v2, + .get_vscp_level =3D dvfsrc_get_vscp_level_v2, + .get_opp_count =3D dvfsrc_get_opp_count_v4, + .get_hw_opps =3D dvfsrc_get_hw_opps_v4, + .calc_dram_bw =3D dvfsrc_calc_dram_bw_v4, + .set_dram_bw =3D dvfsrc_set_dram_bw_v1, + .set_dram_peak_bw =3D dvfsrc_set_dram_peak_bw_v1, + .set_dram_hrt_bw =3D dvfsrc_set_dram_hrt_bw_v1, + .set_opp_level =3D dvfsrc_set_dram_level_v4, + .set_vcore_level =3D dvfsrc_set_vcore_level_v2, + .set_vscp_level =3D dvfsrc_set_vscp_level_v2, + .wait_for_opp_level =3D dvfsrc_wait_for_opp_level_v4, + .wait_for_vcore_level =3D dvfsrc_wait_for_vcore_level_v4, + .bw_constraints =3D &dvfsrc_bw_constr_v1, +}; + static const struct of_device_id mtk_dvfsrc_of_match[] =3D { { .compatible =3D "mediatek,mt6893-dvfsrc", .data =3D &mt6893_data }, { .compatible =3D "mediatek,mt8183-dvfsrc", .data =3D &mt8183_data }, { .compatible =3D "mediatek,mt8195-dvfsrc", .data =3D &mt8195_data }, + { .compatible =3D "mediatek,mt8196-dvfsrc", .data =3D &mt8196_data }, { /* sentinel */ } }; =20 --=20 2.51.2