From nobody Mon Feb 9 07:05:30 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA8F6337113 for ; Thu, 13 Nov 2025 23:31:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763076717; cv=none; b=PE3diBFP1jIzyBGEMMgfgoOe8788+F2Vf+XpVsbeCWbdStj0tP2TttSH3MGnh8yO0VkHplWepMo1L/3Qe+pmzh8Kz+27jBKEwlKY012FnDFSOrbRkiluu3Cj94i9IOVu0tV2Fd6gC92Jh94ortom2mQHHmrmLZZAFq5oHU/wI8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763076717; c=relaxed/simple; bh=yV2Eh2BxPAIz/kC+YJkyf4flz+m5iCj31pjkURNFVlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=esQivheAPztY3qKCVvdNE2EKMVUUJGFwlHZMUAOHcDQc4kfT7q6dPsrmS9mxqJ7Lem6O71WQKmTGjqWJu1ii6g1smw1IZK7Y1rV4/neMu6VTD5CbYghqX2oXC6FulCJ5v8PpPh96WGbwHs3CfRjEzfW4EoYOr0+2fsLM82EOORw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=CZtm2hfu; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=fEuG5ReZ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="CZtm2hfu"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="fEuG5ReZ" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ADMaoKi1423690 for ; Thu, 13 Nov 2025 23:31:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= x4iw0I7W3mqn5fxj/Qx1BIFB2Igjy2lSGReQd24IBms=; b=CZtm2hfu0Ep2VauJ QiE4vlFULP/FUUdZ0PPwzJ3w5WgYVpBIX4nekIVXnO7ar+zL9K3c3ddh5KiVNf/6 NnJfejMILoRasJ6T+F8Kk5V94OdqSwNSE6493eu3NiruaIS0bIxw1SIO8ZRbGwxT Xo/a6naEvxxNQsUNg9sq9idPeghUcmN08+wOUsKRo5i52Ktrvwb4B/cmO+DUosfC b5WTNoPulcVXz+bZzHwaYW3UZ1GZgVWuVt0UhoKD049vuAjpviSIbtzUbjqpL9EH 5sXqQ/5XI+OsueA8/PlR5n9vsBmvqa9HKixMB9F8q+/FiNByKzBrEhJpXZEMeGo+ 1UJ0zA== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4adr9g046d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 13 Nov 2025 23:31:54 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-7b8973c4608so3538232b3a.3 for ; Thu, 13 Nov 2025 15:31:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763076714; x=1763681514; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=x4iw0I7W3mqn5fxj/Qx1BIFB2Igjy2lSGReQd24IBms=; b=fEuG5ReZlqSnd+EJsad3jiV6JDkWMJhS0XhHR/40bB7szimqPCMDSKvqWBzXJRyIl5 OEiD8EVPmxsxJo02h4OQ+g5c9VwTrKDo1l5mIX2/tZBV3ty+hV2ohYKrUoYA56/VZ7Ap 72fhCy1F14Nmk4SRpWiAPhG1TGz0XTvRRcDsyk5tBv54BVr0LWZsoyvh7coTznQIAhSL lrT67RCdhlvkGwFPftF9ihY0cl8rG46BDjv0xewAzjDfeClARH05BM+EwR1pDHXgEk8+ 0attWpbjCYv63j/KDArW3XYZAAPwZfGrdMpv0Yj6vw736azOZTsne7OsV5f/v4XIVX82 vw2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763076714; x=1763681514; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=x4iw0I7W3mqn5fxj/Qx1BIFB2Igjy2lSGReQd24IBms=; b=jBx2LNfzsG2nw3msOB5uppHrZnYuaizYCi8GWR+5gkuoIv2W+EdMmn8bUcX9m5N3FM krcMOl21Oh6VG6XyASsVwXnVibRfhxToR+tX/jN6WVk70lgiRZ52RenH6imP0rhOa8ML YwEmlz92QFYv8rOOXhxcAK5fCz+Xxxgt0tQHta1l0YIgqLoJbRkDPMYYtuCuF+uolI7a 5TR0R1ygnNJcD0ZLcCFLgbqIByGsSHkf71Aw6Su1mraLJHf6kkKxbM4J8DiWHm3c0oBv x0xEPq7NeT+Cb6kY8ps19KJKvrzBB1QlxS8JO6efIuaBes/OKyajZHSzrJBbTkuhwybv zVKQ== X-Forwarded-Encrypted: i=1; AJvYcCWrBc6Bh/y9VwyYS6teYbn3kC/59+TLigbz2uTcXJWRgldXmrzPfVxeW4t5vrnNc0FiMDQo4qF+GWGco1c=@vger.kernel.org X-Gm-Message-State: AOJu0Ywp+Qz/u+T4f2Z2hoYIw/TptVhWsmzlNxTOQz3UWbSegEuxmwqd ZJQmDPM+6svHTO0kgbALqLKcz9wSdoL5OItVg+bsBfiW50gzvjl4c0bXPimplSCqmHp6kk+ElMb LXO5m81d0lop0kjP+y1LID41fKQ0elWmIRyz1xSvcwU8AjxxA85fkCuY3mW9EXDY6+mA= X-Gm-Gg: ASbGncuu6+3stEX7s344acmbpBEjTbN8Ere7wGFyvEdDQ6rpsRR5DXAhQ+7rIvnbz7n y/ouG31d9fiNsr8m5b4M5DiW8YF6xd65d5KnplTdUXTOgSVEVgY6q8vt6X+VM4ivqH+BhD4718z gjcTEUilAPhqNg61Ka8Lxf/xtA7FOpSZJtrrJUgoEUZRwP//hZtm+bjLXOTK9RHp61N7cavbmf3 ccz+Mj4PXOj5qmEKLIfXvAitOnS8SqDGPKYK4cWxyiYznxE7b8P7LJk243qj3FX9cDgLvjl88Sy tJxl+rkiBEOi2UrhlejXFvx4DMxXFhtBQK6/G1Hvcm3XSbUFdk6F48hAzQSiQUK34wYQiioO6j5 MWusc7K34ZoR6xcc4Z5BDy6g= X-Received: by 2002:a05:6a20:244f:b0:342:3b8a:f33e with SMTP id adf61e73a8af0-35ba1d8bff2mr1514843637.39.1763076713657; Thu, 13 Nov 2025 15:31:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IFmwgXSLz02FWNkJ1X/On5Tf8zKgGmJbzhu8REJ1vhWtxFUkvZ01iBmyvIGhB3FIDzn2Lj7cA== X-Received: by 2002:a05:6a20:244f:b0:342:3b8a:f33e with SMTP id adf61e73a8af0-35ba1d8bff2mr1514797637.39.1763076713120; Thu, 13 Nov 2025 15:31:53 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc36ed72cd1sm3049486a12.11.2025.11.13.15.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 15:31:52 -0800 (PST) From: Akhil P Oommen Date: Fri, 14 Nov 2025 04:59:14 +0530 Subject: [PATCH v3 17/20] drm/msm/a8xx: Add support for Adreno X2-85 GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-kaana-gpu-support-v3-17-92300c7ec8ff@oss.qualcomm.com> References: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> In-Reply-To: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763076574; l=8789; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=yV2Eh2BxPAIz/kC+YJkyf4flz+m5iCj31pjkURNFVlQ=; b=qqqgIhwm6BzPVKPxN+RP38o5Z6wGhy7cKXrIloZyDBKSZptL+ZhI5UIdyc+J/vBHV4tptn3TO g/nijUlTXswByKZ+/Z6beynypl62ajNE04ciu6wgFHo37u2WaeYLO+G X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Authority-Analysis: v=2.4 cv=L+AQguT8 c=1 sm=1 tr=0 ts=69166a6a cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=vUcRZ7zKRWKu6Gx-IyYA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEzMDE4NSBTYWx0ZWRfX04MgcVMyGm26 MCSXQd0/fw1yK9b7p8IIB+41KfC8K29yAnAS+W7jLG8s1zIRLIZJN8R42l+gpIIQjjFeWuYGzdP tTSYAsfQgYn2s8fFQpgYlCjdLEUCNEOyExUaIO1/tKTPxkLsX2LRbtpnoPVvMtAR+C+DgnTbDr8 jkmRSa+nGLX22sL89eOnHINz13KPK3FDk4EQNN357sLDKUlfdN9Jy8jrWhkqgDGb/Sf1BTBUGzI OQImH45cm+XZfQluxqlTaf2+dPy2eIKGo68NwuKYLy7c+YDoj3n3MlBBeipJEVsEgk7Zumoqnjv pzucWmOBLtV8BMhoZdZ0FHUOWcDRpgJvVj1mN0hMa4fPsvCT4jCGb8uFri3hw1aDN+pol63X/RB YABWVRRZikfYnraGYPELI+KFGu8QWA== X-Proofpoint-ORIG-GUID: BaFRpd0pa4cjg1baKo7JApQZpbPdLNL9 X-Proofpoint-GUID: BaFRpd0pa4cjg1baKo7JApQZpbPdLNL9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-13_06,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511130185 Adreno X2-85 GPU is found in the next generation of Qualcomm's compute series chipset called Snapdragon X2 Elite (a.k.a Glymur). It is based on the new A8x slice architecture and features up to 4 slices. Due to the wider 12 channel DDR support, there is higher DDR bandwidth available than previous generation to improve performance. Add a new entry in the catalog along with the necessary register configurations to enable support for it. Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 132 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 3 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++ 3 files changed, 140 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index f064ef6b8be1..abd573381b7e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1634,6 +1634,108 @@ static const struct adreno_info a7xx_gpus[] =3D { }; DECLARE_ADRENO_GPULIST(a7xx); =20 +static const struct adreno_reglist_pipe x285_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + /* Disable CS dead batch merge */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) }, + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { }, +}; + +static const u32 x285_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x0082c, 0x0000), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x000a), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; + +DECLARE_ADRENO_PROTECT(x285_protect, 64); + static const struct adreno_reglist_pipe a840_nonctxt_regs[] =3D { { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -1766,6 +1868,36 @@ static const struct adreno_reglist a840_gbif[] =3D { =20 static const struct adreno_info a8xx_gpus[] =3D { { + .chip_ids =3D ADRENO_CHIP_IDS(0x44070001), + .family =3D ADRENO_8XX_GEN2, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen80100_sqe.fw", + [ADRENO_FW_GMU] =3D "gen80100_gmu.bin", + }, + .gmem =3D 21 * SZ_1M, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .funcs =3D &a8xx_gpu_funcs, + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &x285_protect, + .nonctxt_reglist =3D x285_nonctxt_regs, + .gbif_cx =3D a840_gbif, + .max_slices =3D 4, + .gmu_chipid =3D 0x8010100, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 16 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 16500000, + }, + { /* sentinel */ }, + }, + }, + }, { .chip_ids =3D ADRENO_CHIP_IDS(0x44050a01), .family =3D ADRENO_8XX_GEN2, .fw =3D { diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 386ee1207622..5a320f5bde41 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -190,6 +190,9 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool sta= te) struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; u32 val; =20 + if (adreno_is_x285(adreno_gpu) && state) + gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 450e655f59a4..a44331dc0003 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -568,6 +568,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gp= u) return gpu->info->family >=3D ADRENO_8XX_GEN1; } =20 +static inline int adreno_is_x285(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44070001; +} + static inline int adreno_is_a840(struct adreno_gpu *gpu) { return gpu->info->chip_ids[0] =3D=3D 0x44050a01; --=20 2.51.0