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Thu, 13 Nov 2025 15:31:15 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc36ed72cd1sm3049486a12.11.2025.11.13.15.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 15:31:15 -0800 (PST) From: Akhil P Oommen Date: Fri, 14 Nov 2025 04:59:09 +0530 Subject: [PATCH v3 12/20] drm/msm/a6xx: Share dependency vote table with GMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-kaana-gpu-support-v3-12-92300c7ec8ff@oss.qualcomm.com> References: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> In-Reply-To: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Create this new vote table and implement the new HFI message which allows passing vote tables to send this data to GMU. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 54 +++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 53 +++++++++++++++++++++++++++++++= +++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 17 +++++++++++ 4 files changed, 125 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index f32e1aba146b..158c0cd2d92b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1590,6 +1590,57 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct devic= e *dev, u32 *votes, return 0; } =20 +static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes, + unsigned long *freqs, int freqs_count) +{ + const u16 *mx; + size_t count; + + mx =3D cmd_db_read_aux_data("mx.lvl", &count); + if (IS_ERR(mx)) + return PTR_ERR(mx); + /* + * The data comes back as an array of unsigned shorts so adjust the + * count accordingly + */ + count >>=3D 1; + if (!count) + return -EINVAL; + + /* Fix the vote for zero frequency */ + votes[0] =3D 0xffffffff; + + /* Construct a vote for rest of the corners */ + for (int i =3D 1; i < freqs_count; i++) { + unsigned int level =3D a6xx_gmu_get_arc_level(dev, freqs[i]); + u8 j, index =3D 0; + + /* Get the primary index that matches the arc level */ + for (j =3D 0; j < count; j++) { + if (mx[j] >=3D level) { + index =3D j; + break; + } + } + + if (j =3D=3D count) { + DRM_DEV_ERROR(dev, + "Mx Level %u not found in the RPMh list\n", + level); + DRM_DEV_ERROR(dev, "Available levels:\n"); + for (j =3D 0; j < count; j++) + DRM_DEV_ERROR(dev, " %u\n", mx[j]); + + return -EINVAL; + } + + /* Construct the vote */ + votes[i] =3D (0x3fff << 14) | (index << 8) | (0xff); + } + + return 0; +} + /* * The GMU votes with the RPMh for itself and on behalf of the GPU but we = need * to construct the list of votes on the CPU and send it over. Query the R= PMh @@ -1623,6 +1674,9 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *= gmu) ret |=3D a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl"); =20 + ret |=3D a6xx_gmu_rpmh_dep_votes_init(gmu->dev, gmu->dep_arc_votes, + gmu->gpu_freqs, gmu->nr_gpu_freqs); + /* Build the interconnect votes */ if (info->bcms && gmu->nr_gpu_bws > 1) ret |=3D a6xx_gmu_rpmh_bw_votes_init(adreno_gpu, info, gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index edf6c282cd76..2af074c8e8cf 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -97,6 +97,7 @@ struct a6xx_gmu { int nr_gpu_freqs; unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; u32 gx_arc_votes[GMU_MAX_GX_FREQS]; + u32 dep_arc_votes[GMU_MAX_GX_FREQS]; struct a6xx_hfi_acd_table acd_table; =20 int nr_gpu_bws; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.c index 550de6ad68ef..da113e5b535d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -23,6 +23,7 @@ static const char * const a6xx_hfi_msg_id[] =3D { HFI_MSG_ID(HFI_H2F_MSG_START), HFI_MSG_ID(HFI_H2F_FEATURE_CTRL), HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START), + HFI_MSG_ID(HFI_H2F_MSG_TABLE), HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE), HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER), }; @@ -255,11 +256,63 @@ static int a6xx_hfi_send_perf_table_v1(struct a6xx_gm= u *gmu) NULL, 0); } =20 +static int a8xx_hfi_send_perf_table(struct a6xx_gmu *gmu) +{ + unsigned int num_gx_votes =3D 3, num_cx_votes =3D 2; + struct a6xx_hfi_table_entry *entry; + struct a6xx_hfi_table *tbl; + int ret, i; + u32 size; + + size =3D sizeof(*tbl) + (2 * sizeof(tbl->entry[0])) + + (gmu->nr_gpu_freqs * num_gx_votes * sizeof(gmu->gx_arc_votes[0])) + + (gmu->nr_gmu_freqs * num_cx_votes * sizeof(gmu->cx_arc_votes[0])); + tbl =3D kzalloc(size, GFP_KERNEL); + tbl->type =3D HFI_TABLE_GPU_PERF; + + /* First fill GX votes */ + entry =3D &tbl->entry[0]; + entry->count =3D gmu->nr_gpu_freqs; + entry->stride =3D num_gx_votes; + + for (i =3D 0; i < gmu->nr_gpu_freqs; i++) { + unsigned int base =3D i * entry->stride; + + entry->data[base+0] =3D gmu->gx_arc_votes[i]; + entry->data[base+1] =3D gmu->dep_arc_votes[i]; + entry->data[base+2] =3D gmu->gpu_freqs[i] / 1000; + } + + /* Then fill CX votes */ + entry =3D (struct a6xx_hfi_table_entry *) + &tbl->entry[0].data[gmu->nr_gpu_freqs * num_gx_votes]; + + entry->count =3D gmu->nr_gmu_freqs; + entry->stride =3D num_cx_votes; + + for (i =3D 0; i < gmu->nr_gmu_freqs; i++) { + unsigned int base =3D i * entry->stride; + + entry->data[base] =3D gmu->cx_arc_votes[i]; + entry->data[base+1] =3D gmu->gmu_freqs[i] / 1000; + } + + ret =3D a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0); + + kfree(tbl); + return ret; +} + static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_hfi_msg_perf_table msg =3D { 0 }; int i; =20 + if (adreno_is_a8xx(adreno_gpu)) + return a8xx_hfi_send_perf_table(gmu); + msg.num_gpu_levels =3D gmu->nr_gpu_freqs; msg.num_gmu_levels =3D gmu->nr_gmu_freqs; =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.h index 653ef720e2da..6f9f74a0bc85 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -185,6 +185,23 @@ struct a6xx_hfi_msg_core_fw_start { u32 handle; }; =20 +#define HFI_H2F_MSG_TABLE 15 + +struct a6xx_hfi_table_entry { + u32 count; + u32 stride; + u32 data[]; +}; + +struct a6xx_hfi_table { + u32 header; + u32 version; + u32 type; +#define HFI_TABLE_BW_VOTE 0 +#define HFI_TABLE_GPU_PERF 1 + struct a6xx_hfi_table_entry entry[]; +}; + #define HFI_H2F_MSG_GX_BW_PERF_VOTE 30 =20 struct a6xx_hfi_gx_bw_perf_vote_cmd { --=20 2.51.0