From nobody Mon Feb 9 04:03:41 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D8F732D7FA for ; Thu, 13 Nov 2025 23:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763076667; cv=none; b=FupAlOWvgPeQZ57xmWDGcGtz/u1dGlKbw2E/l9XV8sXh01KbjneMomCrAGi9/FYujBht95nwcAXgKn9ST/2/+uqBpYQgqWwMDc4+ndOysVW6RUlAbYlVmgtOU8hA2BHSpIEwfALiDBbjXhZ7m7LTOTpS5dSYfiN5GKy3Y1WlGCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763076667; c=relaxed/simple; bh=LmTQ4+xDC9B28giqo/zBM4nUmBfK/nteJCrG82WwkZU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rHDFGkOfeK/OBlJ7gh4rxA9AxliXaE8p88DP/a+AmRoty1hJdMC9EYD0/vLAZixelaMPLgqfr0Tfr22XrpAQzTuEO3m81Y0TdVw8MmFvU37bYg+l7UHAPWlPl0WisaEHe5kI8Jmo8S30BePatOkr9XZOR/nPR5Q4bjacy7IKuPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mWnge/BI; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GFNlebxv; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mWnge/BI"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GFNlebxv" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ADMbPL51502022 for ; Thu, 13 Nov 2025 23:31:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= FLsirGP3CG3tM2mJ8jxgH5Xo99gAN80a30QteswCvs4=; b=mWnge/BINXTgpVop QmY3oETGJgsBKVvToy/EFLvftYXdGGwkd8srY+A3vcE1bbGGhStEL4ebDCZoSg0x sfz1JuHux0DaHFApyOo3ItUsToFgB71pim+czKNHdjXniSHiJoYX5p04c2gfky+B C6kTzQFzoF6vMmw73BXxkpSzDRBGvkYg0lTOq8Ujze2Rhy1nsWJg/iDlUh0/6h2o oqr38Frd7EgTgcOhPyw1PvECtC1ZS4wy6pX8nlf1mMZgLwU79uyO3umMLUC/STZ5 uWFj/hth6gIv/uXYzAD3reXZyqeSzTF2ThqbgwmKjaYEjbp5LKNA+IC0etkoLLsF SJ/oSw== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4adr9hr424-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 13 Nov 2025 23:31:03 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-bbcf3bd4c8fso1254627a12.0 for ; Thu, 13 Nov 2025 15:31:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763076662; x=1763681462; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FLsirGP3CG3tM2mJ8jxgH5Xo99gAN80a30QteswCvs4=; b=GFNlebxvSBDjvbmQy49oKytvuspBsQPCK93o0jCYzlgNZRcPZsa7tn5GZO4dT4eDZU C7a2J1KrqhQ2pR/vMNd8N0IsfkJgaC+4z6UdMrMS1PuEx2esOoP66KhzOiXhWxSRIYmR bWmkmQQS0eiesYwDtlZuN3DWDGTA/6ShvhDN8bsemqbdQMCBe+EAxzQo8gazE/+LcnJ6 feoj1y+A3bRHwtmgLLdrLfoZuvH1KsaQgj4arqHdHXoWtr7JhIP34PhbYjVYm6VoR6w3 29Cg8U8yGwCIMLfMtlLkTj22C2/tKnYiMaWqcr8TAZYwDR8Q6CnwDu8aeyeipbdZhGZp JgCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763076662; x=1763681462; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FLsirGP3CG3tM2mJ8jxgH5Xo99gAN80a30QteswCvs4=; b=Yje4i3KcD42GCzkHgUKNY9q4NTSf174e6Ukzs6Rq+UwYiHTW8J87Zgc/VqJnWL5fzE mBs6pVIaXWVR2Cjj6w1VK0nfHnxcWmnfhYP9tCPS35hIfDzvgKr67SyivXouAuJRpzMb 6DH4dTDSpO4pBnvl1xcMbS0zANMVnObuds0j184CbAH9Kyozd51tCjEMBU2+bhFy9grF C+ci8QvVzM2UwA7uSOBzXgC8qBM35Pz7c+N+wIncoP+SNisWswLCIv5tXtdO/YCCuf30 ugptEZ2Vpa7v1NgPFdXMFh9vyHBYj2fXI1xMIPcemSPpD7htk+uHJ9k+IRs4O5wgLpqH r9VA== X-Forwarded-Encrypted: i=1; AJvYcCVXBQnevs3fNydVqpvu5U6G0xC3wOwlZM6pOXxm2oldn/MRbt60dtxZX+UV7OJ7ZQ+eOGATEImyvmli9oA=@vger.kernel.org X-Gm-Message-State: AOJu0YwVtNWeV94Z+9ZV8h+euRdTWQ41BdTjk7nv++/uDxFleExojUhj B9oXuClmKQipfEfVPXuHsPSuvuACqM41k+EYpQ8XRSbd8rhDTB8jdQxflqvnyfBUHhmHGYljO5b fOM6bLDO3ASBvtCqGPRWZ7Ajb9/YQ6mvW8luY8APtw6iRNGhvPE6jA4DRHzoWHPixCM0= X-Gm-Gg: ASbGnctiifQ4nHN3XGL2cVkbbOQ2sENXbr21slCrF5M3mUS6y4yLAKyJW59w44vG9CD 1+fcw7fnINteH5oNYgb8Iya0zHk4XbZIhDDFP5t2vqjO8wAFOg6TW0Mhkx2C5p0BMU2O8CyYBeJ LQKoWfMZaSEoxU78zpQUsHJl0gTI3MXE6YbPmPhLSSgjDxpWVJ5u3HdAcqbtNgQ/AQwU8YQVoI5 h/G76scp8/3pqZJk1D/XnQ5wo0txZFsX6ucMvztCMYfHJcL7zbQku3ikvqfyELrduP3aJizLEzN NXXuiVtbbBaj2oMxFlCmJk0ThHWNijyqcWZTo02iq0SNjjCQ3qLmEjWVB0G8XwJEC/XjjCEwCIK KH1Btz3xxelRab2bD6+fQhak= X-Received: by 2002:a05:6a21:6d83:b0:2b9:5bdc:8e28 with SMTP id adf61e73a8af0-35a516a9ffbmr6950637637.15.1763076661713; Thu, 13 Nov 2025 15:31:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IHeOO6Mo5faga/S1m7glc5wMiLxTxA7e6gRSTm1a1Cl3AJPoE7UBwKpjy+sOUCIyO1b2xfgcQ== X-Received: by 2002:a05:6a21:6d83:b0:2b9:5bdc:8e28 with SMTP id adf61e73a8af0-35a516a9ffbmr6950577637.15.1763076660960; Thu, 13 Nov 2025 15:31:00 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc36ed72cd1sm3049486a12.11.2025.11.13.15.30.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 15:31:00 -0800 (PST) From: Akhil P Oommen Date: Fri, 14 Nov 2025 04:59:07 +0530 Subject: [PATCH v3 10/20] drm/msm/a8xx: Add support for A8x GMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-kaana-gpu-support-v3-10-92300c7ec8ff@oss.qualcomm.com> References: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> In-Reply-To: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763076574; l=18689; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=LmTQ4+xDC9B28giqo/zBM4nUmBfK/nteJCrG82WwkZU=; b=OtdVlDwjSXDIYKhWSNasxFR64vmFx69uYtZV7UL4mM4XKwVvZMQ6nMt+6w7zTEti5nyLYYR/K xkRnuOcv+b8BWZJwwVYgC+7nYNQL5kb6qGKzCfLZpHjst/5uXvkeV6x X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-GUID: TLI4Z271I5l35FHHyChZth1L_LCcH5RU X-Proofpoint-ORIG-GUID: TLI4Z271I5l35FHHyChZth1L_LCcH5RU X-Authority-Analysis: v=2.4 cv=N+Qk1m9B c=1 sm=1 tr=0 ts=69166a37 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=e5mUnYsNAAAA:8 a=EUspDBNiAAAA:8 a=BnPpZdVtioYmAKrWMJ8A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEzMDE4NSBTYWx0ZWRfXyDGEIvbJvPhf xJQHs9FaVrVHxhNEC6Y2t/GAGaw3GY3i0LP4V2afrsRLOpvIIOxXvQ/v47fOIi56ECoVOiOUqmJ QBKlvo0fQp3AACPejhueNgwPg3bPn/Gh85ZLgi8t7i9M1saq/w6GlPk979v5wRUFrMgoBaVPoxK /4rl51UrYh/MpHIFDFUQU99w4zIzlujgb6ugTgTLZaNfN5sdnDnsTE5SeEVKuO10F+PRmOKEy2n dVMXMnt7bJNCF6icNz7t3F1G0kiERhLefp9k/Sm1pkYPbARM7P9RfIKX0/yfymcTft4tMqM35qE rOcxsHk5PZCVf2/vpl6tvv0cHvnP/WApQaMcUBUAsQ+SnFTx0QjKsKxIy/iQ/n8FQIAQXwdY8A0 lQ6YPoCVek/frV7GjDMnC9ZlyJRCQQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-13_06,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511130185 A8x GMU configuration are very similar to A7x. Unfortunately, there are minor shuffling in the register offsets in the GMU CX register region. Apart from that, there is a new HFI message support to pass table like data. This patch adds support for perf table using this new HFI message. Apart from that, there is a minor rework in a6xx_gmu_rpmh_arc_votes_init() to simplify handling of MxG to MxA fallback along with the additional calculations for the new dependency vote. Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 77 +++++++++++++++++--= ---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 4 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++ drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 48 ++++++++++---- 4 files changed, 102 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 1495f874e30e..53461be14dc3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -224,14 +224,19 @@ unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) =20 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) { - u32 val; + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; int local =3D gmu->idle_level; + u32 val; =20 /* SPTP and IFPC both report as IFPC */ if (gmu->idle_level =3D=3D GMU_IDLE_STATE_SPTP) local =3D GMU_IDLE_STATE_IFPC; =20 - val =3D gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); + if (adreno_is_a8xx(adreno_gpu)) + val =3D gmu_read(gmu, REG_A8XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); + else + val =3D gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); =20 if (val =3D=3D local) { if (gmu->idle_level !=3D GMU_IDLE_STATE_IFPC || @@ -269,7 +274,9 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) /* Set the log wptr index * note: downstream saves the value in poweroff and restores it here */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(gmu, REG_A8XX_GMU_GENERAL_9, 0); + else if (adreno_is_a7xx(adreno_gpu)) gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); else gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); @@ -485,7 +492,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) * in the power down sequence not being fully executed. That in turn can * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. */ - if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); + else if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu))) gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); } @@ -493,10 +502,15 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *g= mu) /* Let the GMU know that we are about to go into slumber */ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; int ret; =20 /* Disable the power counter so the GMU isn't busy */ - gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); + else + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); =20 /* Disable SPTP_PC if the CPU is responsible for it */ if (gmu->idle_level < GMU_IDLE_STATE_SPTP) @@ -589,12 +603,17 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct platform_device *pdev =3D to_platform_device(gmu->dev); - void __iomem *pdcptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu= _pdc"); u32 seqmem0_drv0_reg =3D REG_A6XX_RSCC_SEQ_MEM_0_DRV0; void __iomem *seqptr =3D NULL; uint32_t pdc_address_offset; + void __iomem *pdcptr; bool pdc_in_aop =3D false; =20 + /* On A8x and above, RPMH/PDC configurations are entirely configured in A= OP */ + if (adreno_is_a8xx(adreno_gpu)) + return; + + pdcptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu_pdc"); if (IS_ERR(pdcptr)) return; =20 @@ -723,7 +742,7 @@ static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); =20 /* A7xx knows better by default! */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) return; =20 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); @@ -786,7 +805,9 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) u32 itcm_base =3D 0x00000000; u32 dtcm_base =3D 0x00040000; =20 - if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a650_family(adreno_gpu) || + adreno_is_a7xx(adreno_gpu) || + adreno_is_a8xx(adreno_gpu)) dtcm_base =3D 0x10004000; =20 if (gmu->legacy) { @@ -850,12 +871,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, un= signed int state) if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); + } else if (adreno_is_a8xx(adreno_gpu)) { + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); } =20 /* Turn on TCM (Tightly Coupled Memory) retention */ if (adreno_is_a7xx(adreno_gpu)) a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); - else + else if (!adreno_is_a8xx(adreno_gpu)) gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); =20 ret =3D a6xx_rpmh_start(gmu); @@ -880,7 +904,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, uns= igned int state) gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); =20 - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a8xx(adreno_gpu)) { + fence_range_upper =3D 0x32; + fence_range_lower =3D 0x8c0; + } else if (adreno_is_a7xx(adreno_gpu)) { fence_range_upper =3D 0x32; fence_range_lower =3D 0x8a0; } else { @@ -914,7 +941,12 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, uns= igned int state) chipid |=3D (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ } =20 - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a8xx(adreno_gpu)) { + gmu_write(gmu, REG_A8XX_GMU_GENERAL_10, chipid); + gmu_write(gmu, REG_A8XX_GMU_GENERAL_8, + (gmu->log.iova & GENMASK(31, 12)) | + ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); + } else if (adreno_is_a7xx(adreno_gpu)) { gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid); gmu_write(gmu, REG_A7XX_GMU_GENERAL_8, (gmu->log.iova & GENMASK(31, 12)) | @@ -977,7 +1009,7 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) u32 val, seqmem_off =3D 0; =20 /* The second spin of A7xx GPUs messed with some register offsets.. */ - if (adreno_is_a740_family(adreno_gpu)) + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) seqmem_off =3D 4; =20 /* Make sure there are no outstanding RPMh votes */ @@ -990,7 +1022,7 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, val, (val & 1), 100, 1000); =20 - if (!adreno_is_a740_family(adreno_gpu)) + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) return; =20 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, @@ -1018,7 +1050,10 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) * Turn off keep alive that might have been enabled by the hang * interrupt */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + else + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); =20 /* Flush all the queues */ a6xx_hfi_stop(gmu); @@ -1122,7 +1157,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) enable_irq(gmu->gmu_irq); =20 /* Check to see if we are doing a cold or warm boot */ - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { status =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D= 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; } else if (gmu->legacy) { @@ -1451,7 +1486,7 @@ static int a6xx_gmu_rpmh_bw_votes_init(struct adreno_= gpu *adreno_gpu, vote =3D clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK); =20 /* GMUs on A7xx votes on both x & y */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) data[bcm_index] =3D BCM_TCS_CMD(commit, true, vote, vote); else data[bcm_index] =3D BCM_TCS_CMD(commit, true, 0, vote); @@ -2035,13 +2070,14 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct= device_node *node) */ gmu->dummy.size =3D SZ_4K; if (adreno_is_a660_family(adreno_gpu) || - adreno_is_a7xx(adreno_gpu)) { + adreno_is_a7xx(adreno_gpu) || + adreno_is_a8xx(adreno_gpu)) { ret =3D a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000, "debug"); if (ret) goto err_memory; =20 - gmu->dummy.size =3D SZ_8K; + gmu->dummy.size =3D SZ_16K; } =20 /* Allocate memory for the GMU dummy page */ @@ -2052,7 +2088,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) =20 /* Note that a650 family also includes a660 family: */ if (adreno_is_a650_family(adreno_gpu) || - adreno_is_a7xx(adreno_gpu)) { + adreno_is_a7xx(adreno_gpu) || + adreno_is_a8xx(adreno_gpu)) { ret =3D a6xx_gmu_memory_alloc(gmu, &gmu->icache, SZ_16M - SZ_16K, 0x04000, "icache"); if (ret) @@ -2116,6 +2153,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) ret =3D -ENODEV; goto err_mmio; } + } else if (adreno_is_a8xx(adreno_gpu)) { + gmu->rscc =3D gmu->mmio + 0x19000; } else { gmu->rscc =3D gmu->mmio + 0x23000; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 55b1c78daa8b..edf6c282cd76 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -19,8 +19,8 @@ struct a6xx_gmu_bo { u64 iova; }; =20 -#define GMU_MAX_GX_FREQS 16 -#define GMU_MAX_CX_FREQS 4 +#define GMU_MAX_GX_FREQS 32 +#define GMU_MAX_CX_FREQS 6 #define GMU_MAX_BCMS 3 =20 struct a6xx_bcm { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 34b09cb127ed..99334deda522 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -50,6 +50,8 @@ enum adreno_family { ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ ADRENO_7XX_GEN3, /* a750 family */ + ADRENO_8XX_GEN1, /* a830 family */ + ADRENO_8XX_GEN2, /* a840 family */ }; =20 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -553,6 +555,11 @@ static inline int adreno_is_a7xx(struct adreno_gpu *gp= u) adreno_is_a740_family(gpu); } =20 +static inline int adreno_is_a8xx(struct adreno_gpu *gpu) +{ + return gpu->info->family >=3D ADRENO_8XX_GEN1; +} + /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */ #define ADRENO_VM_START 0x100000000ULL u64 adreno_private_vm_size(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gp= u/drm/msm/registers/adreno/a6xx_gmu.xml index 09b8a0b9c0de..5dce7934056d 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -66,10 +66,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> + + + + + @@ -89,7 +94,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> - + @@ -99,7 +104,11 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + + + + + @@ -120,9 +129,12 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> - - - + + + + + + @@ -130,8 +142,10 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> - - + + + + @@ -164,6 +178,14 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> + + + + + + + + @@ -233,12 +255,12 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - - + + + + + + =20 --=20 2.51.0