From nobody Sun Feb 8 18:23:59 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 946332E3AF2 for ; Fri, 14 Nov 2025 07:11:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104296; cv=none; b=Y55Bk1HUF3pbIL9IjBIVbJvQR78RHzfra/ZPNauVHEmzM2e0eF1xkj2ya5iDN/StBft1hKmEpIfFXEFwEW/lM0C3f0UCK0j0kX58PtoGP1SmkjOwK5t2ssU0dkVFj1Lvv9Wi95SxdzmhXK1vY14zGnN+drViyd+oFoDtj1i0HQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104296; c=relaxed/simple; bh=yEKXTKlegzyFe/T5Jb2lknPnu9seg508gMV6HdMNA1Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QbPq4hAUMRXa5rxOD6nFVfZjiyrc0s345nGFRsQ5P8tO8ngL2SKN71ND510J6/Nytw7+E6Zb+fq8tf9VF1zz7zzUAQj5bt41vKwZdwMlejI3u2X2GluCkXVNtmx/xIbHoDQi4VOGkx6rzdf25oiECWcpxVEG2a0uDQdleBjFfjc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=c1UcmXEx; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ClQ4h2S4; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="c1UcmXEx"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ClQ4h2S4" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ADMbA5H1595897 for ; Fri, 14 Nov 2025 07:11:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 88+wbiy3eMz/8rZ+Rw4j3vcISrAgAVjlc7UVyprQH8Q=; b=c1UcmXEx6Hz8lmsZ fp/KN2Mv43BMkHcQDHU/yCEcSvXHAbYy+9RgjgefcPguA1R6wIonzN95I/mS2fYj bs5urq82CHTOLCjt2w3aDvkQV/mNyqhEenmbzFSzApbX+2p1wbPatBAq0rXSExZ6 fTuhm1p7+8LzHcERcYo24Pw7zGDVHYmx1ebFiGX7wZdW0SrAAF51t03WEcjoRgJ8 zm7W9PdMS9GQ7vP0xdlX+ywyK+2mYtOGtYLvmPPBuP5t1iTk/5oOTS1PP0krj3zO UEqA2uz36vaa+tCrbERpAX8ddG2IQwt2QQjDpI+h4+X6lnlKx6wP4g5ljwxLDlsq GydUIg== Received: from mail-qv1-f70.google.com (mail-qv1-f70.google.com [209.85.219.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4adr9fs7b2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 14 Nov 2025 07:11:33 +0000 (GMT) Received: by mail-qv1-f70.google.com with SMTP id 6a1803df08f44-88236bcdfc4so48108806d6.1 for ; Thu, 13 Nov 2025 23:11:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763104293; x=1763709093; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=88+wbiy3eMz/8rZ+Rw4j3vcISrAgAVjlc7UVyprQH8Q=; b=ClQ4h2S4O9w5JaK53OJmDgUmiQp/XDtz0vGZFZ3wTY5kA5nhlulH/TkEz/lCu7Ixoj 8D2i+mQIaNu8rKlIKd+Iei0XmxWDttg/oZO3aVtZeHnI9BeKNu93ECyM0iI8lJbC0sej 2TojZqCwLBBN9JHOOO6OtyOLDbYfe62ttsLmyiLB/0YFJKB6Lm9wKMsNsIpYGsA2z78v /ipQ/1Jo1t8e4I5YGZJP2HN5/a4oieT+8zxW8ixGY4h8XgyN5YdcFhTVkFi0LACm6xaS hIaIB+3dCPChyXmi4etWtWaIxdOvD1Aqo64ptEQZ+n0k2OzE8UGXRcYoP39Me2h2E4Bk 9kBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763104293; x=1763709093; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=88+wbiy3eMz/8rZ+Rw4j3vcISrAgAVjlc7UVyprQH8Q=; b=wYFlBa5VeQFbPPPctdRRos6AxWGkCBKKgbZV8Fo9FdNFLZ0XUQow7Ilh/SFBclgguh l6GgU+4g8bpU2YZU0uMt3/fcVqu4jyZ5pHet/gIgH02vSW4bQpg1qYrhGTXePfwIlaso Bgu/dz6Gy7ls/cmIrvNLSHqLuaBr9CCkizDkEPF9vh65LQEYhm7KJEJd0VuE3wovkqtL 5xkHQCVq6UMje0u+GYPvY1nCy6zpDg7AAZwgRx7044uEBXz0gczkIVZIBMEyQ0HnYgO0 Z0bMeFzoMH7gHGt+OcI7g3Ljx4O14wv5nz0vkliXoVVLXeeRsYzo16i4A/PTpZoq1knB 71iw== X-Gm-Message-State: AOJu0YzGK3Dfs+KCydI/pEDuhrR94I/1qUAtTzgragh1XjqpKMwreWID qXSuzQnwtg+Mr4DLYE2mTocx4H8Gg61GQnXHMXdc8D4XFsDjbLYsUB9o/HC9KDaennTM7LZcKHq LUOKykTj6tUWpxtwCv3FLnLrAIldiJa6+dBkWmaOHuYkwAkNk+doVLL6q4CuYOeWjmQo= X-Gm-Gg: ASbGncu/VjnfUoJezJLcXPbjwfuDky+dP/giQ7iNyXrO2pSsTE+4HB0BdOcQfDUbJNs oAzSEMHDUt1iaN2nzQYLU5axho20UYjuDCSZrYZWhdQqznnn8GLl79X96aGDpctQEHLoXvoyLj3 V4pSQgATy38DVs/qV+x3/O4RH4k8e/R1y6MuT1rDhEZxeCCbUzpwhhWT/Wj922cq8k0LKWbPZyO ao554JpTFi8KGEQYoVuG1lD4Ddef/OKvYjofKnFS57WE+640JMiA9kGtb342fv5On3JL8osnCSG JMH622nLpNoOwPRy7MUvqDRJKyYY15hAiEqVGKyin+/CYBO8uIhf1qPZVgTYvKgg9+I7OPNp8Uz PT81Wx6KDF8BXtykJUMtY+kp6q6amywduSVM+KeMdrC4b7+LSqOpfjw1O8Mxqsb9JrQ== X-Received: by 2002:a05:6214:410f:b0:87c:28cc:9e69 with SMTP id 6a1803df08f44-882926af38dmr23620896d6.55.1763104292227; Thu, 13 Nov 2025 23:11:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IFl3sbyUW/GdqRLDhJ4K31zUnO+d+poaEBcy/ezrLS9o/LprKIICBOPIegp4Hby01S5meYWwA== X-Received: by 2002:a05:6214:410f:b0:87c:28cc:9e69 with SMTP id 6a1803df08f44-882926af38dmr23620636d6.55.1763104291617; Thu, 13 Nov 2025 23:11:31 -0800 (PST) Received: from WENMLIU-LAB01.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-882862ce056sm26336666d6.6.2025.11.13.23.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 23:11:30 -0800 (PST) From: Wenmeng Liu Date: Fri, 14 Nov 2025 15:11:18 +0800 Subject: [PATCH v6 1/3] media: qcom: camss: Add common TPG support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-camss_tpg-v6-1-38d3d9fbe339@oss.qualcomm.com> References: <20251114-camss_tpg-v6-0-38d3d9fbe339@oss.qualcomm.com> In-Reply-To: <20251114-camss_tpg-v6-0-38d3d9fbe339@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763104282; l=24194; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=yEKXTKlegzyFe/T5Jb2lknPnu9seg508gMV6HdMNA1Q=; b=lSFQLcfqfOcvXldm07uP0YbXwWXj5Y4ZaQGmnUbdKKbNJqjdC6hJTTILwIWZCk4iQDGDxO4pv 409oDrkjnNnC8KxUDFcakMQE3L8Flh1pEZoui3+2UMstjt195W/MSrc X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Authority-Analysis: v=2.4 cv=SdD6t/Ru c=1 sm=1 tr=0 ts=6916d625 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9-4OygZIhI6akIEH2MEA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: efpuZ0myqgayYyJ81-SQAleKxslG6jLq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA1NCBTYWx0ZWRfX0a4qi0jWjFcN wANcqqql4sM9VElA8imGHb6/PBnMDazKHQ/XChPLkiWD3PyTxCxGATlot2mhYS4jWLnUzx50ja4 jdhRHeburqu1UB+eQpOI8Vrqh0EHLcocOGqct0OhcsU9nfVcqlRsi1uIEzsOrbxo/xwmQaJNtBW IuX3Sk45snLCVB0JADywZ9nprnEdK0g7ub/DZkg2uV9N1dPBkXT+dO2csv9R4WePNXVCA2SuupM Ybue2rbi+53TjQNV5wGj9IU4YFUW0MgQdUaRTLN/t/0+2HDr6Y4Mxw4s5OLOr62iMewu21H05f3 jcemJbrG3TUzM2/oKeZktoah4HevGkUd3fD3mkWUUnDdTW8rPiLhJI0kiOuNKDskoa+nVHWDOtO YIE07i+w0IUleMca5JrFROFSf7hNcQ== X-Proofpoint-ORIG-GUID: efpuZ0myqgayYyJ81-SQAleKxslG6jLq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_01,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 bulkscore=0 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140054 Introduce a new common Test Pattern Generator (TPG) implementation for Qualcomm CAMSS. This module provides a generic interface for pattern generation that can be reused by multiple platforms. Unlike CSID-integrated TPG, this TPG acts as a standalone block that emulates both CSIPHY and sensor behavior, enabling flexible test patterns without external hardware. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-tpg.c | 710 ++++++++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-tpg.h | 126 +++++ drivers/media/platform/qcom/camss/camss.h | 5 + 4 files changed, 842 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 5e349b4915130c71dbff90e73102e46dfede1520..d355e67c25700ac061b878543c3= 2ed8defc03ad0 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -27,5 +27,6 @@ qcom-camss-objs +=3D \ camss-vfe.o \ camss-video.o \ camss-format.o \ + camss-tpg.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-tpg.c b/drivers/media/= platform/qcom/camss/camss-tpg.c new file mode 100644 index 0000000000000000000000000000000000000000..feec78fcc3563f040d19c7b6eb9= 5dee541007a66 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.c @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +const char * const testgen_payload_modes[] =3D { + "Disabled", + "Incrementing", + "Alternating 0x55/0xAA", + "Reserved", + "Reserved", + "Pseudo-random Data", + "User Specified", + "Reserved", + "Reserved", + "Color bars", + "Reserved" +}; + +static const struct tpg_format_info formats_gen1[] =3D { + { + MEDIA_BUS_FMT_SBGGR8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SGBRG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SGRBG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SRGGB8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_SBGGR10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SGBRG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SGRBG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SRGGB10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, + { + MEDIA_BUS_FMT_SBGGR12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SGBRG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SGRBG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_SRGGB12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + 12, + }, + { + MEDIA_BUS_FMT_Y8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + 8, + }, + { + MEDIA_BUS_FMT_Y10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + 10, + }, +}; + +const struct tpg_formats tpg_formats_gen1 =3D { + .nformats =3D ARRAY_SIZE(formats_gen1), + .formats =3D formats_gen1 +}; + +const struct tpg_format_info *tpg_get_fmt_entry(struct tpg_device *tpg, + const struct tpg_format_info *formats, + unsigned int nformats, + u32 code) +{ + struct device *dev =3D tpg->camss->dev; + size_t i; + + for (i =3D 0; i < nformats; i++) + if (code =3D=3D formats[i].code) + return &formats[i]; + + dev_warn(dev, "Unknown pixel format code=3D0x%08x\n", code); + + return ERR_PTR(-EINVAL); +} + +/* + * tpg_set_clock_rates - set clock rates on tpg module + * @tpg: tpg device + */ +static int tpg_set_clock_rates(struct tpg_device *tpg) +{ + struct device *dev =3D tpg->camss->dev; + int ret; + int i; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + long round_rate; + + if (clock->freq[0] > 0) { + round_rate =3D clk_round_rate(clock->clk, clock->freq[0]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + ret =3D clk_set_rate(clock->clk, round_rate); + if (ret < 0) { + dev_err(dev, "clk set rate failed: %d\n", ret); + return ret; + } + } + } + + return 0; +} + +/* + * tpg_set_power - Power on/off tpg module + * @sd: tpg V4L2 subdevice + * @on: Requested power state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_power(struct v4l2_subdev *sd, int on) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct device *dev =3D tpg->camss->dev; + + if (on) { + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + ret =3D tpg_set_clock_rates(tpg); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + ret =3D camss_enable_clocks(tpg->nclocks, tpg->clock, dev); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + tpg->res->hw_ops->reset(tpg); + + tpg->res->hw_ops->hw_version(tpg); + } else { + camss_disable_clocks(tpg->nclocks, tpg->clock); + + pm_runtime_put_sync(dev); + } + + return 0; +} + +/* + * tpg_set_stream - Enable/disable streaming on tpg module + * @sd: tpg V4L2 subdevice + * @enable: Requested streaming state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + int ret =3D 0; + + if (enable) { + ret =3D v4l2_ctrl_handler_setup(&tpg->ctrls); + if (ret < 0) { + dev_err(tpg->camss->dev, + "could not sync v4l2 controls: %d\n", ret); + return ret; + } + } + + ret =3D tpg->res->hw_ops->configure_stream(tpg, enable); + + return ret; +} + +/* + * __tpg_get_format - Get pointer to format structure + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad from which format is requested + * @which: TRY or ACTIVE format + * + * Return pointer to TRY or ACTIVE format structure + */ +static struct v4l2_mbus_framefmt * +__tpg_get_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + if (which =3D=3D V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_state_get_format(sd_state, + pad); + + return &tpg->fmt[pad]; +} + +/* + * tpg_try_format - Handle try format by pad subdev method + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad on which format is requested + * @fmt: pointer to v4l2 format structure + * @which: wanted subdev format + */ +static void tpg_try_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + struct v4l2_mbus_framefmt *fmt, + enum v4l2_subdev_format_whence which) +{ + unsigned int i; + + switch (pad) { + case MSM_TPG_PAD_SINK: + for (i =3D 0; i < tpg->res->formats->nformats; i++) + if (tpg->res->formats->formats[i].code =3D=3D fmt->code) + break; + + /* If not found, use SBGGR8 as default */ + if (i >=3D tpg->res->formats->nformats) + fmt->code =3D MEDIA_BUS_FMT_SBGGR8_1X8; + + fmt->width =3D clamp_t(u32, fmt->width, 1, 8191); + fmt->height =3D clamp_t(u32, fmt->height, 1, 8191); + + fmt->field =3D V4L2_FIELD_NONE; + fmt->colorspace =3D V4L2_COLORSPACE_SRGB; + + break; + case MSM_TPG_PAD_SRC: + *fmt =3D *__tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + which); + + break; + } +} + +/* + * tpg_enum_mbus_code - Handle format enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @code: pointer to v4l2_subdev_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + if (code->pad =3D=3D MSM_TPG_PAD_SINK) { + if (code->index >=3D tpg->res->formats->nformats) + return -EINVAL; + + code->code =3D tpg->res->formats->formats[code->index].code; + } else { + if (code->index > 0) + return -EINVAL; + + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + code->which); + + code->code =3D format->code; + } + + return 0; +} + +/* + * tpg_enum_frame_size - Handle frame size enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fse: pointer to v4l2_subdev_frame_size_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt format; + + if (fse->index !=3D 0) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D 1; + format.height =3D 1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->min_width =3D format.width; + fse->min_height =3D format.height; + + if (format.code !=3D fse->code) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D -1; + format.height =3D -1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->max_width =3D format.width; + fse->max_height =3D format.height; + + return 0; +} + +/* + * tpg_get_format - Handle get format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + fmt->format =3D *format; + + return 0; +} + +/* + * tpg_set_format - Handle set format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + tpg_try_format(tpg, sd_state, fmt->pad, &fmt->format, + fmt->which); + *format =3D fmt->format; + + if (fmt->pad =3D=3D MSM_TPG_PAD_SINK) { + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SRC, + fmt->which); + + *format =3D fmt->format; + tpg_try_format(tpg, sd_state, MSM_TPG_PAD_SRC, + format, + fmt->which); + } + return 0; +} + +/* + * tpg_init_formats - Initialize formats on all pads + * @sd: tpg V4L2 subdevice + * @fh: V4L2 subdev file handle + * + * Initialize all pad formats with default values. + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_init_formats(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct v4l2_subdev_format format =3D { + .pad =3D MSM_TPG_PAD_SINK, + .which =3D fh ? V4L2_SUBDEV_FORMAT_TRY : + V4L2_SUBDEV_FORMAT_ACTIVE, + .format =3D { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .width =3D 1920, + .height =3D 1080 + } + }; + + return tpg_set_format(sd, fh ? fh->state : NULL, &format); +} + +/* + * tpg_set_test_pattern - Set test generator's pattern mode + * @tpg: TPG device + * @value: desired test pattern mode + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_test_pattern(struct tpg_device *tpg, s32 value) +{ + return tpg->res->hw_ops->configure_testgen_pattern(tpg, value); +} + +/* + * tpg_s_ctrl - Handle set control subdev method + * @ctrl: pointer to v4l2 control structure + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tpg_device *tpg =3D container_of(ctrl->handler, + struct tpg_device, ctrls); + int ret =3D -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret =3D tpg_set_test_pattern(tpg, ctrl->val); + break; + } + + return ret; +} + +static const struct v4l2_ctrl_ops tpg_ctrl_ops =3D { + .s_ctrl =3D tpg_s_ctrl, +}; + +/* + * msm_tpg_subdev_init - Initialize tpg device structure and resources + * @tpg: tpg device + * @res: tpg module resources table + * @id: tpg module id + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id) +{ + struct platform_device *pdev; + struct device *dev; + int i, j; + + dev =3D camss->dev; + pdev =3D to_platform_device(dev); + + tpg->camss =3D camss; + tpg->id =3D id; + tpg->res =3D &res->tpg; + tpg->res->hw_ops->subdev_init(tpg); + + tpg->base =3D devm_platform_ioremap_resource_byname(pdev, res->reg[0]); + if (IS_ERR(tpg->base)) + return PTR_ERR(tpg->base); + + tpg->nclocks =3D 0; + while (res->clock[tpg->nclocks]) + tpg->nclocks++; + + if (tpg->nclocks) { + tpg->clock =3D devm_kcalloc(dev, + tpg->nclocks, sizeof(*tpg->clock), + GFP_KERNEL); + if (!tpg->clock) + return -ENOMEM; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + + clock->clk =3D devm_clk_get(dev, res->clock[i]); + if (IS_ERR(clock->clk)) + return PTR_ERR(clock->clk); + + clock->name =3D res->clock[i]; + + clock->nfreqs =3D 0; + while (res->clock_rate[i][clock->nfreqs]) + clock->nfreqs++; + + if (!clock->nfreqs) { + clock->freq =3D NULL; + continue; + } + + clock->freq =3D devm_kcalloc(dev, + clock->nfreqs, + sizeof(*clock->freq), + GFP_KERNEL); + if (!clock->freq) + return -ENOMEM; + + for (j =3D 0; j < clock->nfreqs; j++) + clock->freq[j] =3D res->clock_rate[i][j]; + } + } + + return 0; +} + +/* + * tpg_link_setup - Setup tpg connections + * @entity: Pointer to media entity structure + * @local: Pointer to local pad + * @remote: Pointer to remote pad + * @flags: Link flags + * + * Return 0 on success + */ +static int tpg_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + if (flags & MEDIA_LNK_FL_ENABLED) + if (media_pad_remote_pad_first(local)) + return -EBUSY; + + return 0; +} + +static const struct v4l2_subdev_core_ops tpg_core_ops =3D { + .s_power =3D tpg_set_power, +}; + +static const struct v4l2_subdev_video_ops tpg_video_ops =3D { + .s_stream =3D tpg_set_stream, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops =3D { + .enum_mbus_code =3D tpg_enum_mbus_code, + .enum_frame_size =3D tpg_enum_frame_size, + .get_fmt =3D tpg_get_format, + .set_fmt =3D tpg_set_format, +}; + +static const struct v4l2_subdev_ops tpg_v4l2_ops =3D { + .core =3D &tpg_core_ops, + .video =3D &tpg_video_ops, + .pad =3D &tpg_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops tpg_v4l2_internal_ops =3D { + .open =3D tpg_init_formats, +}; + +static const struct media_entity_operations tpg_media_ops =3D { + .link_setup =3D tpg_link_setup, + .link_validate =3D v4l2_subdev_link_validate, +}; + +/* + * msm_tpg_register_entity - Register subdev node for tpg module + * @tpg: tpg device + * @v4l2_dev: V4L2 device + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev) +{ + struct v4l2_subdev *sd =3D &tpg->subdev; + struct media_pad *pads =3D tpg->pads; + struct device *dev =3D tpg->camss->dev; + int ret; + + v4l2_subdev_init(sd, &tpg_v4l2_ops); + sd->internal_ops =3D &tpg_v4l2_internal_ops; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; + snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", + MSM_TPG_NAME, tpg->id); + sd->grp_id =3D TPG_GUP_ID; + v4l2_set_subdevdata(sd, tpg); + + ret =3D v4l2_ctrl_handler_init(&tpg->ctrls, 1); + if (ret < 0) { + dev_err(dev, "Failed to init ctrl handler: %d\n", ret); + return ret; + } + + tpg->testgen_mode =3D v4l2_ctrl_new_std_menu_items(&tpg->ctrls, + &tpg_ctrl_ops, V4L2_CID_TEST_PATTERN, + tpg->testgen.nmodes, 0, 0, + tpg->testgen.modes); + + if (tpg->ctrls.error) { + dev_err(dev, "Failed to init ctrl: %d\n", tpg->ctrls.error); + ret =3D tpg->ctrls.error; + goto free_ctrl; + } + + tpg->subdev.ctrl_handler =3D &tpg->ctrls; + + ret =3D tpg_init_formats(sd, NULL); + if (ret < 0) { + dev_err(dev, "Failed to init format: %d\n", ret); + goto free_ctrl; + } + + pads[MSM_TPG_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; + pads[MSM_TPG_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + + sd->entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + sd->entity.ops =3D &tpg_media_ops; + ret =3D media_entity_pads_init(&sd->entity, MSM_TPG_PADS_NUM, pads); + if (ret < 0) { + dev_err(dev, "Failed to init media entity: %d\n", ret); + goto free_ctrl; + } + + ret =3D v4l2_device_register_subdev(v4l2_dev, sd); + if (ret < 0) { + dev_err(dev, "Failed to register subdev: %d\n", ret); + media_entity_cleanup(&sd->entity); + goto free_ctrl; + } + + return 0; + +free_ctrl: + v4l2_ctrl_handler_free(&tpg->ctrls); + + return ret; +} + +/* + * msm_tpg_unregister_entity - Unregister tpg module subdev node + * @tpg: tpg device + */ +void msm_tpg_unregister_entity(struct tpg_device *tpg) +{ + v4l2_device_unregister_subdev(&tpg->subdev); + media_entity_cleanup(&tpg->subdev.entity); + v4l2_ctrl_handler_free(&tpg->ctrls); +} diff --git a/drivers/media/platform/qcom/camss/camss-tpg.h b/drivers/media/= platform/qcom/camss/camss-tpg.h new file mode 100644 index 0000000000000000000000000000000000000000..25537735e3cabb62c7a0a0e9b18= 22749a277bed3 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * camss-tpg.h + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef QC_MSM_CAMSS_TPG_H +#define QC_MSM_CAMSS_TPG_H + +#include +#include +#include +#include +#include +#include + +#define MSM_TPG_PAD_SINK 0 +#define MSM_TPG_PAD_SRC 1 +#define MSM_TPG_PADS_NUM 2 + +#define DATA_TYPE_RAW_8BIT 0x2a +#define DATA_TYPE_RAW_10BIT 0x2b +#define DATA_TYPE_RAW_12BIT 0x2c + +#define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 +#define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 +#define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 +#define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 +#define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 +#define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 +#define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 + +#define TPG_GUP_ID 0 +#define MSM_TPG_NAME "msm_tpg" + +enum tpg_testgen_mode { + TPG_PAYLOAD_MODE_DISABLED =3D 0, + TPG_PAYLOAD_MODE_INCREMENTING =3D 1, + TPG_PAYLOAD_MODE_ALTERNATING_55_AA =3D 2, + TPG_PAYLOAD_MODE_RANDOM =3D 5, + TPG_PAYLOAD_MODE_USER_SPECIFIED =3D 6, + TPG_PAYLOAD_MODE_COLOR_BARS =3D 9, + TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 =3D 9, +}; + +struct tpg_testgen_config { + enum tpg_testgen_mode mode; + const char * const*modes; + u8 nmodes; +}; + +struct tpg_format_info { + u32 code; + u8 data_type; + u8 encode_format; + u8 bpp; +}; + +struct tpg_formats { + unsigned int nformats; + const struct tpg_format_info *formats; +}; + +struct tpg_device; + +struct tpg_hw_ops { + int (*configure_stream)(struct tpg_device *tpg, u8 enable); + + int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val); + + u32 (*hw_version)(struct tpg_device *tpg); + + int (*reset)(struct tpg_device *tpg); + + void (*subdev_init)(struct tpg_device *tpg); +}; + +struct tpg_subdev_resources { + u8 lane_cnt; + u8 vc_cnt; + const struct tpg_formats *formats; + const struct tpg_hw_ops *hw_ops; +}; + +struct tpg_device { + struct camss *camss; + u8 id; + struct v4l2_subdev subdev; + struct media_pad pads[MSM_TPG_PADS_NUM]; + void __iomem *base; + struct camss_clock *clock; + int nclocks; + struct tpg_testgen_config testgen; + struct v4l2_mbus_framefmt fmt[MSM_TPG_PADS_NUM]; + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *testgen_mode; + const struct tpg_subdev_resources *res; + const struct tpg_format *formats; + unsigned int nformats; +}; + +struct camss_subdev_resources; + +const struct tpg_format_info *tpg_get_fmt_entry(struct tpg_device *tpg, + const struct tpg_format_info *formats, + unsigned int nformats, + u32 code); + +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id); + +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev); + +void msm_tpg_unregister_entity(struct tpg_device *tpg); + +extern const char * const testgen_payload_modes[]; + +extern const struct tpg_formats tpg_formats_gen1; + +extern const struct tpg_hw_ops tpg_ops_gen1; + +#endif /* QC_MSM_CAMSS_TPG_H */ diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 9d9a62640e25dce0e8d45af9df01bbfd64b9bb4b..a892a87bed8bde8919200d6eac2= b7a5338763c0e 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -21,6 +21,7 @@ #include "camss-csid.h" #include "camss-csiphy.h" #include "camss-ispif.h" +#include "camss-tpg.h" #include "camss-vfe.h" #include "camss-format.h" =20 @@ -52,6 +53,7 @@ struct camss_subdev_resources { char *interrupt[CAMSS_RES_MAX]; union { struct csiphy_subdev_resources csiphy; + struct tpg_subdev_resources tpg; struct csid_subdev_resources csid; struct vfe_subdev_resources vfe; }; @@ -104,6 +106,7 @@ struct camss_resources { enum camss_version version; const char *pd_name; const struct camss_subdev_resources *csiphy_res; + const struct camss_subdev_resources *tpg_res; const struct camss_subdev_resources *csid_res; const struct camss_subdev_resources *ispif_res; const struct camss_subdev_resources *vfe_res; @@ -111,6 +114,7 @@ struct camss_resources { const struct resources_icc *icc_res; const unsigned int icc_path_num; const unsigned int csiphy_num; + const unsigned int tpg_num; const unsigned int csid_num; const unsigned int vfe_num; }; @@ -121,6 +125,7 @@ struct camss { struct media_device media_dev; struct device *dev; struct csiphy_device *csiphy; + struct tpg_device *tpg; struct csid_device *csid; struct ispif_device *ispif; struct vfe_device *vfe; --=20 2.34.1 From nobody Sun Feb 8 18:23:59 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 742562F4A19 for ; Fri, 14 Nov 2025 07:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104300; cv=none; b=skm0XB7KY4AWKcC6F6IO1xNFTsyU+dd17P0/DimVvdFyhS92BDC4vj7jeDouCnsqHjkBw5IpeTjCatWQbCMCxyRHudoYXQV3Ds1YNqfb6Yuz/5Rwz5wlaIqPIp6XriBhzsgI69TSULvq84rFiLXqknVCpQ9M6/+Ma4Lrv6465RI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104300; c=relaxed/simple; bh=eTxcwVlzQOBnGz/0g5KnnF/PMqyyWhweSs9zLsLncSs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EuwHYLoM9AD5L+YqNnI6Sby+2Squng8oqJdblDiFozxTZKzjcV0L2W2UaVGPi8aPw1H2HsCXoZoOxPqtupYXO5i+TFPenyhHgau4pl84Nwlz5bigmlQIjNiid0wjtOn39BTBR1K/FwHqy3gxPNdTigAWb0AtX/aWYNgNiNQg6VE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=iWo8tPpy; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GHfJ/QeO; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="iWo8tPpy"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GHfJ/QeO" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ADMawUH1485144 for ; Fri, 14 Nov 2025 07:11:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= P2cxNG02rqVbK6Xamryhmd9ntHtyFViQL5//XE2P+9U=; b=iWo8tPpytw0rplvR LuR6pB6gfyQ1QLkNfws0i3ptdnakpvBVi4+0DHckgsn9stuq2ahjAmbyVCT/2Fl+ BF0YobNSJHOQtthmC3wrBxKSzAIqCIk39hVLctFrby3+gQNv8/AeRVDepMu1ZQ2p aRwwirmp1zce2ySEi0bDNalP/av08ILDDqVdSZeD1exTFeJNmuxQ4/R6mLpry37r IRFduY55mh1Epya3HefoRZXRJCuEC6GmqFTedxXOcJwaUokAQsUxxz9T91x9irsT n8Nx1tJ/ZRv495GfD6cuoEkjRqKr3ZBFbn0cBume7NZDUfAPUsf03X6+e5qCPwgG 6UcWjA== Received: from mail-qv1-f70.google.com (mail-qv1-f70.google.com [209.85.219.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4adr9ch7p5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 14 Nov 2025 07:11:37 +0000 (GMT) Received: by mail-qv1-f70.google.com with SMTP id 6a1803df08f44-88041f9e686so33331806d6.1 for ; Thu, 13 Nov 2025 23:11:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763104296; x=1763709096; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=P2cxNG02rqVbK6Xamryhmd9ntHtyFViQL5//XE2P+9U=; b=GHfJ/QeOQzD3+f+E8aUahVB2rIBs9ceHvpOD7DQDYYjBCYWwoivHjALVP+AFuT6K6i 2gKo+y/+i1YYnU0xcpiqMiMXLOutcaogyPzGC7HdON4O2f7Bmc3j9nwhGC753KRkM1WD wFTbGLqfdyaaD0j/HgDYbO+7VX+XaOEa3pCXD82iHz1P1KQOZlbeHs+ulZy4HeRy+333 US/SgqX4NtkQ4VAYL0K707oj/Ec7+kjsVjpGveqLYy02g/aOUgKLrcWEgZATgWHhYRMJ 84FlikmRt7VdChIdd2tge1UMJxs7RH6lWoJkeXES2UvdkisS0JXwPbdHOkSTWxWTK6qy Rnog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763104296; x=1763709096; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=P2cxNG02rqVbK6Xamryhmd9ntHtyFViQL5//XE2P+9U=; b=mZi5lQuJ9ODY72pWx03I/2pKpR9sr8+e1eVcDtjdlrw3SBGkpgYr+nyfarhMZXA4C0 q3yoeT4gIRqB/oEU7tgHBoRZRk2pgLwCdNV3CrtTeJNgZAd4Bt0d3fbDKpOi9AqT+P9k IU8X+SPRTCI3kWc1l7UJ74yoH0O7ZtJlunXXrLZzkD3nbl9zrF+ejeiSY9poapzCJrPY eY07ZE/WGgR2s5X8y30IIOPL85e1OdrHiJ+4R60TYaPCr1XZgQo0GvC1iIzQYYtB3SW7 wro7Mqty9mRwA5vR2yu9Dk1I9p1K6BftNEzxnSkPYu8v1aomFRtIfJOMqSwdsCH6OQYx IClw== X-Gm-Message-State: AOJu0YzOKe1vgDUoXdgxIxRe+1ujye0X/SCSkVuhAmRBiBJ1mcKuPwPR vgC19Evba6WLP6ZCGxiBFmJSRisPoLJae3v1GJu6HdwNI//qSIoLyzoerz+vSJvCHFlziFm0wph IU2SfabSsK5ytZJk1q7EoAOQermKU+A/S/i8eM3mw/+8VrXfHCQ5VI6aLKykiLJtCKII= X-Gm-Gg: ASbGncsGXzTwTXgI29/Hv4yuDiNanHhBzWlBAk/8OuigPRCOzDb9F8iXBe9HpOooDMF 0BkZpwN7Je1fwWay0g4rG/Q++bMZM4IojOx+0KM7hMlfkN9bL3yOI7nSugA9MVl1Hqt2ZW0STm/ tGu6o7RYEyQA5wk9mUx++QEDV2bxlaFZFn7OjxOOn7uNAyEXpGKyE13pNgZqIvcutyjrZiOmFAq nHdgbE92lRTVLwT59MQvaxgrwwtI+R50cEy8J4jNOk92Z5wH/KKOAhO0aPfChQl/GQ1SWogs3v5 0Td3L2z1S9niN4HOmd8BYPuuFxDWD0tR+sF5g7CLa3qUqlXxmq9vWWM3dC44rsCT+1QeW/Cn3HI 6ZCLedc4VCJlHvv2QAEFeyn/r33UWfwBR6pBJy65fkQv4wW82wnlcvcZBi/oivU4Ozg== X-Received: by 2002:a05:6214:d8e:b0:7d2:e1e6:f79f with SMTP id 6a1803df08f44-88292698c76mr25592856d6.47.1763104296528; Thu, 13 Nov 2025 23:11:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IEsgG9pi01gCNpzs+G5nsmU/zFJkM5Z65NF6uhZctdBPeUne6WFTTsV8ipn9k95oGTPIxw96w== X-Received: by 2002:a05:6214:d8e:b0:7d2:e1e6:f79f with SMTP id 6a1803df08f44-88292698c76mr25592626d6.47.1763104296007; Thu, 13 Nov 2025 23:11:36 -0800 (PST) Received: from WENMLIU-LAB01.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-882862ce056sm26336666d6.6.2025.11.13.23.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 23:11:35 -0800 (PST) From: Wenmeng Liu Date: Fri, 14 Nov 2025 15:11:19 +0800 Subject: [PATCH v6 2/3] media: qcom: camss: Add link support for TPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-camss_tpg-v6-2-38d3d9fbe339@oss.qualcomm.com> References: <20251114-camss_tpg-v6-0-38d3d9fbe339@oss.qualcomm.com> In-Reply-To: <20251114-camss_tpg-v6-0-38d3d9fbe339@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763104282; l=7489; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=eTxcwVlzQOBnGz/0g5KnnF/PMqyyWhweSs9zLsLncSs=; b=VG9DEvoFjekbys0i/dppAAcGpLMs0589AKDsTcUihFaMmMbD2Vaquvasb2x4h3Mi+bP/G9HOX 6HH5jFiE0ZVB9H2Y5qzOlCYTJbOFnG8yGYuIfOX35yvXmEF17wXfUb/ X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-GUID: Mpi4aBkH55fpKJjQii2cOFSsdV5Q2Ceu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA1NSBTYWx0ZWRfXxQoACX9RBAaw 3jPJJ7AUkHAdA7WVWxWO96hpcmxWpUjWqlNmVBk6OrxPUZGj0jXDogUb03KlpVPk2whTcJL/n6H Cu/rwC+XyTF2fMrf/MyKqH2YUBOZh9rOQVAO9UkXAWBqILHPrlmXczXlCwxi2n8rMyyAYTDUdG6 opHphxaFyH+vWB0yrJFzkB0cMRMXXZFpBi+bYKOSgDyaOhW+5w2uydef7LkhXkWenP++UXu6yz2 i2tTFr7zsyjB5ZV3nHNXXxyvFAM8qpW1S6kF5pdA6cg5n0RxaV6WljDyyFOFKg8x+AFhR5Ns+yL UtewaaWidKyWVatO0Z2aMC8I9zWXlgVsGgnlbNZcyjyKB2qnoXdLqSNzXlOKOEBC03pPO6K5PDk UeUJ78hsdgi3+Xz1zgZNc6H8PszRJQ== X-Authority-Analysis: v=2.4 cv=MNdtWcZl c=1 sm=1 tr=0 ts=6916d629 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=D-OMaI2VJto731AKaP4A:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-ORIG-GUID: Mpi4aBkH55fpKJjQii2cOFSsdV5Q2Ceu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_01,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140055 TPG is connected to the csid as an entity, the link needs to be adapted. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/camss-csid.c | 43 ++++++++++++------ drivers/media/platform/qcom/camss/camss-csiphy.c | 1 + drivers/media/platform/qcom/camss/camss-csiphy.h | 2 + drivers/media/platform/qcom/camss/camss.c | 55 ++++++++++++++++++++= ++++ 4 files changed, 87 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 5284b5857368c37c202cd89dad6ae8042b637537..aea3267289ff887330480fddf3f= 8e35d9dda69e0 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -35,6 +35,8 @@ #define HW_VERSION_REVISION 16 #define HW_VERSION_GENERATION 28 =20 +#define LANE_CFG_BITWIDTH 4 + #define MSM_CSID_NAME "msm_csid" =20 const char * const csid_testgen_modes[] =3D { @@ -1227,18 +1229,22 @@ void msm_csid_get_csid_id(struct media_entity *enti= ty, u8 *id) } =20 /* - * csid_get_lane_assign - Calculate CSI2 lane assign configuration paramet= er - * @lane_cfg - CSI2 lane configuration + * csid_get_lane_assign - Calculate lane assign by csiphy/tpg lane num + * @num: lane num + * @pos_array: Array of lane positions * * Return lane assign */ -static u32 csid_get_lane_assign(struct csiphy_lanes_cfg *lane_cfg) +static u32 csid_get_lane_assign(struct csiphy_lanes_cfg *lane_cfg, int num= _lanes) { u32 lane_assign =3D 0; + int pos; int i; =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_assign |=3D lane_cfg->data[i].pos << (i * 4); + for (i =3D 0; i < num_lanes; i++) { + pos =3D lane_cfg ? lane_cfg->data[i].pos : i; + lane_assign |=3D pos << (i * LANE_CFG_BITWIDTH); + } =20 return lane_assign; } @@ -1266,6 +1272,7 @@ static int csid_link_setup(struct media_entity *entit= y, struct csid_device *csid; struct csiphy_device *csiphy; struct csiphy_lanes_cfg *lane_cfg; + struct tpg_device *tpg; =20 sd =3D media_entity_to_v4l2_subdev(entity); csid =3D v4l2_get_subdevdata(sd); @@ -1277,18 +1284,26 @@ static int csid_link_setup(struct media_entity *ent= ity, return -EBUSY; =20 sd =3D media_entity_to_v4l2_subdev(remote->entity); - csiphy =3D v4l2_get_subdevdata(sd); + if (sd->grp_id =3D=3D TPG_GUP_ID) { + tpg =3D v4l2_get_subdevdata(sd); =20 - /* If a sensor is not linked to CSIPHY */ - /* do no allow a link from CSIPHY to CSID */ - if (!csiphy->cfg.csi2) - return -EPERM; + csid->phy.lane_cnt =3D tpg->res->lane_cnt; + csid->phy.csiphy_id =3D tpg->id; + csid->phy.lane_assign =3D csid_get_lane_assign(NULL, csid->phy.lane_cnt= ); + } else { + csiphy =3D v4l2_get_subdevdata(sd); =20 - csid->phy.csiphy_id =3D csiphy->id; + /* If a sensor is not linked to CSIPHY */ + /* do no allow a link from CSIPHY to CSID */ + if (!csiphy->cfg.csi2) + return -EPERM; =20 - lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; - csid->phy.lane_cnt =3D lane_cfg->num_data; - csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg); + csid->phy.csiphy_id =3D csiphy->id; + + lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; + csid->phy.lane_cnt =3D lane_cfg->num_data; + csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg, lane_cfg->num_= data); + } } /* Decide which virtual channels to enable based on which source pads are= enabled */ if (local->flags & MEDIA_PAD_FL_SOURCE) { diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index a734fb7dde0a492cf6e33f53e379557665d54f64..c15990d9d09cc8f9960729bdc11= 2d81751b4938c 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -800,6 +800,7 @@ int msm_csiphy_register_entity(struct csiphy_device *cs= iphy, sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE; snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", MSM_CSIPHY_NAME, csiphy->id); + sd->grp_id =3D CSIPHY_GUP_ID; v4l2_set_subdevdata(sd, csiphy); =20 ret =3D csiphy_init_formats(sd, NULL); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 895f80003c441dcacf98435f91567f90afa29279..b7bcf2bdd2124f77b5354b15b33= aa1e0983143e8 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -21,6 +21,8 @@ #define MSM_CSIPHY_PAD_SRC 1 #define MSM_CSIPHY_PADS_NUM 2 =20 +#define CSIPHY_GUP_ID 1 + struct csiphy_lane { u8 pos; u8 pol; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index fcc2b2c3cba076e598bc8aacd34efce5d71713ca..43fdcb9af101ef34b118035ca9c= 68757b66118df 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4145,6 +4145,19 @@ static int camss_init_subdevices(struct camss *camss) } } =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) { + ret =3D msm_tpg_subdev_init(camss, &camss->tpg[i], + &res->tpg_res[i], i); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init tpg%d sub-device: %d\n", + i, ret); + return ret; + } + } + } + /* note: SM8250 requires VFE to be initialized before CSID */ for (i =3D 0; i < camss->res->vfe_num; i++) { ret =3D msm_vfe_subdev_init(camss, &camss->vfe[i], @@ -4233,6 +4246,23 @@ static int camss_link_entities(struct camss *camss) } } =20 + for (i =3D 0; i < camss->res->tpg_num; i++) { + for (j =3D 0; j < camss->res->csid_num; j++) { + ret =3D media_create_pad_link(&camss->tpg[i].subdev.entity, + MSM_TPG_PAD_SRC, + &camss->csid[j].subdev.entity, + MSM_CSID_PAD_SINK, + 0); + if (ret < 0) { + camss_link_err(camss, + camss->tpg[i].subdev.entity.name, + camss->csid[j].subdev.entity.name, + ret); + return ret; + } + } + } + if (camss->ispif) { for (i =3D 0; i < camss->res->csid_num; i++) { for (j =3D 0; j < camss->ispif->line_num; j++) { @@ -4337,6 +4367,19 @@ static int camss_register_entities(struct camss *cam= ss) } } =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) { + ret =3D msm_tpg_register_entity(&camss->tpg[i], + &camss->v4l2_dev); + if (ret < 0) { + dev_err(camss->dev, + "Failed to register tpg%d entity: %d\n", + i, ret); + goto err_reg_tpg; + } + } + } + for (i =3D 0; i < camss->res->csid_num; i++) { ret =3D msm_csid_register_entity(&camss->csid[i], &camss->v4l2_dev); @@ -4380,6 +4423,13 @@ static int camss_register_entities(struct camss *cam= ss) for (i--; i >=3D 0; i--) msm_csid_unregister_entity(&camss->csid[i]); =20 + i =3D camss->res->tpg_num; +err_reg_tpg: + if (camss->tpg) { + for (i--; i >=3D 0; i--) + msm_tpg_unregister_entity(&camss->tpg[i]); + } + i =3D camss->res->csiphy_num; err_reg_csiphy: for (i--; i >=3D 0; i--) @@ -4401,6 +4451,11 @@ static void camss_unregister_entities(struct camss *= camss) for (i =3D 0; i < camss->res->csiphy_num; i++) msm_csiphy_unregister_entity(&camss->csiphy[i]); =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) + msm_tpg_unregister_entity(&camss->tpg[i]); + } + for (i =3D 0; i < camss->res->csid_num; i++) msm_csid_unregister_entity(&camss->csid[i]); =20 --=20 2.34.1 From nobody Sun Feb 8 18:23:59 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82A322F5A36 for ; Fri, 14 Nov 2025 07:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104305; cv=none; b=cRuPSext1Z5w/ZSBEvPM8jANK46/+v2HstAiPQHNG/2CB/Ge+WQFBDnhVZW2tRiirGtrhJ39k+Ndum/tJfghVsIF0xxCN4Suuz6v6WIhaZtlrrypwIvndH20Iaa6VnHSKFal4E7Ej4USt7KxefKZGwYZl8KHk/f4izOWB/t/Mdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763104305; c=relaxed/simple; bh=8S31U7MmYPn2nmhGIIm4RCr89FexhlrQA6cvwYJmvFw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lJTOjeQC43ujnKUfzjGnFXvpch9JPOhiB85ZxSPl+D97YxzIADqmNBFqvCQSVwA6F6u43ntbXUVBwJGOfhfim7NXxTdaEXRuX9eMIX28E1Wm7xlK4f0jNktjO7PHJqIdn+d8A4Gv/UVLW9S2rL1AMKRLTJ91cGt8Z2GwEtWvCKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=HVpgvx3U; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hkunjBcl; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="HVpgvx3U"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hkunjBcl" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5ADMadFm1484507 for ; Fri, 14 Nov 2025 07:11:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XktchzTOMtCDjUaDtSoz0Q0aJB0fGkJ8c3O1MVr7kNE=; b=HVpgvx3UnFo/t+xd ih4LdCrS0brReCG9J9fcGk/obi4Tbifte1McgBicuwMuhHJcjyt3V/OpUOl099Fq znQA/KW88pNz+DLG1ytQ8IIUQecIHNzZOFeXRo5Cta5H77H9IHSKdoYcOszigAjB MrZhcq/1ohr9QanCg1/q7i9553jKdxt0DD87yyIyDtL/2XfLBdIFYAuh57DiLc4N 6IIF98tPLOAh7ilmi8DtMc5EIUcbdP/WSI9hTjPJ8ud1v85B+arfSHxow9iKUWEI AG+82O1r7ymTCE973uBA6aPmfjy1Tm8qyUWdGlq+PxqcfmSvZhrIaa2dJqedRbrM 3wpPag== Received: from mail-qv1-f70.google.com (mail-qv1-f70.google.com [209.85.219.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4adr9ch7pd-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 14 Nov 2025 07:11:42 +0000 (GMT) Received: by mail-qv1-f70.google.com with SMTP id 6a1803df08f44-882380bead6so48615406d6.0 for ; Thu, 13 Nov 2025 23:11:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763104301; x=1763709101; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XktchzTOMtCDjUaDtSoz0Q0aJB0fGkJ8c3O1MVr7kNE=; b=hkunjBcl92yZXnZ3SBkCmuAtE4t3dzDR2qPe9/kMgVmRuLyxovRCSrNXFkZ4xf+RvX kclablyqk2sk/NHjmMd7zDo/Cf9IZ2zQbejbQTQieFbMLpX6bfFkEo2r7L3Kq5kUwhON qQxTOr9TYDeQtc58mIDG5tfEm1vD0moZv+xEjM/bwN3UzwI/UWWCOCVB3PSwyyNu10sb E2ItF6fF1KY0DcS1pnoUyhrtNaL6U3xeX6Nx/T/Ff8p5Is+cjG9vjE2Yqjuy90UoZqun +yepGCnP+6f1nYETXgu+RJ+1trkOk+vKHIVHG0qrK/+llA4NXpXHbwXu94qaiyGLYmOv CAjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763104301; x=1763709101; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=XktchzTOMtCDjUaDtSoz0Q0aJB0fGkJ8c3O1MVr7kNE=; b=RiH+lLbnr1vpct/6z7OnyqetfvHH60dM9odgRqx959VRU4UqDsJ/ZY8FoYNB72Jd7C lV3NoLJ9DxJkeyhXSagXJcmhAuksY0gdn8m+FpjFdx3QccGu1Z7xAawTR5P+uk60b/Li amcKfMFj3HhwHn0xgoDQoF/cweZP2Ql6PiCDbOh6DhtzeSUo1h9jrSpLGhweoG1zNxNm KRSiKTMeQTt8oEZXjtv6QlkCg5aveNADEDKcBQIKld19mNlRi9GhzFr5TwxGcYzXb2xG Un0F+lwlPl8BGoN6HrQ7FZdpLZG2I3mYh3FDIumY9aWJu58JRdbJ9xpq5B97KUhiqDX8 /+QA== X-Gm-Message-State: AOJu0YyJPL+TmDHSSnzkvafYWK6oHjxERMHzf21nVFsHNJBGkaZKmLTe GwtmCNDJkOEJZUl5ggs2AOquuddaYtHqf08NbQ1EO69KrLTXPjNszraRdLrsUHn1ix+7r5o3Esz rRx1kDO5prmMJnhQjQh8pEdjkknF2MFYqOO/K/q8dzZNPAnM7uYSjrie9GmEeW7jQljg= X-Gm-Gg: ASbGncv4IjkoHBP2vJN3mEcjyw1gud0pxQMEQbOPfY3X6Nrjs/SDQy/o6IJYAXSGJ7c /mpnJvEJKWnzuFmgZ94NI/a0nDlGff36lhaAdYD5aNtOllRtsETUeSmRAanEBLzUlY2g1X6Rb8H xU3b5JwdvBfHWvKLCFMW1MRg6AZOf21+paP+AUJpBRNPptMtV5dgCUkuMp6f/INQuSut17GBg9S wGocZx+IHUQT1XYaU/9kIsehPSagiulkXV6E9KXLqxyAO/qAt96WzqBwLGR5FBEx1V+a3SuhN8y ac6Qc2ARkF9jXhFyGomrKZYfRZ6EXu7Oz90CZC9W2M0XUqv8G7pyKiawEJJepodT0CLBCy+iCBS HwRfObm2XltBcXr0QExop1aczBSpjnVCbzWwopMacC03eOAQUnNkN6eY/0bv5zP71CA== X-Received: by 2002:a05:6214:268a:b0:87b:b3a2:6727 with SMTP id 6a1803df08f44-88292695b52mr26555926d6.45.1763104301189; Thu, 13 Nov 2025 23:11:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IEwZyyV/NX/cpzzNAvb91tVO8m3mDf2wWW+E3EJcEZu+5EvyAX+MgsuTKfOobSliRbgJN79bQ== X-Received: by 2002:a05:6214:268a:b0:87b:b3a2:6727 with SMTP id 6a1803df08f44-88292695b52mr26555566d6.45.1763104300606; Thu, 13 Nov 2025 23:11:40 -0800 (PST) Received: from WENMLIU-LAB01.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-882862ce056sm26336666d6.6.2025.11.13.23.11.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 23:11:39 -0800 (PST) From: Wenmeng Liu Date: Fri, 14 Nov 2025 15:11:20 +0800 Subject: [PATCH v6 3/3] media: qcom: camss: tpg: Add TPG support for LeMans and Monaco Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251114-camss_tpg-v6-3-38d3d9fbe339@oss.qualcomm.com> References: <20251114-camss_tpg-v6-0-38d3d9fbe339@oss.qualcomm.com> In-Reply-To: <20251114-camss_tpg-v6-0-38d3d9fbe339@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763104282; l=13720; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=8S31U7MmYPn2nmhGIIm4RCr89FexhlrQA6cvwYJmvFw=; b=MtGE3nJYDNdV4886Dxjf/kv+txNGX15r0lme6Jgh3HmjFVqa/Vwe7FuJrico1KnXH/mwHD+od C9+9x3R8R1iA/wQeHftpgpZTsmIY5lNoYnZRdoYhGOt8QwnecBiWzIF X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-GUID: ObsEyGc3Hss6B-1P_mCGpcjF_j98ilkX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA1NSBTYWx0ZWRfX0+Py3X3jc7w8 4j6FV3iht38I+ajGDQTYCJHfnawflHN6HMtIPmixL3CQrno0onnYXoOsbrpJm6Ca/77AOgQvN8q OR6TjRVsk/xp89+kLbUYQCM1Hnj+l9wUioctE+OwNX7BDd+fnj1CUMbmI66jC7w2jpFGMdr6+lQ nhhz+QzBcxhy+Wud15c0z3oxCI1VWVHRDzwbKlGIJb2CL594qy5v7W26PEa7n3orGzo1Ljg+3RP kQlKwuSwLazFBUYojI2GccJI41AY2JeJgRuGaurkDuMGgnjSb6wq7IV95OYzFVh6olnYn4iit1w GlpDFOetqvO5gQKFaCUwhVk3g/dNJod99qm3qJ8aRD6WOTcNTxk29i8CYZK3/JM5b62yeXAPJBm /1RcD9wUaqj5vM4EOUYJJr54nV/QKw== X-Authority-Analysis: v=2.4 cv=MNdtWcZl c=1 sm=1 tr=0 ts=6916d62e cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=d2G8kzP7RSt0yfC46H0A:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-ORIG-GUID: ObsEyGc3Hss6B-1P_mCGpcjF_j98ilkX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_01,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140055 Add support for TPG found on LeMans and Monaco. Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen3.c | 16 ++ drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 235 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 67 ++++++ 4 files changed, 319 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index d355e67c25700ac061b878543c32ed8defc03ad0..e8996dacf1771d13ec1936c9beb= c0e71566898ef 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -28,5 +28,6 @@ qcom-camss-objs +=3D \ camss-video.o \ camss-format.o \ camss-tpg.o \ + camss-tpg-gen1.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0cac662b02f8b920cd1c72db0aeb2..2c94727daeb799aa4f72250cbb2= d9c443c5fe351 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -66,6 +66,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_NUM_EN 27 +#define CSI2_RX_CFG0_TPG_NUM_SEL 28 =20 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -109,11 +111,25 @@ static void __csid_configure_rx(struct csid_device *c= sid, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; + struct tpg_device *tpg; =20 + camss =3D csid->camss; val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; =20 + if (camss->tpg) { + tpg =3D &camss->tpg[phy->csiphy_id]; + + if (tpg->testgen.mode > 0) { + val |=3D (phy->csiphy_id + 1) << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 1 << CSI2_RX_CFG0_TPG_NUM_EN; + } else { + val &=3D ~(CSI2_RX_CFG0_TPG_NUM_SEL | CSI2_RX_CFG0_TPG_NUM_EN); + } + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..931e14f32bbeb317db33de39f24= 8f9e2870dd3a9 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG (Test Patter Generator) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +#define TPG_HW_VERSION 0x0 +# define HW_VERSION_STEPPING GENMASK(15, 0) +# define HW_VERSION_REVISION GENMASK(27, 16) +# define HW_VERSION_GENERATION GENMASK(31, 28) + +#define TPG_HW_STATUS 0x4 + +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_CTRL 0x64 +# define TPG_CTRL_TEST_EN BIT(0) +# define TPG_CTRL_PHY_SEL BIT(3) +# define TPG_CTRL_NUM_ACTIVE_LANES GENMASK(5, 4) +# define TPG_CTRL_VC_DT_PATTERN_ID GENMASK(8, 6) +# define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) +# define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) +# define NUM_ACTIVE_VC_0_ENABLED 0 +# define NUM_ACTIVE_VC_0_1_ENABLED 1 +# define NUM_ACTIVE_VC_0_1_2_ENABLED 2 +# define NUM_ACTIVE_VC_0_1_3_ENABLED 3 + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +# define TPG_VC_n_CFG0_VC_NUM GENMASK(4, 0) +# define TPG_VC_n_CFG0_NUM_ACTIVE_DT GENMASK(9, 8) +# define NUM_ACTIVE_SLOTS_0_ENABLED 0 +# define NUM_ACTIVE_SLOTS_0_1_ENABLED 1 +# define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2 +# define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3 +# define TPG_VC_n_CFG0_NUM_BATCH GENMASK(15, 12) +# define TPG_VC_n_CFG0_NUM_FRAMES GENMASK(31, 16) + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) + +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) + +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +# define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN GENMASK(2, 0) +# define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN BIT(3) +# define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN BIT(4) +# define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN BIT(5) +# define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD GENMASK(13, 8) +# define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN BIT(16) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_X GENMASK(26, 24) +# define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y GENMASK(30, 28) + +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT GENMASK(15, 0) +# define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_1_DATA_TYPE GENMASK(5, 0) +# define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK GENMASK(13, 8) +# define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK GENMASK(31, 16) + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +# define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE GENMASK(3, 0) +# define TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(27, 4) +# define TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(31, 28) + +#define TPG_VC_n_COLOR_BAR_CFA_COLOR0(n) (0xB0 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR1(n) (0xB4 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR2(n) (0xB8 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR3(n) (0xBC + (n) * 0x60) + +/* Line offset between VC(n) and VC(n-1), n form 1 to 3 */ +#define TPG_VC_n_SHDR_CFG (0x84 + (n) * 0x60) + +#define TPG_CLEAR 0x1F4 + +#define TPG_HBI_PCT_DEFAULT 545 /* 545% */ +#define TPG_VBI_PCT_DEFAULT 10 /* 10% */ +#define PERCENT_BASE 100 +#define BITS_PER_BYTE 8 + +/* Default user-specified payload for TPG test generator. + * Keep consistent with CSID TPG default: 0xBE. + */ +#define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE +#define TPG_LFSR_SEED_DEFAULT 0x12345678 +#define TPG_COLOR_BARS_CFG_STANDARD \ + FIELD_PREP(TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD, 0xA) + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg =3D &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 lane_cnt =3D tpg->res->lane_cnt; + u8 dt_cnt =3D 0; + u8 i; + u32 val; + + /* Loop through all enabled VCs and configure stream for each */ + for (i =3D 0; i < tpg->res->vc_cnt; i++) { + input_format =3D &tpg->fmt[MSM_TPG_PAD_SRC + i]; + format =3D tpg_get_fmt_entry(tpg, + tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + if (IS_ERR(format)) + return -EINVAL; + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT, input_format->heigh= t & 0xffff) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH, input_format->width & = 0xffff); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(i, dt_cnt)); + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_1_DATA_TYPE, format->data_type); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(i, dt_cnt)); + + val =3D FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, tg->mode - 1) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, + TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | + FIELD_PREP(TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT, format->encode_forma= t); + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(i, dt_cnt)); + + writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(= i)); + + val =3D DIV_ROUND_UP(input_format->width * format->bpp * TPG_HBI_PCT_DEF= AULT, + BITS_PER_BYTE * lane_cnt * PERCENT_BASE); + writel(val, tpg->base + TPG_VC_n_HBI_CFG(i)); + val =3D input_format->height * TPG_VBI_PCT_DEFAULT / PERCENT_BASE; + writel(val, tpg->base + TPG_VC_n_VBI_CFG(i)); + + writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(i)); + + /* configure one DT, infinite frames */ + val =3D FIELD_PREP(TPG_VC_n_CFG0_VC_NUM, i) | + FIELD_PREP(TPG_VC_n_CFG0_NUM_FRAMES, 0); + writel(val, tpg->base + TPG_VC_n_CFG0(i)); + } + + val =3D FIELD_PREP(TPG_CTRL_TEST_EN, 1) | + FIELD_PREP(TPG_CTRL_PHY_SEL, 0) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + FIELD_PREP(TPG_CTRL_VC_DT_PATTERN_ID, 0) | + FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, tpg->res->vc_cnt - 1); + writel(val, tpg->base + TPG_CTRL); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); +} + +static int tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + int ret =3D 0; + + if (enable) + ret =3D tpg_stream_on(tpg); + else + tpg_stream_off(tpg); + + return ret; +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val > 0 && val <=3D TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode =3D val; + + return 0; +} + +/* + * tpg_hw_version - tpg hardware version query + * @tpg: tpg device + * + * Return HW version or error + */ +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version; + u32 hw_gen; + u32 hw_rev; + u32 hw_step; + + hw_version =3D readl(tpg->base + TPG_HW_VERSION); + hw_gen =3D FIELD_GET(HW_VERSION_GENERATION, hw_version); + hw_rev =3D FIELD_GET(HW_VERSION_REVISION, hw_version); + hw_step =3D FIELD_GET(HW_VERSION_STEPPING, hw_version); + dev_dbg_once(tpg->camss->dev, "tpg HW Version =3D %u.%u.%u\n", + hw_gen, hw_rev, hw_step); + + return hw_version; +} + +/* + * tpg_reset - Trigger reset on tpg module and wait to complete + * @tpg: tpg device + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_reset(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes =3D testgen_payload_modes; + tpg->testgen.nmodes =3D TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 =3D { + .configure_stream =3D tpg_configure_stream, + .configure_testgen_pattern =3D tpg_configure_testgen_pattern, + .hw_version =3D tpg_hw_version, + .reset =3D tpg_reset, + .subdev_init =3D tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 43fdcb9af101ef34b118035ca9c68757b66118df..667fd03502058745dfbf34923a2= 6ac4a54677798 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3199,6 +3199,62 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, }; =20 +static const struct camss_subdev_resources tpg_res_8775p[] =3D { + /* TPG0 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg0" }, + .interrupt =3D { "tpg0" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG1 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg1" }, + .interrupt =3D { "tpg1" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG2 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg2" }, + .interrupt =3D { "tpg2" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] =3D { /* CSID0 */ { @@ -4674,6 +4730,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; =20 + if (camss->res->tpg_num > 0) { + camss->tpg =3D devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid =3D devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->cs= id), GFP_KERNEL); if (!camss->csid) @@ -4863,11 +4926,13 @@ static const struct camss_resources qcs8300_resourc= es =3D { .version =3D CAMSS_8300, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8300, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_qcs8300, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8300), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_qcs8300), @@ -4877,11 +4942,13 @@ static const struct camss_resources sa8775p_resourc= es =3D { .version =3D CAMSS_8775P, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8775p, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_sa8775p, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8775p), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_sa8775p), --=20 2.34.1