From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2440329BD95; Thu, 13 Nov 2025 18:01:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056885; cv=none; b=B4tftptj1b013z2ycHIWvvnKqUhBloaKFGX9Sy25Wby8Dqbwri3SAn4RhZo1BsG5MIDMv6OueEPQ3EufynFQe4a28pvYvuD5NGA9TIhwc1PbxQctPmkZsxMoOdjjmOOkhuKS9qJmpiSASelU7/5tB0JZsSnOQN/5/mnRbEkUykQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056885; c=relaxed/simple; bh=w/eqwcH4YBVoPX7qAYr81YCS6pKpZMntJReWM+XRRZ0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=aVf3sSsM5vvvMhT9sCSAWv7c+ShdnA+4G5BkC/yJelMqq/xVGZYvSNiPWHYhsDi/HtKoAZ7yXBJT38NTkqpyTWOyEeecGRdDkRusO/WekmciE4IS9cv6WiFEfzOJfZzNY/xZo9QfnTsIhawyt0GmXJ2vNmywXjkIdmlkjwG2lNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DIkh1geG; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DIkh1geG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763056883; x=1794592883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w/eqwcH4YBVoPX7qAYr81YCS6pKpZMntJReWM+XRRZ0=; b=DIkh1geGoGTQ0qbymYv9IDl4exKrEwQtoZ8JHuPQKodJ8FKtTVpVR+y5 P7cMprzYf3HC/+s7NjwqicHoOxkFdayhKr9BeYyv5W89KzMrLS3OYMF1+ 5oQpMb5hzLquU4mGfCXudE55n9auqbpeAOC25/M4KeHBisa+aQLa7qCLt X8yEuDYyoIyyczDjGEiopOZRczarXx3DQtcSRwhkQFNGDB3AYhpzhgrQW d2KD/PZ2kQs1ASxPrAGCJqurA190eyEjY/AmTFjrhLxKjkemBWLYE/AUs 7fS/dzPMmeq+k+PBgk32kj6C4sQbYgrabI4ojRN0y4qNgRTP30CFGVpcj w==; X-CSE-ConnectionGUID: NAPFc6VcQUeiG5uAoZwANg== X-CSE-MsgGUID: P/DtolZHQFebybMitcOIgA== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="75826879" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="75826879" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:01:22 -0800 X-CSE-ConnectionGUID: l+/eRDiXSuCEh657R344Lg== X-CSE-MsgGUID: KqE05w0XTvGQpxKcXpB2wg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="194713595" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.164]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:01:14 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 01/11] PCI: Move Resizable BAR code to rebar.c Date: Thu, 13 Nov 2025 20:00:43 +0200 Message-Id: <20251113180053.27944-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable For lack of a better place to put it, Resizable BAR code has been placed inside pci.c and setup-res.c that do not use it for anything. Upcoming changes are going to add more Resizable BAR related functions, increasing the code size. As pci.c is huge as is, move the Resizable BAR related code and the BAR resize code from setup-res.c to rebar.c. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- Documentation/driver-api/pci/pci.rst | 3 + drivers/pci/Makefile | 2 +- drivers/pci/pci.c | 149 ---------------- drivers/pci/pci.h | 1 + drivers/pci/rebar.c | 247 +++++++++++++++++++++++++++ drivers/pci/setup-res.c | 85 --------- 6 files changed, 252 insertions(+), 235 deletions(-) create mode 100644 drivers/pci/rebar.c diff --git a/Documentation/driver-api/pci/pci.rst b/Documentation/driver-ap= i/pci/pci.rst index 59d86e827198..99a1bbaaec5d 100644 --- a/Documentation/driver-api/pci/pci.rst +++ b/Documentation/driver-api/pci/pci.rst @@ -37,6 +37,9 @@ PCI Support Library .. kernel-doc:: drivers/pci/slot.c :export: =20 +.. kernel-doc:: drivers/pci/rebar.c + :export: + .. kernel-doc:: drivers/pci/rom.c :export: =20 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 67647f1880fb..f3c81c892786 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -4,7 +4,7 @@ =20 obj-$(CONFIG_PCI) +=3D access.o bus.o probe.o host-bridge.o \ remove.o pci.o pci-driver.o search.o \ - rom.o setup-res.o irq.o vpd.o \ + rebar.o rom.o setup-res.o irq.o vpd.o \ setup-bus.o vc.o mmap.o devres.o =20 obj-$(CONFIG_PCI) +=3D msi/ diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7dfc58b0e55e..aedf6a9932ce 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1823,32 +1823,6 @@ static void pci_restore_config_space(struct pci_dev = *pdev) } } =20 -static void pci_restore_rebar_state(struct pci_dev *pdev) -{ - unsigned int pos, nbars, i; - u32 ctrl; - - pos =3D pdev->rebar_cap; - if (!pos) - return; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); - - for (i =3D 0; i < nbars; i++, pos +=3D 8) { - struct resource *res; - int bar_idx, size; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; - res =3D pci_resource_n(pdev, bar_idx); - size =3D pci_rebar_bytes_to_size(resource_size(res)); - ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; - ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); - pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); - } -} - /** * pci_restore_state - Restore the saved state of a PCI device * @dev: PCI device that we're dealing with @@ -3687,129 +3661,6 @@ void pci_acs_init(struct pci_dev *dev) pci_enable_acs(dev); } =20 -void pci_rebar_init(struct pci_dev *pdev) -{ - pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); -} - -/** - * pci_rebar_find_pos - find position of resize ctrl reg for BAR - * @pdev: PCI device - * @bar: BAR to find - * - * Helper to find the position of the ctrl register for a BAR. - * Returns -ENOTSUPP if resizable BARs are not supported at all. - * Returns -ENOENT if no ctrl register for the BAR could be found. - */ -static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) -{ - unsigned int pos, nbars, i; - u32 ctrl; - - if (pci_resource_is_iov(bar)) { - pos =3D pci_iov_vf_rebar_cap(pdev); - bar =3D pci_resource_num_to_vf_bar(bar); - } else { - pos =3D pdev->rebar_cap; - } - - if (!pos) - return -ENOTSUPP; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); - - for (i =3D 0; i < nbars; i++, pos +=3D 8) { - int bar_idx; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); - if (bar_idx =3D=3D bar) - return pos; - } - - return -ENOENT; -} - -/** - * pci_rebar_get_possible_sizes - get possible sizes for BAR - * @pdev: PCI device - * @bar: BAR to query - * - * Get the possible sizes of a resizable BAR as bitmask defined in the spec - * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. - */ -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) -{ - int pos; - u32 cap; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return 0; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - cap =3D FIELD_GET(PCI_REBAR_CAP_SIZES, cap); - - /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ - if (pdev->vendor =3D=3D PCI_VENDOR_ID_ATI && pdev->device =3D=3D 0x731f && - bar =3D=3D 0 && cap =3D=3D 0x700) - return 0x3f00; - - return cap; -} -EXPORT_SYMBOL(pci_rebar_get_possible_sizes); - -/** - * pci_rebar_get_current_size - get the current size of a BAR - * @pdev: PCI device - * @bar: BAR to set size to - * - * Read the size of a BAR from the resizable BAR config. - * Returns size if found or negative error code. - */ -int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) -{ - int pos; - u32 ctrl; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return pos; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); -} - -/** - * pci_rebar_set_size - set a new size for a BAR - * @pdev: PCI device - * @bar: BAR to set size to - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) - * - * Set the new size of a BAR as defined in the spec. - * Returns zero if resizing was successful, error code otherwise. - */ -int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) -{ - int pos; - u32 ctrl; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return pos; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; - ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); - pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); - - if (pci_resource_is_iov(bar)) - pci_iov_resource_set_size(pdev, bar, size); - - return 0; -} - /** * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port * @dev: the PCI device diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 9893ea12d1f2..41df35920632 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1021,6 +1021,7 @@ static inline int acpi_get_rc_resources(struct device= *dev, const char *hid, #endif =20 void pci_rebar_init(struct pci_dev *pdev); +void pci_restore_rebar_state(struct pci_dev *pdev); int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); static inline u64 pci_rebar_size_to_bytes(int size) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c new file mode 100644 index 000000000000..f6ed7e4893a7 --- /dev/null +++ b/drivers/pci/rebar.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Resizable BAR Extended Capability handling. + */ + +#include +#include +#include +#include +#include +#include + +#include "pci.h" + +void pci_rebar_init(struct pci_dev *pdev) +{ + pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); +} + +/** + * pci_rebar_find_pos - find position of resize ctrl reg for BAR + * @pdev: PCI device + * @bar: BAR to find + * + * Helper to find the position of the ctrl register for a BAR. + * Returns -ENOTSUPP if resizable BARs are not supported at all. + * Returns -ENOENT if no ctrl register for the BAR could be found. + */ +static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + if (pci_resource_is_iov(bar)) { + pos =3D pci_iov_vf_rebar_cap(pdev); + bar =3D pci_resource_num_to_vf_bar(bar); + } else { + pos =3D pdev->rebar_cap; + } + + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); + if (bar_idx =3D=3D bar) + return pos; + } + + return -ENOENT; +} + +/** + * pci_rebar_get_possible_sizes - get possible sizes for BAR + * @pdev: PCI device + * @bar: BAR to query + * + * Get the possible sizes of a resizable BAR as bitmask defined in the spec + * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. + */ +u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap =3D FIELD_GET(PCI_REBAR_CAP_SIZES, cap); + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_ATI && pdev->device =3D=3D 0x731f && + bar =3D=3D 0 && cap =3D=3D 0x700) + return 0x3f00; + + return cap; +} +EXPORT_SYMBOL(pci_rebar_get_possible_sizes); + +/** + * pci_rebar_get_current_size - get the current size of a BAR + * @pdev: PCI device + * @bar: BAR to set size to + * + * Read the size of a BAR from the resizable BAR config. + * Returns size if found or negative error code. + */ +int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) +{ + int pos; + u32 ctrl; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return pos; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); +} + +/** + * pci_rebar_set_size - set a new size for a BAR + * @pdev: PCI device + * @bar: BAR to set size to + * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * + * Set the new size of a BAR as defined in the spec. + * Returns zero if resizing was successful, error code otherwise. + */ +int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) +{ + int pos; + u32 ctrl; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return pos; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + + if (pci_resource_is_iov(bar)) + pci_iov_resource_set_size(pdev, bar, size); + + return 0; +} + +void pci_restore_rebar_state(struct pci_dev *pdev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos =3D pdev->rebar_cap; + if (!pos) + return; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + struct resource *res; + int bar_idx, size; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; + res =3D pci_resource_n(pdev, bar_idx); + size =3D pci_rebar_bytes_to_size(resource_size(res)); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + } +} + +static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, + int resno) +{ + u16 cmd; + + if (pci_resource_is_iov(resno)) + return pci_iov_is_memory_decoding_enabled(dev); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + + return cmd & PCI_COMMAND_MEMORY; +} + +void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size) +{ + resource_size_t res_size =3D pci_rebar_size_to_bytes(size); + struct resource *res =3D pci_resource_n(dev, resno); + + if (pci_resource_is_iov(resno)) + res_size *=3D pci_sriov_get_totalvfs(dev); + + resource_set_size(res, res_size); +} + +/** + * pci_resize_resource - reconfigure a Resizable BAR and resources + * @dev: the PCI device + * @resno: index of the BAR to be resized + * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * @exclude_bars: a mask of BARs that should not be released + * + * Reconfigure @resno to @size and re-run resource assignment algorithm + * with the new size. + * + * Prior to resize, release @dev resources that share a bridge window with + * @resno. This unpins the bridge window resource to allow changing it. + * + * The caller may prevent releasing a particular BAR by providing + * @exclude_bars mask, but this may result in the resize operation failing + * due to insufficient space. + * + * Return: 0 on success, or negative on error. In case of an error, the + * resources are restored to their original places. + */ +int pci_resize_resource(struct pci_dev *dev, int resno, int size, + int exclude_bars) +{ + struct pci_host_bridge *host; + int old, ret; + u32 sizes; + + /* Check if we must preserve the firmware's resource assignment */ + host =3D pci_find_host_bridge(dev->bus); + if (host->preserve_config) + return -ENOTSUPP; + + if (pci_resize_is_memory_decoding_enabled(dev, resno)) + return -EBUSY; + + sizes =3D pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return -ENOTSUPP; + + if (!(sizes & BIT(size))) + return -EINVAL; + + old =3D pci_rebar_get_current_size(dev, resno); + if (old < 0) + return old; + + ret =3D pci_rebar_set_size(dev, resno, size); + if (ret) + return ret; + + ret =3D pci_do_resource_release_and_resize(dev, resno, size, exclude_bars= ); + if (ret) + goto error_resize; + return 0; + +error_resize: + pci_rebar_set_size(dev, resno, old); + return ret; +} +EXPORT_SYMBOL(pci_resize_resource); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index caec9fec5d03..e5fcadfc58b0 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -431,91 +431,6 @@ int pci_release_resource(struct pci_dev *dev, int resn= o) } EXPORT_SYMBOL(pci_release_resource); =20 -static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, - int resno) -{ - u16 cmd; - - if (pci_resource_is_iov(resno)) - return pci_iov_is_memory_decoding_enabled(dev); - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - - return cmd & PCI_COMMAND_MEMORY; -} - -void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size) -{ - resource_size_t res_size =3D pci_rebar_size_to_bytes(size); - struct resource *res =3D pci_resource_n(dev, resno); - - if (pci_resource_is_iov(resno)) - res_size *=3D pci_sriov_get_totalvfs(dev); - - resource_set_size(res, res_size); -} - -/** - * pci_resize_resource - reconfigure a Resizable BAR and resources - * @dev: the PCI device - * @resno: index of the BAR to be resized - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) - * @exclude_bars: a mask of BARs that should not be released - * - * Reconfigure @resno to @size and re-run resource assignment algorithm - * with the new size. - * - * Prior to resize, release @dev resources that share a bridge window with - * @resno. This unpins the bridge window resource to allow changing it. - * - * The caller may prevent releasing a particular BAR by providing - * @exclude_bars mask, but this may result in the resize operation failing - * due to insufficient space. - * - * Return: 0 on success, or negative on error. In case of an error, the - * resources are restored to their original places. - */ -int pci_resize_resource(struct pci_dev *dev, int resno, int size, - int exclude_bars) -{ - struct pci_host_bridge *host; - int old, ret; - u32 sizes; - - /* Check if we must preserve the firmware's resource assignment */ - host =3D pci_find_host_bridge(dev->bus); - if (host->preserve_config) - return -ENOTSUPP; - - if (pci_resize_is_memory_decoding_enabled(dev, resno)) - return -EBUSY; - - sizes =3D pci_rebar_get_possible_sizes(dev, resno); - if (!sizes) - return -ENOTSUPP; - - if (!(sizes & BIT(size))) - return -EINVAL; - - old =3D pci_rebar_get_current_size(dev, resno); - if (old < 0) - return old; - - ret =3D pci_rebar_set_size(dev, resno, size); - if (ret) - return ret; - - ret =3D pci_do_resource_release_and_resize(dev, resno, size, exclude_bars= ); - if (ret) - goto error_resize; - return 0; - -error_resize: - pci_rebar_set_size(dev, resno, old); - return ret; -} -EXPORT_SYMBOL(pci_resize_resource); - int pci_enable_resources(struct pci_dev *dev, int mask) { u16 cmd, old_cmd; --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F15229BD95; Thu, 13 Nov 2025 18:01:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056899; cv=none; b=hg7fmi0r4nO6KZqk4UnEz9D4Pk6lyi3s+acEaPkmZyefQgjXST4JqRWto1cveBGUSV8JK4Ew7ntYG35KEkYUZhw21ztTQ90joOp16opxcdE1Yos4zyzGJO8g8MAWyA+D8Smvo8GfgwgVtb5au2mqS0DnJlpc9a31r2QALXdjsCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056899; c=relaxed/simple; bh=Mhb9W5CShBH9lUW5aOdaQ3Fc0vAw/2EZR+ZRatwurTQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=gHhVjQszhnQXAttuAMmzUwOlyzuhYBFAN7BqXqJzPxZXON/ey6sfdv/pxRdL4pEtB+JW3ALUGr1eiqKJynrIMathmOQotdKOSeVyCRGMj3hli+rC1fUgXS18hJHPjcwLbWqnJ7O3Dya0kitWwluW0+bospC8vXAyb8m0B+omt7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MHVARSFP; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MHVARSFP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763056898; x=1794592898; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mhb9W5CShBH9lUW5aOdaQ3Fc0vAw/2EZR+ZRatwurTQ=; b=MHVARSFPH/dQuzUF0E4FjL0BfK+idNxEknvVbVw5/W7N+6jl8IX6jlEk ig7TSl3S1aYpLxCJO3Y5+Tu9sedTGKAX4+Sb0KEg15ihTEE/Ae7NX65eF qCIQOE9Bk29dnuAsj/TVFgU48NccQn9yqCQNq7GEWKZo+0bURwHzdYTXB 07NqFc48L8l1SD64BINt+HbrZipflXn/VGyAufkzV1AtaqtQA54C6vva2 0v4o1NGIMJ1mf1ileEMx9FJsX3PjA1acXWU1IGt102QO1hxGiT8JeH5w/ Q/BdSoWyJJ+1L5/mBCuYXGjWl36cOo/vdN2lmS4iBWGeoLXqCLdtBQN2m g==; X-CSE-ConnectionGUID: EvELzVvGT5eBaA08PZxh/g== X-CSE-MsgGUID: 9ncLbq2CTl+55vjkD3EqAA== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="52710946" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="52710946" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:01:36 -0800 X-CSE-ConnectionGUID: C+/nr2tmSy2iDXrs8M2vFQ== X-CSE-MsgGUID: XLm8AHb6RteJDIg01Kchxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="189574021" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.164]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:01:28 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 02/11] PCI: Clean up pci_rebar_bytes_to_size() and move to rebar.c Date: Thu, 13 Nov 2025 20:00:44 +0200 Message-Id: <20251113180053.27944-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move pci_rebar_bytes_to_size() from include/linux/pci.h to rebar.c as it does not look very trivial and is not expected to be performance critical. Convert literals to use a newly added PCI_REBAR_MIN_SIZE define. Also add kernel doc for the function as the function is exported. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig Reviewed-by: Michael J. Ruhl --- drivers/pci/rebar.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 10 +++------- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index f6ed7e4893a7..0eb6fc445703 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -7,11 +7,34 @@ #include #include #include +#include #include +#include #include =20 #include "pci.h" =20 +#define PCI_REBAR_MIN_SIZE ((resource_size_t)SZ_1M) + +/** + * pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size + * @bytes: size in bytes + * + * Convert bytes to BAR Size in Resizable BAR Capability (PCIe r6.2, + * sec. 7.8.6.3). + * + * Return: BAR Size as defined in the PCIe spec (0=3D1MB, 31=3D128TB). + */ +int pci_rebar_bytes_to_size(u64 bytes) +{ + int rebar_minsize =3D ilog2(PCI_REBAR_MIN_SIZE); + + bytes =3D roundup_pow_of_two(bytes); + + return max(ilog2(bytes), rebar_minsize) - rebar_minsize; +} +EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size); + void pci_rebar_init(struct pci_dev *pdev) { pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); diff --git a/include/linux/pci.h b/include/linux/pci.h index 34ff295cd2e3..628dda63b9e0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1419,17 +1419,13 @@ void pcibios_reset_secondary_bus(struct pci_dev *de= v); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int pci_release_resource(struct pci_dev *dev, int resno); -static inline int pci_rebar_bytes_to_size(u64 bytes) -{ - bytes =3D roundup_pow_of_two(bytes); - - /* Return BAR size as defined in the resizable BAR specification */ - return max(ilog2(bytes), 20) - 20; -} =20 +/* Resizable BAR related routines */ +int pci_rebar_bytes_to_size(u64 bytes); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, int exclude_bars); + int pci_select_bars(struct pci_dev *dev, unsigned long flags); bool pci_device_is_present(struct pci_dev *pdev); void pci_ignore_hotplug(struct pci_dev *dev); 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 03/11] PCI: Move pci_rebar_size_to_bytes() and export it Date: Thu, 13 Nov 2025 20:00:45 +0200 Message-Id: <20251113180053.27944-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_rebar_size_to_bytes() is in drivers/pci/pci.h but would be useful for endpoint drivers as well. Move the function to rebar.c and export it. In addition, convert the literal to where the number comes from (PCI_REBAR_MIN_SIZE). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/pci.h | 4 ---- drivers/pci/rebar.c | 12 ++++++++++++ include/linux/pci.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 41df35920632..a1e7dbeb0f2c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1024,10 +1024,6 @@ void pci_rebar_init(struct pci_dev *pdev); void pci_restore_rebar_state(struct pci_dev *pdev); int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); -static inline u64 pci_rebar_size_to_bytes(int size) -{ - return 1ULL << (size + 20); -} =20 struct device_node; =20 diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 0eb6fc445703..8b291d3e0ad4 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -35,6 +35,18 @@ int pci_rebar_bytes_to_size(u64 bytes) } EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size); =20 +/** + * pci_rebar_size_to_bytes - Convert BAR Size to bytes + * @size: BAR Size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) + * + * Return: BAR size in bytes. + */ +resource_size_t pci_rebar_size_to_bytes(int size) +{ + return 1ULL << (size + ilog2(PCI_REBAR_MIN_SIZE)); +} +EXPORT_SYMBOL_GPL(pci_rebar_size_to_bytes); + void pci_rebar_init(struct pci_dev *pdev) { pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); diff --git a/include/linux/pci.h b/include/linux/pci.h index 628dda63b9e0..33b27e0c4f3e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1422,6 +1422,7 @@ int pci_release_resource(struct pci_dev *dev, int res= no); =20 /* Resizable BAR related routines */ int pci_rebar_bytes_to_size(u64 bytes); +resource_size_t pci_rebar_size_to_bytes(int size); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, int exclude_bars); --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E3EC2F8BF7; Thu, 13 Nov 2025 18:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 04/11] PCI: Improve Resizable BAR functions kernel doc Date: Thu, 13 Nov 2025 20:00:46 +0200 Message-Id: <20251113180053.27944-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Fix the copy-pasted errors in the Resizable BAR handling functions kernel doc and generally improve wording choices. Fix the formatting errors of the Return: line. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/rebar.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 8b291d3e0ad4..e5c0ea6d6063 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -53,13 +53,15 @@ void pci_rebar_init(struct pci_dev *pdev) } =20 /** - * pci_rebar_find_pos - find position of resize ctrl reg for BAR + * pci_rebar_find_pos - find position of resize control reg for BAR * @pdev: PCI device * @bar: BAR to find * - * Helper to find the position of the ctrl register for a BAR. - * Returns -ENOTSUPP if resizable BARs are not supported at all. - * Returns -ENOENT if no ctrl register for the BAR could be found. + * Helper to find the position of the control register for a BAR. + * + * Return: + * * %-ENOTSUPP if resizable BARs are not supported at all, + * * %-ENOENT if no control register for the BAR could be found. */ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) { @@ -92,12 +94,14 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int= bar) } =20 /** - * pci_rebar_get_possible_sizes - get possible sizes for BAR + * pci_rebar_get_possible_sizes - get possible sizes for Resizable BAR * @pdev: PCI device * @bar: BAR to query * - * Get the possible sizes of a resizable BAR as bitmask defined in the spec - * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. + * Get the possible sizes of a resizable BAR as bitmask. + * + * Return: A bitmask of possible sizes (bit 0=3D1MB, bit 31=3D128TB), or %= 0 if + * BAR isn't resizable. */ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) { @@ -121,12 +125,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev= , int bar) EXPORT_SYMBOL(pci_rebar_get_possible_sizes); =20 /** - * pci_rebar_get_current_size - get the current size of a BAR + * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device - * @bar: BAR to set size to + * @bar: BAR to get the size from * - * Read the size of a BAR from the resizable BAR config. - * Returns size if found or negative error code. + * Reads the current size of a BAR from the Resizable BAR config. + * + * Return: BAR Size if @bar is resizable (0=3D1MB, 31=3D128TB), or negativ= e on + * error. */ int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) { @@ -142,13 +148,14 @@ int pci_rebar_get_current_size(struct pci_dev *pdev, = int bar) } =20 /** - * pci_rebar_set_size - set a new size for a BAR + * pci_rebar_set_size - set a new size for a Resizable BAR * @pdev: PCI device * @bar: BAR to set size to - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * @size: new size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) * * Set the new size of a BAR as defined in the spec. - * Returns zero if resizing was successful, error code otherwise. + * + * Return: %0 if resizing was successful, or negative on error. */ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) { --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 469C13043B8; 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 05/11] PCI: Add pci_rebar_size_supported() helper Date: Thu, 13 Nov 2025 20:00:47 +0200 Message-Id: <20251113180053.27944-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Many callers of pci_rebar_get_possible_sizes() are interested in finding out if a particular encoded BAR Size (PCIe r7.0, sec 7.8.6.3) is supported by the particular BAR. Add pci_rebar_size_supported() into PCI core to make it easy for the drivers to determine if the BAR size is supported or not. Use the new function in pci_resize_resource() and in pci_iov_vf_bar_set_size(). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig Reviewed-by: Andi Shyti --- drivers/pci/iov.c | 8 +------- drivers/pci/rebar.c | 25 +++++++++++++++++++------ include/linux/pci.h | 1 + 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 04b675e90963..71ed85d38508 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1339,19 +1339,13 @@ EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); */ int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) { - u32 sizes; - if (!pci_resource_is_iov(resno)) return -EINVAL; =20 if (pci_iov_is_memory_decoding_enabled(dev)) return -EBUSY; =20 - sizes =3D pci_rebar_get_possible_sizes(dev, resno); - if (!sizes) - return -ENOTSUPP; - - if (!(sizes & BIT(size))) + if (!pci_rebar_size_supported(dev, resno, size)) return -EINVAL; =20 return pci_rebar_set_size(dev, resno, size); diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index e5c0ea6d6063..0e7bf2d380cf 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -3,6 +3,7 @@ * PCI Resizable BAR Extended Capability handling. */ =20 +#include #include #include #include @@ -124,6 +125,23 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev,= int bar) } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); =20 +/** + * pci_rebar_size_supported - check if size is supported for BAR + * @pdev: PCI device + * @bar: BAR to check + * @size: size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) + * + * Return: %true if @bar is resizable and @size is a supported, otherwise + * %false. + */ +bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size) +{ + u64 sizes =3D pci_rebar_get_possible_sizes(pdev, bar); + + return BIT(size) & sizes; +} +EXPORT_SYMBOL_GPL(pci_rebar_size_supported); + /** * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device @@ -252,7 +270,6 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size, { struct pci_host_bridge *host; int old, ret; - u32 sizes; =20 /* Check if we must preserve the firmware's resource assignment */ host =3D pci_find_host_bridge(dev->bus); @@ -262,11 +279,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno= , int size, if (pci_resize_is_memory_decoding_enabled(dev, resno)) return -EBUSY; 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Jani Nikula Subject: [PATCH v4 06/11] drm/i915/gt: Use pci_rebar_size_supported() Date: Thu, 13 Nov 2025 20:00:48 +0200 Message-Id: <20251113180053.27944-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core provides pci_rebar_size_supported() that helps in checking if an encoded BAR Size is supported for the BAR or not. Use it in i915_resize_lmem_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Jani Nikula Reviewed-by: Andi Shyti Acked-by: Christian K=C3=B6nig Acked-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/= i915/gt/intel_region_lmem.c index c37a0560ebe0..15e83ce00eff 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -49,16 +49,12 @@ static void i915_resize_lmem_bar(struct drm_i915_privat= e *i915, resource_size_t current_size =3D roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR= )); =20 if (i915->params.lmem_bar_size) { - u32 bar_sizes; - - rebar_size =3D i915->params.lmem_bar_size * - (resource_size_t)SZ_1M; - bar_sizes =3D pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR); - + rebar_size =3D i915->params.lmem_bar_size * (resource_size_t)SZ_1M; if (rebar_size =3D=3D current_size) return; =20 - if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) || + if (!pci_rebar_size_supported(pdev, GEN12_LMEM_BAR, + pci_rebar_bytes_to_size(rebar_size)) || rebar_size >=3D roundup_pow_of_two(lmem_size)) { rebar_size =3D lmem_size; =20 --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EF352E88AB; Thu, 13 Nov 2025 18:02:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056977; cv=none; b=P40LyywGC34LMJdIMnLhiRaarK8kPvnaB5X/SlZrXJPjktyCsdWFLRRTt5umIVKp5ksEao+rif+cRw8IYOVPb4EFPEtRV+2F9Xj5eX2wRFyQ2fObncTUSxPC7gGYW+2/YJB3bO3tPD7+2BU58ZhJ21Z4XdcAnj3JdhpkDbhQ1H0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056977; c=relaxed/simple; bh=M2purkX58XpoDCgPpoqBbZEYXtvs2qMrCZ98GWMYAVU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=SKj3d5wWXBTJpIX0p/vhr8T3P9u7lbAaQ9bSzFH7uNJAQKS8EvQi/BBMkIIlZqpli0ED6F8v4D/g0y0Qk609xE8tdCP+tz/vMwnkbrKPRTMDfYiP2mI+MG2WpxpOFnWwpWatdumsO77d/W7+6Q/AE5L2fNrcafNfdLtn/ujVjPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XKFGY+v5; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XKFGY+v5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763056976; x=1794592976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M2purkX58XpoDCgPpoqBbZEYXtvs2qMrCZ98GWMYAVU=; b=XKFGY+v5YMQJItmkifkdaTCUfmSCwd04JqBpxLS+IlX+pDTNDOlhM9PC EERAtyvo81btjC4GAO0gfe2pVdsWbT3FWHYra+rvH+9I09ev/0P49TbfE pB6KX+GUiPMHNZ6iiCepch9x7ijx2y4jvYh2lWf1jWgbQ4A6PC79OrMYF WGX8vcC+rocriEJ/+TlUK25eDoFsKwOVjhFcm+iUxrVAwMVFFyYuo3MMI b7nehuXA+WDFn69MHVOX34sPj+ZM2y+ufkwMsD54lzZXHjulQVb0DWtXH tq7cSyTSRGjpkdrRA3e5BhKs/cFpN8waMevOH54Vvd8p2yzFToXhdZ5r7 Q==; X-CSE-ConnectionGUID: CpKmOgJQTb+gui/5rkoE7g== X-CSE-MsgGUID: 60HHFdl5QYabbFRU/OeTzg== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="76490823" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="76490823" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:02:43 -0800 X-CSE-ConnectionGUID: 525jiC4/Thyf8IZn8GihIw== X-CSE-MsgGUID: 0P8PNuQPR5yMWWDUTn2X4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="189407973" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.164]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:02:35 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 07/11] drm/xe/vram: Use PCI rebar helpers in resize_vram_bar() Date: Thu, 13 Nov 2025 20:00:49 +0200 Message-Id: <20251113180053.27944-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core provides pci_rebar_size_supported() and pci_rebar_size_to_bytes(); use them in resize_vram_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Christian K=C3=B6nig Acked-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_vram.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 5aacab9358a4..57c224fa0b56 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -24,8 +24,6 @@ #include "xe_vram.h" #include "xe_vram_types.h" =20 -#define BAR_SIZE_SHIFT 20 - static void _resize_bar(struct xe_device *xe, int resno, resource_size_t size) { @@ -71,25 +69,22 @@ static void resize_vram_bar(struct xe_device *xe) =20 /* set to a specific size? */ if (force_vram_bar_size) { - u32 bar_size_bit; - - rebar_size =3D force_vram_bar_size * (resource_size_t)SZ_1M; + rebar_size =3D pci_rebar_bytes_to_size(force_vram_bar_size * + (resource_size_t)SZ_1M); =20 - bar_size_bit =3D bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size)= ); - - if (!bar_size_bit) { + if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) { drm_info(&xe->drm, "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", - (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20); + (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, + bar_size_mask, (u64)current_size >> 20); return; } =20 - rebar_size =3D 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT); - + rebar_size =3D pci_rebar_size_to_bytes(rebar_size); if (rebar_size =3D=3D current_size) return; } else { - rebar_size =3D 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT); + rebar_size =3D pci_rebar_size_to_bytes(__fls(bar_size_mask)); =20 /* only resize if larger than current */ if (rebar_size <=3D current_size) --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2456B30215B; Thu, 13 Nov 2025 18:02:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056978; cv=none; b=e2vr6fei+c1CC/KzS78HTF851bs+4s3vscN06FEgCy53/D2/bzxjrBl3BbOfjZYXbZ7RfXdr5ViXqlIHUJ9XsGvsW2bqE5hRkIJTK8qA2C2GwkYkDFbtUoonjS6hMiPaBnysTwXdptYPGPhobO/nmUNTSz3OpRwnvd7GmKdJBEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763056978; c=relaxed/simple; bh=l0j9ML8iHiATiqtmWBVUlBorQSkfSz4beQCfgWXYnN4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=PlYJ0GbZfLPTQ2GapCIFdvHzTywvjIAnNwULKF1x59ks+0lcuffIZRmq9IrMUcvs11EgNtTDP2Wkt2wrEPIpqqReTiGiLcznE5zJnLUNDppPp28+uL1tjR64/h3GglrDZV7gdhxG0TjZ6JgOpUx0gcun1ddhnqnEjgRFtYm2slw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Wvwp5olN; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Wvwp5olN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763056977; x=1794592977; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l0j9ML8iHiATiqtmWBVUlBorQSkfSz4beQCfgWXYnN4=; b=Wvwp5olNeqgSmZdHYu/1vNhJ/htcMZX02Bh74iTo95RVjryfLUsBK2yM T8JunuyH0F9dHduPoSQ6muEtJ0ec+kIU9bgNSc6UtbTJOEOs71uHAsFwB SCFb9hVTuOf42ukc/6lomKJsYNRxOQYjEW7VbqhRGGvggivnCnv1SB6wP K3VjXIW9c6N/qsUsJjQM5viKhbAyNR7I6xjL2OSqIKGDA4jHr1bzuxDo9 4WUTBVbtJIGmKtVAYpHX5PruOresyAiIH16c8Nb7P6L/9QxaRKfB6tpJu YoJC+CzAaBxtecZ8Hdh4GtQ7HSnz3I19m8BqQrglMGs9yl9FmIkvlfC7O A==; X-CSE-ConnectionGUID: Upj92HXRQ++bqcvYd6bM9A== X-CSE-MsgGUID: mcv+EykOSEayTk9rlmNYjQ== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="76490856" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="76490856" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:02:54 -0800 X-CSE-ConnectionGUID: OZKbIj+1QzunwNdade7fiw== X-CSE-MsgGUID: nvag0MhwTguX3yOZqHme5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="189407984" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.164]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:02:47 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 08/11] PCI: Add pci_rebar_get_max_size() Date: Thu, 13 Nov 2025 20:00:50 +0200 Message-Id: <20251113180053.27944-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add pci_rebar_get_max_size() to allow simplifying code that wants to know the maximum possible size for a Resizable BAR. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/rebar.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 0e7bf2d380cf..d85d458c7007 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -142,6 +143,28 @@ bool pci_rebar_size_supported(struct pci_dev *pdev, in= t bar, int size) } EXPORT_SYMBOL_GPL(pci_rebar_size_supported); =20 +/** + * pci_rebar_get_max_size - get the maximum supported size of a BAR + * @pdev: PCI device + * @bar: BAR to query + * + * Get the largest supported size of a resizable BAR as a size. + * + * Returns: the maximum BAR size as defined in the PCIe spec (0=3D1MB, 31= =3D128TB), + * or %-NOENT on error. + */ +int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) +{ + u32 sizes; + + sizes =3D pci_rebar_get_possible_sizes(pdev, bar); + if (!sizes) + return -ENOENT; + + return __fls(sizes); +} +EXPORT_SYMBOL_GPL(pci_rebar_get_max_size); + /** * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device diff --git a/include/linux/pci.h b/include/linux/pci.h index 0ef827cfaf0c..898bc3a4e8e7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1425,6 +1425,7 @@ int pci_rebar_bytes_to_size(u64 bytes); resource_size_t pci_rebar_size_to_bytes(int size); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); +int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, int exclude_bars); =20 --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 204E129B795; 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Ruhl" , Andi Shyti , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 09/11] drm/xe/vram: Use pci_rebar_get_max_size() Date: Thu, 13 Nov 2025 20:00:51 +0200 Message-Id: <20251113180053.27944-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use pci_rebar_get_max_size() from PCI core in resize_vram_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Christian K=C3=B6nig Acked-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_vram.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 57c224fa0b56..524469f8a4bd 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -53,16 +53,11 @@ static void resize_vram_bar(struct xe_device *xe) resource_size_t current_size; resource_size_t rebar_size; struct resource *root_res; - u32 bar_size_mask; + int max_size, i; u32 pci_cmd; - int i; =20 /* gather some relevant info */ current_size =3D pci_resource_len(pdev, LMEM_BAR); - bar_size_mask =3D pci_rebar_get_possible_sizes(pdev, LMEM_BAR); - - if (!bar_size_mask) - return; =20 if (force_vram_bar_size < 0) return; @@ -76,7 +71,8 @@ static void resize_vram_bar(struct xe_device *xe) drm_info(&xe->drm, "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, - bar_size_mask, (u64)current_size >> 20); + pci_rebar_get_possible_sizes(pdev, LMEM_BAR), + (u64)current_size >> 20); return; } =20 @@ -84,7 +80,10 @@ static void resize_vram_bar(struct xe_device *xe) if (rebar_size =3D=3D current_size) return; } else { - rebar_size =3D pci_rebar_size_to_bytes(__fls(bar_size_mask)); + max_size =3D pci_rebar_get_max_size(pdev, LMEM_BAR); + if (max_size < 0) + return; + rebar_size =3D pci_rebar_size_to_bytes(max_size); =20 /* only resize if larger than current */ if (rebar_size <=3D current_size) --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D792627B4F7; Thu, 13 Nov 2025 18:03:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763057001; cv=none; b=T1G1YLOkmbt2JUWEg6pEKJ6aiKMwdxOooXrK6+LkGqhHLInZ79scB//aCv2YAE36tR/o1t3ot4WLcZVFtcGbhKnQm4AS1J2l4It1I1cEEuqJG0lf7A3djmxXLl+ZwRz/fWNPqGc9YC2YnjwXPFApuKJ9ajuL+JzxnzZS0ooLy30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763057001; c=relaxed/simple; bh=e5pHv3WKNR67jU/OKNlgxz1wxiWJXKsANnUH51oNoN4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=RJ6UKv9Va82gbEiUF6mLv8BAJcPXE1bdjDkw/o6z/X6lyGDTJgvIHv+E5JawjWW+mtyhHkZHikeoxxuAdkUvF/6CXbed3o7RreeN9aEJID2Le0APsASHViwTW/pmG+amFQjfDAwjz8Y7NJsHhHTYTCtYysxAFSLs2XbEajHjtt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=n3C5BY2B; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="n3C5BY2B" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763057000; x=1794593000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e5pHv3WKNR67jU/OKNlgxz1wxiWJXKsANnUH51oNoN4=; b=n3C5BY2B9Nt0XJT2oOlh3vZfBJIxx4RVhvfZq182eHFXcsvPzj5L32Zl QOYJzLAlD+BHaP+9/rLioss6nRENkdDazsRliRXfHcUuKj56xKSuIrWZz pZnjiY0C80+ucmgjAGcwErVv4c57G21W86uyoIm5ibCho4M+zS+SYHRrR E8CY7zrd/woHLLphHxuczvFd10Bc07FK1iLQ11a70WFwUUzjt1J6Pgg5G 3M/oMd/77+sE1FXWdmYQAxdM7AHcx/Uqbr8M7r+pAgn5FC36LxhARUh3m x6esLUI7GhitnI2rwdJruNue13W4nu6705xt45mFrp2NLShQaY3COP446 w==; X-CSE-ConnectionGUID: OYxCNlOcR8ukEx1EvxrEaQ== X-CSE-MsgGUID: O9RgHI+LQZykqeH4O6MVwg== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="65186389" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="65186389" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:03:19 -0800 X-CSE-ConnectionGUID: vw5syRMES/e5N/FePsjwlQ== X-CSE-MsgGUID: GX9mxbz3QqCr9ylcbbcFmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="194001333" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.164]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:03:13 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 10/11] drm/amdgpu: Use pci_rebar_get_max_size() Date: Thu, 13 Nov 2025 20:00:52 +0200 Message-Id: <20251113180053.27944-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use pci_rebar_get_max_size() to simplify amdgpu_device_resize_fb_bar(). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index f11a255786d7..da2b6158b65f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1673,9 +1673,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device = *adev) int rbar_size =3D pci_rebar_bytes_to_size(adev->gmc.real_vram_size); struct pci_bus *root; struct resource *res; + int max_size, r; unsigned int i; u16 cmd; - int r; =20 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) return 0; @@ -1721,8 +1721,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device= *adev) return 0; =20 /* Limit the BAR size to what is available */ - rbar_size =3D min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, - rbar_size); + max_size =3D pci_rebar_get_max_size(adev->pdev, 0); + if (max_size < 0) + return 0; + rbar_size =3D min(max_size, rbar_size); =20 /* Disable memory decoding while we change the BAR addresses and size */ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); --=20 2.39.5 From nobody Thu Dec 18 06:17:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C385270ED9; Thu, 13 Nov 2025 18:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763057016; cv=none; b=JklSNQmhygxZJnhIVVD4NZjDVCiEu7lFNT3RT8mwSwVs8kM3SqSiMIGk46aTnRKHME1vW/Ga0UKgoSEQ8XBP9OPVUbX+3tN6j1soZt7Jw0kMrsPI41dQtpaxM4+3sJVjD2dNQcMLbGkvGBu9FV5uW16HWp4gZjsM45XhPChFjcE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763057016; c=relaxed/simple; bh=d+MXZ4DY1vw/qz4xqKxtxsAAGCa9o+jzDmGdXpGbA0I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=O7mgZz2+n7D0dqbNOS/F/R5N7tVPJo1ZBLWOFNQvJ3TqnVK9dWNHKVAOtzTmyHgpJyL6nrq+1FrfdEcMOfAPQ1/ZUKkwzPzY+7H+sALGpHrB2Al0qnogemxFUkLS/zwVie2ukyDlKXCA/sAaFjtrpkFiRBAP0nOrIZO34TcjaxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=X45YUh3w; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="X45YUh3w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763057015; x=1794593015; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d+MXZ4DY1vw/qz4xqKxtxsAAGCa9o+jzDmGdXpGbA0I=; b=X45YUh3wQCUPgQJC29oDCFxEV+xpKBuXoKGpAsTgOoLteAJNIB6aA/Nu tqezzy2IUa1gsIoEVgZlDYGrhpFytm4X8s8uE0yQq8L3Rik+BI2/SLavm N+Uj1n7SidYknUzogBNU64T140pRcrxEFX21ggrWIPkBN3rmp0w6Au9YV r90HB2eFVR79/RLSzIAVehwnrMeWzneWuok81QQCtJmCZz79WUxqCKa78 0m7KYHQWZgBDmrT7ZNbyPi/PCxLVpNfH/MMMJ2dUSOX+MbNvbD+PXwrz+ SteaEgzIPF4buluVBkVSEcz+rbIT3TNL9+oAZwVYGMMTMvwe22PbnOBBI Q==; X-CSE-ConnectionGUID: VjPxJTJpSCa9bPkegCOJJg== X-CSE-MsgGUID: abM4HxsyT5+Pz4Wkoqgy0A== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="65186449" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="65186449" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:03:34 -0800 X-CSE-ConnectionGUID: 4jHij2NnTPunN/MfNXLzSQ== X-CSE-MsgGUID: T9yigM35Qiyv2xnabZItlg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="194001432" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.164]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:03:27 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v4 11/11] PCI: Convert BAR sizes bitmasks to u64 Date: Thu, 13 Nov 2025 20:00:53 +0200 Message-Id: <20251113180053.27944-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> References: <20251113180053.27944-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCIe r7.0, sec 7.8.6, defines resizable BAR sizes beyond the currently supported maximum of 128TB, which will require more than u32 to store the entire bitmask. Convert Resizable BAR related functions to use u64 bitmask for BAR sizes to make the typing more future-proof. The support for the larger BAR sizes themselves is not added at this point. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/xe/xe_vram.c | 2 +- drivers/pci/iov.c | 2 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/rebar.c | 4 ++-- include/linux/pci.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 524469f8a4bd..10f8a73e190b 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -69,7 +69,7 @@ static void resize_vram_bar(struct xe_device *xe) =20 if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) { drm_info(&xe->drm, - "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", + "Requested size: %lluMiB is not supported by rebar sizes: 0x%llx. Lea= ving default: %lluMiB\n", (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, pci_rebar_get_possible_sizes(pdev, LMEM_BAR), (u64)current_size >> 20); diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 71ed85d38508..00784a60ba80 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1367,7 +1367,7 @@ EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) { u64 vf_len =3D pci_resource_len(dev, resno); - u32 sizes; + u64 sizes; =20 if (!num_vfs) return 0; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 2a1b5456c2dc..cb512bf0df7c 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1587,7 +1587,7 @@ static ssize_t __resource_resize_show(struct device *= dev, int n, char *buf) pci_config_pm_runtime_get(pdev); =20 ret =3D sysfs_emit(buf, "%016llx\n", - (u64)pci_rebar_get_possible_sizes(pdev, n)); + pci_rebar_get_possible_sizes(pdev, n)); =20 pci_config_pm_runtime_put(pdev); =20 diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index d85d458c7007..8f7af3053cd8 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -105,7 +105,7 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int= bar) * Return: A bitmask of possible sizes (bit 0=3D1MB, bit 31=3D128TB), or %= 0 if * BAR isn't resizable. */ -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) { int pos; u32 cap; @@ -155,7 +155,7 @@ EXPORT_SYMBOL_GPL(pci_rebar_size_supported); */ int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) { - u32 sizes; + u64 sizes; =20 sizes =3D pci_rebar_get_possible_sizes(pdev, bar); if (!sizes) diff --git a/include/linux/pci.h b/include/linux/pci.h index 898bc3a4e8e7..4b7f4c08b5c7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1423,7 +1423,7 @@ int pci_release_resource(struct pci_dev *dev, int res= no); /* Resizable BAR related routines */ int pci_rebar_bytes_to_size(u64 bytes); resource_size_t pci_rebar_size_to_bytes(int size); -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); +u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, --=20 2.39.5