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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2025 16:09:21.7065 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ee39ade-992d-4c24-8be9-08de22cf01d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4089 Content-Type: text/plain; charset="utf-8" No functional change for now, as we always use entity 0. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 11 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 76 +++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 10 +-- 5 files changed, 66 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gmc.c index 2a444d02cf4b..e73dcfed5338 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -655,7 +655,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, struct amdgpu_vmhub *hub =3D &adev->vmhub[vmhub]; struct dma_fence *fence; struct amdgpu_job *job; - int r; + int r, i; =20 if (!hub->sdma_invalidation_workaround || vmid || !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || @@ -686,8 +686,9 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, * translation. Avoid this by doing the invalidation from the SDMA * itself at least for GART. */ - mutex_lock(&adev->mman.clear_entity.gart_window_lock); mutex_lock(&adev->mman.move_entity.gart_window_lock); + for (i =3D 0; i < adev->mman.num_clear_entities; i++) + mutex_lock(&adev->mman.clear_entities[i].gart_window_lock); r =3D amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.bas= e, AMDGPU_FENCE_OWNER_UNDEFINED, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, @@ -701,7 +702,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, amdgpu_ring_pad_ib(ring, &job->ibs[0]); fence =3D amdgpu_job_submit(job); mutex_unlock(&adev->mman.move_entity.gart_window_lock); - mutex_unlock(&adev->mman.clear_entity.gart_window_lock); + for (i =3D 0; i < adev->mman.num_clear_entities; i++) + mutex_unlock(&adev->mman.clear_entities[i].gart_window_lock); =20 dma_fence_wait(fence, false); dma_fence_put(fence); @@ -710,7 +712,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *ade= v, uint32_t vmid, =20 error_alloc: mutex_unlock(&adev->mman.move_entity.gart_window_lock); - mutex_unlock(&adev->mman.clear_entity.gart_window_lock); + for (i =3D 0; i < adev->mman.num_clear_entities; i++) + mutex_unlock(&adev->mman.clear_entities[i].gart_window_lock); dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); } =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_gtt_mgr.c index 0760e70402ec..3771e89035f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -269,10 +269,12 @@ static const struct ttm_resource_manager_func amdgpu_= gtt_mgr_func =3D { * * @adev: amdgpu_device pointer * @gtt_size: maximum size of GTT + * @reserved_windows: num of already used windows * * Allocate and initialize the GTT manager. */ -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, + u32 reserved_windows) { struct amdgpu_gtt_mgr *mgr =3D &adev->mman.gtt_mgr; struct ttm_resource_manager *man =3D &mgr->manager; @@ -283,7 +285,7 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uin= t64_t gtt_size) =20 ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); =20 - start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; + start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * reserved_windows; size =3D (adev->gmc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c index c06c132a753c..e7b2cae031b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1321,7 +1321,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_objec= t *bo) if (r) goto out; =20 - r =3D amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &bo->base._res= v, + r =3D amdgpu_fill_buffer(&adev->mman.clear_entities[0], abo, 0, &bo->base= ._resv, &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 7193a341689d..2f305ad32080 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1891,6 +1891,7 @@ static void amdgpu_ttm_mmio_remap_bo_fini(struct amdg= pu_device *adev) int amdgpu_ttm_init(struct amdgpu_device *adev) { uint64_t gtt_size; + u32 gart_window; int r; =20 dma_set_max_seg_size(adev->dev, UINT_MAX); @@ -1923,7 +1924,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } =20 /* Change the size here instead of the init above so only lpfn is affecte= d */ - amdgpu_ttm_set_buffer_funcs_status(adev, false); + gart_window =3D amdgpu_ttm_set_buffer_funcs_status(adev, false); #ifdef CONFIG_64BIT #ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) @@ -2019,7 +2020,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } =20 /* Initialize GTT memory pool */ - r =3D amdgpu_gtt_mgr_init(adev, gtt_size); + r =3D amdgpu_gtt_mgr_init(adev, gtt_size, gart_window); if (r) { dev_err(adev->dev, "Failed initializing GTT heap.\n"); return r; @@ -2158,16 +2159,22 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) * * Enable/disable use of buffer functions during suspend/resume. This shou= ld * only be called at bootup or when userspace isn't running. + * + * Returns: the number of GART reserved window */ -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool e= nable) +u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool en= able) { struct ttm_resource_manager *man =3D ttm_manager_type(&adev->mman.bdev, T= TM_PL_VRAM); uint64_t size; - int r, i; + int r, i, j; + u32 num_clear_entities, windows, w; + + num_clear_entities =3D adev->sdma.num_instances; + windows =3D adev->gmc.is_app_apu ? 0 : (2 + num_clear_entities); =20 if (!adev->mman.initialized || amdgpu_in_reset(adev) || adev->mman.buffer_funcs_enabled =3D=3D enable || adev->gmc.is_app_apu) - return; + return windows; =20 if (enable) { struct amdgpu_ring *ring; @@ -2180,19 +2187,9 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) 1, NULL); if (r) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", + "Failed setting up TTM BO eviction entity (%d)\n", r); - return; - } - - r =3D drm_sched_entity_init(&adev->mman.clear_entity.base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { - dev_err(adev->dev, - "Failed setting up TTM BO clear entity (%d)\n", - r); - goto error_free_entity; + return 0; } =20 r =3D drm_sched_entity_init(&adev->mman.move_entity.base, @@ -2202,26 +2199,51 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); goto error_free_entity; } =20 + adev->mman.num_clear_entities =3D num_clear_entities; + adev->mman.clear_entities =3D kcalloc(num_clear_entities, + sizeof(struct amdgpu_ttm_buffer_entity), + GFP_KERNEL); + if (!adev->mman.clear_entities) + goto error_free_entity; + + for (i =3D 0; i < num_clear_entities; i++) { + r =3D drm_sched_entity_init(&adev->mman.clear_entities[i].base, + DRM_SCHED_PRIORITY_NORMAL, &sched, + 1, NULL); + if (r) { + for (j =3D 0; j < i; j++) + drm_sched_entity_destroy( + &adev->mman.clear_entities[j].base); + kfree(adev->mman.clear_entities); + goto error_free_entity; + } + } + /* Statically assign GART windows to each entity. */ + w =3D 0; mutex_init(&adev->mman.default_entity.gart_window_lock); - adev->mman.move_entity.gart_window_id0 =3D 0; - adev->mman.move_entity.gart_window_id1 =3D 1; + adev->mman.move_entity.gart_window_id0 =3D w++; + adev->mman.move_entity.gart_window_id1 =3D w++; mutex_init(&adev->mman.move_entity.gart_window_lock); - /* Clearing entity doesn't use id0 */ - adev->mman.clear_entity.gart_window_id1 =3D 2; - mutex_init(&adev->mman.clear_entity.gart_window_lock); + for (i =3D 0; i < num_clear_entities; i++) { + /* Clearing entities don't use id0 */ + adev->mman.clear_entities[i].gart_window_id1 =3D w++; + mutex_init(&adev->mman.clear_entities[i].gart_window_lock); + } + WARN_ON(w !=3D windows); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); drm_sched_entity_destroy(&adev->mman.move_entity.base); + for (i =3D 0; i < num_clear_entities; i++) + drm_sched_entity_destroy(&adev->mman.clear_entities[i].base); for (i =3D 0; i < TTM_NUM_MOVE_FENCES; i++) { dma_fence_put(man->eviction_fences[i]); man->eviction_fences[i] =3D NULL; } + kfree(adev->mman.clear_entities); } =20 /* this just adjusts TTM size idea, which sets lpfn to the correct value = */ @@ -2232,10 +2254,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) man->size =3D size; adev->mman.buffer_funcs_enabled =3D enable; =20 - return; + return windows; =20 error_free_entity: drm_sched_entity_destroy(&adev->mman.default_entity.base); + return 0; } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, @@ -2388,8 +2411,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, =20 if (!fence) return -EINVAL; - - entity =3D &adev->mman.clear_entity; + entity =3D &adev->mman.clear_entities[0]; *fence =3D dma_fence_get_stub(); =20 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index f4f762be9fdd..797f851a4578 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -39,7 +39,6 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) =20 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 =20 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -73,8 +72,9 @@ struct amdgpu_mman { struct mutex gtt_window_lock; =20 struct amdgpu_ttm_buffer_entity default_entity; /* has no gart windows */ - struct amdgpu_ttm_buffer_entity clear_entity; struct amdgpu_ttm_buffer_entity move_entity; + struct amdgpu_ttm_buffer_entity *clear_entities; + u32 num_clear_entities; =20 struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; @@ -134,7 +134,7 @@ struct amdgpu_copy_mem { #define AMDGPU_COPY_FLAGS_GET(value, field) \ (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAG= S_##field##_MASK) =20 -int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); +int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, u32= reserved_windows); void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); @@ -168,8 +168,8 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, =20 int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, - bool enable); +u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, + bool enable); int amdgpu_copy_buffer(struct amdgpu_ring *ring, struct drm_sched_entity *entity, uint64_t src_offset, --=20 2.43.0