From nobody Sun Feb 8 19:43:20 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5173C33469F; Thu, 13 Nov 2025 08:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024020; cv=none; b=H8jloRtI0SvhZVzFJ4sd7re95EzzcfxX82Qqb1aKCbti3uuDjCgvlocH95cBTndC1fCtxkL+OQj7BwXaxGxH8gzBJ/gX2vihZZRqtB4rbD4x2GxtkDXKLFg9A8R+S3rLCzwTo8jMqSa3n35FQQpL8477liVANkjcVLxKGWAWjbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024020; c=relaxed/simple; bh=tG6vMr2hoVhOuJo5jJ8pdXV4N6JEO7x1fI9tJOFgxrk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=av7ws5EdcrBaf/m4sBrUgLJ+9RjxGUvZcjQ6es49HrDU/jTsy3LxOEKN0k+YFAyqafhBLVm48VQoLyCW4m+VO5tpm82a+84Xm0XZ4yYHbkRRHGD9D+xJJn1DVI3mqjveih854WfLzy09LVq5ROIk6spDTYgd5Aq/5aNXyAgcLLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 13 Nov 2025 16:53:33 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 13 Nov 2025 16:53:33 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH 1/4] dt-bindings: spi: aspeed,ast2600-fmc: Add AST2700 SoC support Date: Thu, 13 Nov 2025 16:53:29 +0800 Message-ID: <20251113085332.89688-2-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> References: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add AST2700 to the list of supported SoCs in the ASPEED FMC/SPI bindings. Signed-off-by: Chin-Ting Kuo Acked-by: Conor Dooley --- Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml = b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml index 57d932af4506..80e542624cc6 100644 --- a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml @@ -12,7 +12,7 @@ maintainers: =20 description: | This binding describes the Aspeed Static Memory Controllers (FMC and - SPI) of the AST2400, AST2500 and AST2600 SOCs. + SPI) of the AST2400, AST2500, AST2600 and AST2700 SOCs. =20 allOf: - $ref: spi-controller.yaml# @@ -20,6 +20,8 @@ allOf: properties: compatible: enum: + - aspeed,ast2700-fmc + - aspeed,ast2700-spi - aspeed,ast2600-fmc - aspeed,ast2600-spi - aspeed,ast2500-fmc --=20 2.34.1 From nobody Sun Feb 8 19:43:20 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 994D1337BB0; Thu, 13 Nov 2025 08:53:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024022; cv=none; b=q477G4RfIX7T0j/iFzUTBrNNzWY5THSYLxcJNj40sjpxaK/9hXLtFDLOl0sykOT5IyhTJLK3Sk1UneCjoKl2jeoPVcOEFBi6X4k3L8ro0EyMIwE7oGS5u5yy2F+cM5Plj8jCxLU4dpTTOhYqVnF0dx0LwMSLdu+K3yk7RbhxwLw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024022; c=relaxed/simple; bh=y0R355uAebCKJwwcxV5wFFdVmXK5xnO/pzj3PYhKo+Y=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K6HgECuu6ai8p0N+kSf/gTTbU5sj8a3YZkuQLt5rIvV1t6eFbKgvvNz4+F0YzImFGOZvhoqeI3v8rrV7inGo0T78Cm8CT+OwE5KYmrs2Fln6wDbtfvav6z5rOuOA7Dj3wOwP4HH64s0Cq+ohvf8tXZFV66kKeCZpDvSXyT+76VU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 13 Nov 2025 16:53:33 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 13 Nov 2025 16:53:33 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH 2/4] spi: aspeed: Enable Quad SPI mode for page program Date: Thu, 13 Nov 2025 16:53:30 +0800 Message-ID: <20251113085332.89688-3-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> References: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ensure the controller switches to quad I/O mode when spi-tx-bus-width dts property is 4 and the Quad SPI program opcode (32h or 34h) is used. Without this change, high-bit data will be lost during page programming. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 179c47ffbfeb..4163632fed8b 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -263,11 +263,15 @@ static ssize_t aspeed_spi_write_user(struct aspeed_sp= i_chip *chip, const struct spi_mem_op *op) { int ret; + int io_mode =3D aspeed_spi_get_io_mode(op); =20 aspeed_spi_start_user(chip); ret =3D aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op-= >cmd.opcode); if (ret < 0) goto stop_user; + + aspeed_spi_set_io_mode(chip, io_mode); + aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes= ); stop_user: aspeed_spi_stop_user(chip); --=20 2.34.1 From nobody Sun Feb 8 19:43:20 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7FA033893A; Thu, 13 Nov 2025 08:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024024; cv=none; b=dlI3dsI0F/qHMMKusKA1mFxtOdzI+kDGblMwJFVkc863VfKJ/zGavSwobvg0jKRmiKWRgeedh5kRDupNm0LSBewnXht6ip2xfRMH381wQEa3/CRVjASPeGCRtTYuaG01nDN/pUnRyQVglw+1wGfJ5cqatS0CtkD+O0vaYZAZMUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024024; c=relaxed/simple; bh=WYasyDutiN9J04g4w7tsx80DcE2lP79ppqoN5EAnPH8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ACZFHVQjz16H1FN0eijIlz4pL66CDn9BNpderoZHbOzeDgIt0n9y89l16gMHp1oscarOo5d5NsvDd7D0SZPuNScRVsU3sGLmJ4IgSd49qoYv4NfRJi9XqdaMfQkou2ooYgMkvxRJl0eH9W/xWUpAE4/+OFfghb5fMRidxBAvbTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 13 Nov 2025 16:53:33 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 13 Nov 2025 16:53:33 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH 3/4] spi: aspeed: Use phys_addr_t for bus addresses to support 64-bit platforms Date: Thu, 13 Nov 2025 16:53:31 +0800 Message-ID: <20251113085332.89688-4-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> References: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update bus address types from u32 to phys_addr_t to support systems with 64-bit memory address space. This change ensures compatibility with upcoming SoCs that extend the system bus beyond 32-bit, while maintaining support for existing platforms. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 4163632fed8b..d1a8bdf6d540 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -82,9 +82,10 @@ struct aspeed_spi_data { u32 hdiv_max; u32 min_window_size; =20 - u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg); - u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg); - u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end); + phys_addr_t (*segment_start)(struct aspeed_spi *aspi, u32 reg); + phys_addr_t (*segment_end)(struct aspeed_spi *aspi, u32 reg); + u32 (*segment_reg)(struct aspeed_spi *aspi, phys_addr_t start, + phys_addr_t end); int (*adjust_window)(struct aspeed_spi *aspi); u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz); int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv, @@ -97,7 +98,7 @@ struct aspeed_spi { const struct aspeed_spi_data *data; =20 void __iomem *regs; - u32 ahb_base_phy; + phys_addr_t ahb_base_phy; u32 ahb_window_size; u32 num_cs; struct device *dev; @@ -484,9 +485,9 @@ static int aspeed_spi_chip_set_default_window(struct as= peed_spi *aspi) /* Assign the minimum window size to each CS */ for (cs =3D 0; cs < aspi->num_cs; cs++) { aspi->chips[cs].ahb_window_size =3D aspi->data->min_window_size; - dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ]", - cs, aspi->ahb_base_phy + aspi->data->min_window_size * cs, - aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1); + dev_dbg(aspi->dev, "CE%d default window [ 0x%.9llx - 0x%.9llx ]", + cs, (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs), + (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1)); } =20 /* Close unused CS */ @@ -930,17 +931,18 @@ static void aspeed_spi_remove(struct platform_device = *pdev) * The address range is encoded with absolute addresses in the overall * mapping window. */ -static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg) +static phys_addr_t aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 r= eg) { return ((reg >> 16) & 0xFF) << 23; } =20 -static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) +static phys_addr_t aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) { return ((reg >> 24) & 0xFF) << 23; } =20 -static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 = end) +static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, + phys_addr_t start, phys_addr_t end) { return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); } @@ -952,16 +954,16 @@ static u32 aspeed_spi_segment_reg(struct aspeed_spi *= aspi, u32 start, u32 end) =20 #define AST2600_SEG_ADDR_MASK 0x0ff00000 =20 -static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi, - u32 reg) +static phys_addr_t aspeed_spi_segment_ast2600_start(struct aspeed_spi *asp= i, + u32 reg) { u32 start_offset =3D (reg << 16) & AST2600_SEG_ADDR_MASK; =20 return aspi->ahb_base_phy + start_offset; } =20 -static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, - u32 reg) +static phys_addr_t aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, + u32 reg) { u32 end_offset =3D reg & AST2600_SEG_ADDR_MASK; =20 @@ -973,7 +975,7 @@ static u32 aspeed_spi_segment_ast2600_end(struct aspeed= _spi *aspi, } =20 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi, - u32 start, u32 end) + phys_addr_t start, phys_addr_t end) { /* disable zero size segments */ if (start =3D=3D end) --=20 2.34.1 From nobody Sun Feb 8 19:43:20 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7C133AD9B; Thu, 13 Nov 2025 08:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763024026; cv=none; b=iUjePX9Noz4b532xOiJlgUOXaWxIu5lZVwuO/028J3da5kYeFvrBe4YbGYPWvLapGLq0FImmyIsHXiDwRezkRwOLJ7Q6QJsi2D/yLX13RY3kHUgPIUGCjPBuYDmzaDP20naF64c9dvkUmaH8hnfZmaW0ntjLsDLG+JJi9kK4J5E= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 13 Nov 2025 16:53:33 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , , , Subject: [PATCH 4/4] spi: aspeed: Add support for the AST2700 SPI controller Date: Thu, 13 Nov 2025 16:53:32 +0800 Message-ID: <20251113085332.89688-5-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> References: <20251113085332.89688-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the driver to support the AST2700 SPI controller. Compared to AST2600, AST2700 has the following characteristics: - A 64-bit memory address space. - A 64KB address decoding unit. - Segment registers now use (start <=3D range < end) semantics, which differs slightly from (start <=3D range <=3D end) in AST2600. - Known issues related to address decoding range registers have been resolved, and the decoding range is now 1GB, which is sufficient. Therefore, the adjust_window callback is no longer required on AST2700 for range adjustment and bug fixes. - The SPI clock divider method and timing calibration logic remain unchanged from AST2600. Signed-off-by: Chin-Ting Kuo --- drivers/spi/spi-aspeed-smc.c | 71 ++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index d1a8bdf6d540..db3e096f2eb0 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -985,6 +985,41 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspee= d_spi *aspi, ((end - 1) & AST2600_SEG_ADDR_MASK); } =20 +/* The Segment Registers of the AST2700 use a 64KB unit. */ +#define AST2700_SEG_ADDR_MASK 0x7fff0000 + +static phys_addr_t aspeed_spi_segment_ast2700_start(struct aspeed_spi *asp= i, + u32 reg) +{ + u64 start_offset =3D (reg << 16) & AST2700_SEG_ADDR_MASK; + + if (!start_offset) + return aspi->ahb_base_phy; + + return aspi->ahb_base_phy + start_offset; +} + +static phys_addr_t aspeed_spi_segment_ast2700_end(struct aspeed_spi *aspi, + u32 reg) +{ + u64 end_offset =3D reg & AST2700_SEG_ADDR_MASK; + + if (!end_offset) + return aspi->ahb_base_phy; + + return aspi->ahb_base_phy + end_offset; +} + +static u32 aspeed_spi_segment_ast2700_reg(struct aspeed_spi *aspi, + phys_addr_t start, phys_addr_t end) +{ + if (start =3D=3D end) + return 0; + + return (u32)(((start & AST2700_SEG_ADDR_MASK) >> 16) | + (end & AST2700_SEG_ADDR_MASK)); +} + /* * Read timing compensation sequences */ @@ -1511,6 +1546,40 @@ static const struct aspeed_spi_data ast2600_spi_data= =3D { .adjust_window =3D aspeed_adjust_window_ast2600, }; =20 +static const struct aspeed_spi_data ast2700_fmc_data =3D { + .max_cs =3D 3, + .hastype =3D false, + .mode_bits =3D SPI_RX_QUAD | SPI_TX_QUAD, + .we0 =3D 16, + .ctl0 =3D CE0_CTRL_REG, + .timing =3D CE0_TIMING_COMPENSATION_REG, + .hclk_mask =3D 0xf0fff0ff, + .hdiv_max =3D 2, + .min_window_size =3D 0x10000, + .get_clk_div =3D aspeed_get_clk_div_ast2600, + .calibrate =3D aspeed_spi_ast2600_calibrate, + .segment_start =3D aspeed_spi_segment_ast2700_start, + .segment_end =3D aspeed_spi_segment_ast2700_end, + .segment_reg =3D aspeed_spi_segment_ast2700_reg, +}; + +static const struct aspeed_spi_data ast2700_spi_data =3D { + .max_cs =3D 2, + .hastype =3D false, + .mode_bits =3D SPI_RX_QUAD | SPI_TX_QUAD, + .we0 =3D 16, + .ctl0 =3D CE0_CTRL_REG, + .timing =3D CE0_TIMING_COMPENSATION_REG, + .hclk_mask =3D 0xf0fff0ff, + .hdiv_max =3D 2, + .min_window_size =3D 0x10000, + .get_clk_div =3D aspeed_get_clk_div_ast2600, + .calibrate =3D aspeed_spi_ast2600_calibrate, + .segment_start =3D aspeed_spi_segment_ast2700_start, + .segment_end =3D aspeed_spi_segment_ast2700_end, + .segment_reg =3D aspeed_spi_segment_ast2700_reg, +}; + static const struct of_device_id aspeed_spi_matches[] =3D { { .compatible =3D "aspeed,ast2400-fmc", .data =3D &ast2400_fmc_data }, { .compatible =3D "aspeed,ast2400-spi", .data =3D &ast2400_spi_data }, @@ -1518,6 +1587,8 @@ static const struct of_device_id aspeed_spi_matches[]= =3D { { .compatible =3D "aspeed,ast2500-spi", .data =3D &ast2500_spi_data }, { .compatible =3D "aspeed,ast2600-fmc", .data =3D &ast2600_fmc_data }, { .compatible =3D "aspeed,ast2600-spi", .data =3D &ast2600_spi_data }, + { .compatible =3D "aspeed,ast2700-fmc", .data =3D &ast2700_fmc_data }, + { .compatible =3D "aspeed,ast2700-spi", .data =3D &ast2700_spi_data }, { } }; MODULE_DEVICE_TABLE(of, aspeed_spi_matches); --=20 2.34.1