From nobody Tue Dec 9 03:20:18 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C9A0D274B23 for ; Thu, 13 Nov 2025 03:49:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763005771; cv=none; b=XR07eAGMxIX0Re5su5IXH/45Va213yDwRQSMAsWRxlleCyIisdRi65HkE/T1UXy9AJ7xCQ/tuRqqDa4psoEerL6TpYy4itsdc8Sghfm/w08TRSGh3Kb/62WSHMSb7f/Y+MVxvjO8lnrGc2hHEf+g3iOSzvj5meemX4eZkwrlpyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763005771; c=relaxed/simple; bh=t3Cd7hg2hGbCtGJ9jeKcQ1i/dz5mbmLQ3jxvFDoyah4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Dtvy96EmidM0RIw4LY93z6gRgFu0FD7EO/DrM2aFUt8lXaGyPMGli3KObuvd02zy2nyg0UGrEEUbj8SGUClGHeu6Tfge+Igx4tKQpKDeR+N6/npYmYZOOkaMJsD7w12AqbxvK5TYqUti3+Cgy4NMkFIMNu9G1HooR/q9s2KqG9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.40.46.139]) by gateway (Coremail) with SMTP id _____8DxLvBHVRVp4rciAA--.9716S3; Thu, 13 Nov 2025 11:49:27 +0800 (CST) Received: from localhost.localdomain (unknown [10.40.46.139]) by front1 (Coremail) with SMTP id qMiowJCxM+REVRVpyDkxAQ--.9432S3; Thu, 13 Nov 2025 11:49:25 +0800 (CST) From: Tianyang Zhang To: chenhuacai@kernel.org, kernel@xen0n.name, akpm@linux-foundation.org, willy@infradead.org, david@redhat.com, linmag7@gmail.com, thuth@redhat.com, maobibo@loongson.cn, apopple@nvidia.com Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Tianyang Zhang Subject: [PATCH v6 1/2] Docs/LoongArch: Add Advanced Extended-Redirect IRQ model description Date: Thu, 13 Nov 2025 11:49:19 +0800 Message-ID: <20251113034923.9699-2-zhangtianyang@loongson.cn> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20251113034923.9699-1-zhangtianyang@loongson.cn> References: <20251113034923.9699-1-zhangtianyang@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+REVRVpyDkxAQ--.9432S3 X-CM-SenderInfo: x2kd0wxwld05hdqjqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoWxAryfuw1rKw1kKFyUuw45Jwc_yoWrXr4fpr Z3GryxXF18Jry5Xr17Jr4UXr13Gwn3Ja1DtF1xKry8Xr4kAr1ktr1UJrykJFy7G34rAr1U XFWrJw4UJr1UJwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUB0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1ln4kS14v26r126r1DM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2 x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5 McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr4 1lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_ Gr1l4IxYO2xFxVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67 AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8I cVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI 8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v2 6r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU4eMKDUUUU Introduce the redirect interrupt controllers.When the redirect interrupt controller is enabled, the routing target of MSI interrupts is no longer a specific CPU and vector number, but a specific redirect entry. The actual CPU and vector number used are described by the redirect entry. Signed-off-by: Tianyang Zhang --- .../arch/loongarch/irq-chip-model.rst | 38 +++++++++++++++++++ .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 ++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentatio= n/arch/loongarch/irq-chip-model.rst index a7ecce11e445..d9a2e8d7f70e 100644 --- a/Documentation/arch/loongarch/irq-chip-model.rst +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -181,6 +181,44 @@ go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and the= n go to CPUINTC directly:: | Devices | +---------+ =20 +Advanced Extended IRQ model (with redirection) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interru= pt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupt= s go +to REDIRECT for remapping it to AVEC, and then go to CPUINTC directly, whi= le all +other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, an= d then +go to CPUINTC directly:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + +---------+ +----------+ +---------+ +-------+ + | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + +---------+ +----------+ +---------+ +-------+ + ^ ^ + | | + | +----------+ + | | REDIRECT | + | +----------+ + | ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI-related definitions =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model= .rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst index d4ff80de47b6..7e4e3e55c7ad 100644 --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst @@ -174,6 +174,43 @@ CPU=E4=B8=B2=E5=8F=A3=EF=BC=88UARTs=EF=BC=89=E4=B8=AD= =E6=96=AD=E5=8F=91=E9=80=81=E5=88=B0LIOINTC=EF=BC=8CPCH-MSI=E4=B8=AD=E6=96= =AD=E5=8F=91=E9=80=81=E5=88=B0AVECINTC=EF=BC=8C | Devices | +---------+ =20 +=E9=AB=98=E7=BA=A7=E6=89=A9=E5=B1=95IRQ=E6=A8=A1=E5=9E=8B (=E5=B8=A6=E9=87= =8D=E5=AE=9A=E5=90=91) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +=E5=9C=A8=E8=BF=99=E7=A7=8D=E6=A8=A1=E5=9E=8B=E9=87=8C=E9=9D=A2=EF=BC=8CIP= I=EF=BC=88Inter-Processor Interrupt=EF=BC=89=E5=92=8CCPU=E6=9C=AC=E5=9C=B0= =E6=97=B6=E9=92=9F=E4=B8=AD=E6=96=AD=E7=9B=B4=E6=8E=A5=E5=8F=91=E9=80=81=E5= =88=B0CPUINTC=EF=BC=8C +CPU=E4=B8=B2=E5=8F=A3=EF=BC=88UARTs=EF=BC=89=E4=B8=AD=E6=96=AD=E5=8F=91=E9= =80=81=E5=88=B0LIOINTC=EF=BC=8CPCH-MSI=E4=B8=AD=E6=96=AD=E9=A6=96=E5=85=88= =E5=8F=91=E9=80=81=E5=88=B0REDIRECT=E6=A8=A1=E5=9D=97,=E5=AE=8C=E6=88=90=E9= =87=8D=E5=AE=9A=E5=90=91=E5=90=8E=E5=8F=91 +=E9=80=81=E5=88=B0AVECINTC=EF=BC=8C=E8=80=8C=E5=90=8E=E9=80=9A=E8=BF=87AVE= CINTC=E7=9B=B4=E6=8E=A5=E9=80=81=E8=BE=BECPUINTC=EF=BC=8C=E8=80=8C=E5=85=B6= =E4=BB=96=E6=89=80=E6=9C=89=E8=AE=BE=E5=A4=87=E7=9A=84=E4=B8=AD=E6=96=AD=E5= =88=99=E5=88=86=E5=88=AB=E5=8F=91=E9=80=81=E5=88=B0=E6=89=80=E8=BF=9E +=E6=8E=A5=E7=9A=84PCH-PIC/PCH-LPC=EF=BC=8C=E7=84=B6=E5=90=8E=E7=94=B1EIOIN= TC=E7=BB=9F=E4=B8=80=E6=94=B6=E9=9B=86=EF=BC=8C=E5=86=8D=E7=9B=B4=E6=8E=A5= =E5=88=B0=E8=BE=BECPUINTC:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + +---------+ +----------+ +---------+ +-------+ + | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + +---------+ +----------+ +---------+ +-------+ + ^ ^ + | | + | +----------+ + | | REDIRECT | + | +----------+ + | ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI=E7=9B=B8=E5=85=B3=E7=9A=84=E5=AE=9A=E4=B9=89 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 --=20 2.41.0 From nobody Tue Dec 9 03:20:18 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2C107286410 for ; Thu, 13 Nov 2025 03:49:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763005774; cv=none; b=mCJ3q9qjf02QYjEK2dHLX43fvaUzH/DCa5yD0EVa1GipNQoguzhgSUef700Q1y6tl3xsDP3h/yWn4wv30ieOJ/UzCS3z7Rl2TksBvL41a2jJPTJnxoCL8dX3+vUQPYm4dkYX2LDT+x+KIoP+C07UoP+KO/v4cvomkO2OhQcM4t4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763005774; c=relaxed/simple; bh=QsvVOyul1L12LM6uwtS1uVcw/aVtcur5P3tlS5T0MgE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q9Hcp9t4vTLyTiLJfls005+ZW8TBXhFhtYuZ8z/mPpcCvRpu5T4gGnsRbdXjIZkU2Qp9MJYXEzoU3qCcLR58Fj4ERsHtbvb1eZLUKuTcz6ZV7Lw3Goj/+c/gcZvgqfRovSOvNwsku1WVYzFReGFqL1S3K5niallsj53BlaDOiqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.40.46.139]) by gateway (Coremail) with SMTP id _____8Bx3tJIVRVp67ciAA--.9580S3; Thu, 13 Nov 2025 11:49:28 +0800 (CST) Received: from localhost.localdomain (unknown [10.40.46.139]) by front1 (Coremail) with SMTP id qMiowJCxM+REVRVpyDkxAQ--.9432S4; Thu, 13 Nov 2025 11:49:27 +0800 (CST) From: Tianyang Zhang To: chenhuacai@kernel.org, kernel@xen0n.name, akpm@linux-foundation.org, willy@infradead.org, david@redhat.com, linmag7@gmail.com, thuth@redhat.com, maobibo@loongson.cn, apopple@nvidia.com Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Tianyang Zhang , Liupu Wang Subject: [PATCH v6 2/2] irqchip/irq-loongarch-ir:Add Redirect irqchip support Date: Thu, 13 Nov 2025 11:49:20 +0800 Message-ID: <20251113034923.9699-3-zhangtianyang@loongson.cn> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20251113034923.9699-1-zhangtianyang@loongson.cn> References: <20251113034923.9699-1-zhangtianyang@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+REVRVpyDkxAQ--.9432S4 X-CM-SenderInfo: x2kd0wxwld05hdqjqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj9fXoWfWr1xWFW3Aw1DWw4ruryrKrX_yoW8trW3Wo WfJFs3G34rWr18CrWFkw47tFyxZ3yrGw4Fy34fuFs7Z3ZFvrWrKrW7G3yavFy2gF10qFnr AayIqrn5Jayxtrn3l-sFpf9Il3svdjkaLaAFLSUrUUUUnb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYX7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUtVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_JF0_Jw1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0c Ia020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_ WrylYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwI xGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwCFI7km07C267AKxVWUAVWUtwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07UAKsUUUUUU= Content-Type: text/plain; charset="utf-8" The main function of the Redirected interrupt controller is to manage the redirected-interrupt table, which consists of many redirected entries. When MSI interrupts are requested, the driver creates a corresponding redirected entry that describes the target CPU/vector number and the operating mode of the interrupt. The redirected interrupt module has an independent cache, and during the interrupt routing process, it will prioritize the redirected entries that hit the cache. The driver invalidates certain entry caches via a command queue. Co-developed-by: Liupu Wang Signed-off-by: Liupu Wang Signed-off-by: Tianyang Zhang --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 + arch/loongarch/include/asm/loongarch.h | 6 + arch/loongarch/kernel/cpu-probe.c | 2 + drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-loongarch-avec.c | 20 +- drivers/irqchip/irq-loongarch-ir.c | 527 ++++++++++++++++++++++ drivers/irqchip/irq-loongson.h | 19 + 8 files changed, 565 insertions(+), 14 deletions(-) create mode 100644 drivers/irqchip/irq-loongarch-ir.c diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index fc83bb32f9f0..03f7e93e81e0 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -68,5 +68,6 @@ #define cpu_has_ptw cpu_opt(LOONGARCH_CPU_PTW) #define cpu_has_lspw cpu_opt(LOONGARCH_CPU_LSPW) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) +#define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index dfb982fe8701..27b9cfbfbaa8 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -102,6 +102,7 @@ enum cpu_type_enum { #define CPU_FEATURE_PTW 27 /* CPU has hardware page table walker */ #define CPU_FEATURE_LSPW 28 /* CPU has LSPW (lddir/ldpte instructions) */ #define CPU_FEATURE_AVECINT 29 /* CPU has AVEC interrupt */ +#define CPU_FEATURE_REDIRECTINT 30 /* CPU has interrupt remmap */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -133,5 +134,6 @@ enum cpu_type_enum { #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW) #define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) +#define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 09dfd7eb406e..2cb4b407fbff 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -1137,6 +1137,7 @@ #define IOCSRF_FLATMODE BIT_ULL(10) #define IOCSRF_VM BIT_ULL(11) #define IOCSRF_AVEC BIT_ULL(15) +#define IOCSRF_REDIRECTINT BIT_ULL(16) =20 #define LOONGARCH_IOCSR_VENDOR 0x10 =20 @@ -1196,6 +1197,11 @@ =20 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0 +#define LOONGARCH_IOCSR_REDIRECT_CFG 0x15e0 +#define LOONGARCH_IOCSR_REDIRECT_TBR 0x15e8 /* IRT BASE REG*/ +#define LOONGARCH_IOCSR_REDIRECT_CQB 0x15f0 /* IRT CACHE QUEUE BASE */ +#define LOONGARCH_IOCSR_REDIRECT_CQH 0x15f8 /* IRT CACHE QUEUE HEAD, 32b= it */ +#define LOONGARCH_IOCSR_REDIRECT_CQT 0x15fc /* IRT CACHE QUEUE TAIL, 32b= it */ #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800 diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index fedaa67cde41..543474fd1399 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -289,6 +289,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_lo= ongarch *c, unsigned int c->options |=3D LOONGARCH_CPU_EIODECODE; if (config & IOCSRF_AVEC) c->options |=3D LOONGARCH_CPU_AVECINT; + if (config & IOCSRF_REDIRECTINT) + c->options |=3D LOONGARCH_CPU_REDIRECTINT; if (config & IOCSRF_VM) c->options |=3D LOONGARCH_CPU_HYPERVISOR; } diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 93e3ced023bb..a0be18891890 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -118,7 +118,7 @@ obj-$(CONFIG_LS1X_IRQ) +=3D irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) +=3D irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) +=3D irq-ti-sci-inta.o obj-$(CONFIG_TI_PRUSS_INTC) +=3D irq-pruss-intc.o -obj-$(CONFIG_IRQ_LOONGARCH_CPU) +=3D irq-loongarch-cpu.o irq-loongarch-av= ec.o +obj-$(CONFIG_IRQ_LOONGARCH_CPU) +=3D irq-loongarch-cpu.o irq-loongarch-av= ec.o irq-loongarch-ir.o obj-$(CONFIG_LOONGSON_LIOINTC) +=3D irq-loongson-liointc.o obj-$(CONFIG_LOONGSON_EIOINTC) +=3D irq-loongson-eiointc.o obj-$(CONFIG_LOONGSON_HTPIC) +=3D irq-loongson-htpic.o diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loo= ngarch-avec.c index bf52dc8345f5..de7b6059c1b6 100644 --- a/drivers/irqchip/irq-loongarch-avec.c +++ b/drivers/irqchip/irq-loongarch-avec.c @@ -24,7 +24,6 @@ #define VECTORS_PER_REG 64 #define IRR_VECTOR_MASK 0xffUL #define IRR_INVALID_MASK 0x80000000UL -#define AVEC_MSG_OFFSET 0x100000 =20 #ifdef CONFIG_SMP struct pending_list { @@ -47,15 +46,6 @@ struct avecintc_chip { =20 static struct avecintc_chip loongarch_avec; =20 -struct avecintc_data { - struct list_head entry; - unsigned int cpu; - unsigned int vec; - unsigned int prev_cpu; - unsigned int prev_vec; - unsigned int moving; -}; - static inline void avecintc_enable(void) { u64 value; @@ -85,7 +75,7 @@ static inline void pending_list_init(int cpu) INIT_LIST_HEAD(&plist->head); } =20 -static void avecintc_sync(struct avecintc_data *adata) +void avecintc_sync(struct avecintc_data *adata) { struct pending_list *plist; =20 @@ -109,7 +99,7 @@ static int avecintc_set_affinity(struct irq_data *data, = const struct cpumask *de return -EBUSY; =20 if (cpu_online(adata->cpu) && cpumask_test_cpu(adata->cpu, dest)) - return 0; + return IRQ_SET_MASK_OK_DONE; =20 cpumask_and(&intersect_mask, dest, cpu_online_mask); =20 @@ -121,7 +111,8 @@ static int avecintc_set_affinity(struct irq_data *data,= const struct cpumask *de adata->cpu =3D cpu; adata->vec =3D vector; per_cpu_ptr(irq_map, adata->cpu)[adata->vec] =3D irq_data_to_desc(data); - avecintc_sync(adata); + if (!cpu_has_redirectint) + avecintc_sync(adata); } =20 irq_data_update_effective_affinity(data, cpumask_of(cpu)); @@ -412,6 +403,9 @@ static int __init pch_msi_parse_madt(union acpi_subtabl= e_headers *header, =20 static inline int __init acpi_cascade_irqdomain_init(void) { + if (cpu_has_redirectint) + return redirect_acpi_init(loongarch_avec.domain); + return acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, = 1); } =20 diff --git a/drivers/irqchip/irq-loongarch-ir.c b/drivers/irqchip/irq-loong= arch-ir.c new file mode 100644 index 000000000000..988f06cd9c76 --- /dev/null +++ b/drivers/irqchip/irq-loongarch-ir.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Loongson Technologies, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "irq-loongson.h" + +#define IRD_ENTRY_SIZE 16 +#define IRD_ENTRIES 65536 +#define IRD_TABLE_PAGE_ORDER get_order(IRD_ENTRIES * IRD_ENTRY_SIZE) + +#define INVALID_QUEUE_SIZE 4096 +#define INV_QUEUE_PAGE_ORDER get_order(INVALID_QUEUE_SIZE * IRD_ENTRY_SIZ= E) + +#define GPID_ADDR_MASK GENMASK(47, 6) +#define GPID_ADDR_SHIFT 6 + +#define CQB_SIZE_MASK 0xf +#define CQB_ADDR_MASK GENMASK(47, 12) + +#define CFG_DISABLE_IDLE 2 +#define INVALID_INDEX 0 + +#define MAX_IR_ENGINES 16 + +struct redirect_entry { + struct { + u64 valid : 1, + res1 : 5, + gpid : 42, + res2 : 8, + vector : 8; + } lo; + u64 hi; +}; + +struct redirect_gpid { + u64 pir[4]; // Pending interrupt requested + u8 en : 1, // doorbell + res0 : 7; + u8 irqnum; + u16 res1; + u32 dst; + u32 rsvd[6]; +}; + +struct irde_inv_cmd { + union { + u64 cmd_info; + struct { + u64 res1 : 4, + type : 1, + need_notice : 1, + pad : 2, + index : 16, + pad2 : 40; + } index; + }; + u64 notice_addr; +}; + +struct redirect_table { + struct redirect_entry *table; + unsigned long *bitmap; + raw_spinlock_t lock; +}; + +struct redirect_queue { + struct irde_inv_cmd *cmd_base; + int head; + int tail; + raw_spinlock_t lock; +}; + +struct irde_desc { + struct redirect_table ird_table; + struct redirect_queue inv_queue; + int node; +}; + +struct redirect_item { + int index; + struct irde_desc *irde; + struct redirect_gpid *gpid; +}; + + +static struct irq_domain *redirect_domain; +static struct irde_desc irde_descs[MAX_IR_ENGINES]; +static phys_addr_t msi_base_addr; +static phys_addr_t redirect_reg_base =3D LOONGSON_REG_BASE; + +#define REDIRECT_REG(reg, node) \ + ((void __iomem *)(IO_BASE | redirect_reg_base | (u64)(node) << NODE_ADDRS= PACE_SHIFT | (reg))) + +static inline void redirect_write_reg64(u32 node, u64 val, u32 reg) +{ + void __iomem *reg_addr =3D REDIRECT_REG(reg, node); + + return writeq(val, reg_addr); +} + +static inline void redirect_write_reg32(int node, u32 val, u32 reg) +{ + void __iomem *reg_addr =3D REDIRECT_REG(reg, node); + + return writel(val, reg_addr); +} + +static inline u32 redirect_read_reg32(int node, int reg) +{ + void __iomem *reg_addr =3D REDIRECT_REG(reg, node); + + return readl(reg_addr); +} + +static inline struct redirect_entry *item_get_entry(struct redirect_item *= item) +{ + return item->irde->ird_table.table + item->index; +} + +static inline bool invalid_queue_is_full(int node, u32 *tail) +{ + u32 head =3D redirect_read_reg32(node, LOONGARCH_IOCSR_REDIRECT_CQH); + + *tail =3D redirect_read_reg32(node, LOONGARCH_IOCSR_REDIRECT_CQT); + + return head =3D=3D ((*tail + 1) % INVALID_QUEUE_SIZE); +} + +static void invalid_enqueue(struct redirect_item *item, struct irde_inv_cm= d *cmd) +{ + struct redirect_queue *inv_queue =3D &item->irde->inv_queue; + u32 tail; + + guard(raw_spinlock_irqsave)(&inv_queue->lock); + + while (invalid_queue_is_full(item->irde->node, &tail)) + cpu_relax(); + + memcpy(&inv_queue->cmd_base[tail], cmd, sizeof(*cmd)); + + redirect_write_reg32(item->irde->node, (tail + 1) % INVALID_QUEUE_SIZE, + LOONGARCH_IOCSR_REDIRECT_CQT); +} + +static void irde_invalid_entry_node(struct redirect_item *item) +{ + struct irde_inv_cmd cmd; + u64 raddr =3D 0; + + cmd.cmd_info =3D 0; + cmd.index.type =3D INVALID_INDEX; + cmd.index.need_notice =3D 1; + cmd.index.index =3D item->index; + cmd.notice_addr =3D (u64)(__pa(&raddr)); + + invalid_enqueue(item, &cmd); + + while (!raddr) + cpu_relax(); + +} + +static inline struct avecintc_data *irq_data_get_avec_data(struct irq_data= *data) +{ + return data->parent_data->chip_data; +} + +static int redirect_table_alloc(struct redirect_item *item) +{ + struct redirect_table *ird_table =3D &item->irde->ird_table; + int index; + + guard(raw_spinlock_irqsave)(&ird_table->lock); + + index =3D find_first_zero_bit(ird_table->bitmap, IRD_ENTRIES); + if (index > IRD_ENTRIES) { + pr_err("No redirect entry to use\n"); + return -ENOMEM; + } + + __set_bit(index, ird_table->bitmap); + + item->index =3D index; + + return 0; +} + +static void redirect_table_free(struct redirect_item *item) +{ + struct redirect_table *ird_table =3D &item->irde->ird_table; + struct redirect_entry *entry =3D item_get_entry(item); + + memset(entry, 0, sizeof(*entry)); + + scoped_guard(raw_spinlock_irq, &ird_table->lock) + bitmap_release_region(ird_table->bitmap, item->index, 0); + + kfree(item->gpid); + + irde_invalid_entry_node(item); +} + +static inline void redirect_domain_prepare_entry(struct redirect_item *ite= m, + struct avecintc_data *adata) +{ + struct redirect_entry *entry =3D item_get_entry(item); + + item->gpid->en =3D 1; + item->gpid->irqnum =3D adata->vec; + item->gpid->dst =3D adata->cpu; + + entry->lo.valid =3D 1; + entry->lo.gpid =3D ((u64)item->gpid & GPID_ADDR_MASK) >> GPID_ADDR_SHIFT; + entry->lo.vector =3D 0xff; +} + +static int redirect_set_affinity(struct irq_data *data, const struct cpuma= sk *dest, bool force) +{ + struct redirect_item *item =3D data->chip_data; + int ret; + + ret =3D irq_chip_set_affinity_parent(data, dest, force); + if (ret =3D=3D IRQ_SET_MASK_OK_DONE) { + return ret; + } else if (ret) { + pr_err("IRDE:set_affinity error %d\n", ret); + return ret; + } else { + struct avecintc_data *adata =3D irq_data_get_avec_data(data); + + redirect_domain_prepare_entry(item, adata); + irde_invalid_entry_node(item); + avecintc_sync(adata); + } + + return IRQ_SET_MASK_OK; +} + +static void redirect_compose_msi_msg(struct irq_data *d, struct msi_msg *m= sg) +{ + struct redirect_item *item =3D irq_data_get_irq_chip_data(d); + + msg->address_lo =3D (msi_base_addr | 1 << 2 | ((item->index & 0xffff) << = 4)); + msg->address_hi =3D 0x0; + msg->data =3D 0x0; +} + +static struct irq_chip loongarch_redirect_chip =3D { + .name =3D "REDIRECT", + .irq_ack =3D irq_chip_ack_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_affinity =3D redirect_set_affinity, + .irq_compose_msi_msg =3D redirect_compose_msi_msg, +}; + +static void redirect_free_resources(struct irq_domain *domain, unsigned in= t virq, + unsigned int nr_irqs) +{ + for (int i =3D 0; i < nr_irqs; i++) { + struct irq_data *irq_data =3D irq_domain_get_irq_data(domain, virq + i); + + if (irq_data && irq_data->chip_data) { + struct redirect_item *item =3D irq_data->chip_data; + + redirect_table_free(item); + kfree(item); + } + } +} + +static int redirect_domain_alloc(struct irq_domain *domain, unsigned int v= irq, + unsigned int nr_irqs, void *arg) +{ + msi_alloc_info_t *info =3D arg; + int ret, i, node; + + node =3D dev_to_node(info->desc->dev); + + ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); + if (ret < 0) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + struct irq_data *irq_data =3D irq_domain_get_irq_data(domain, virq + i); + struct redirect_item *item; + + item =3D kzalloc(sizeof(*item), GFP_KERNEL); + if (!item) { + pr_err("Alloc redirect descriptor failed\n"); + goto out_free_resources; + } + item->irde =3D &irde_descs[node]; + + ret =3D redirect_table_alloc(item); + if (ret) { + pr_err("Alloc redirect table entry failed\n"); + goto out_free_resources; + } + /* + * Only bits 47:6 of the GPID are passed to the controller, + * 64-byte alignment must be guaranteed. + */ + BUILD_BUG_ON(sizeof(*item->gpid) !=3D 64); + item->gpid =3D kzalloc_node(sizeof(*item->gpid), GFP_KERNEL, node); + if (!item->gpid) { + pr_err("Alloc redirect GPID failed\n"); + goto out_free_resources; + } + + irq_data->chip_data =3D item; + irq_data->chip =3D &loongarch_redirect_chip; + + redirect_domain_prepare_entry(item, irq_data_get_avec_data(irq_data)); + } + return 0; + +out_free_resources: + redirect_free_resources(domain, virq, nr_irqs); + irq_domain_free_irqs_common(domain, virq, nr_irqs); + + return -ENOMEM; +} + +static void redirect_domain_free(struct irq_domain *domain, unsigned int v= irq, unsigned int nr_irqs) +{ + redirect_free_resources(domain, virq, nr_irqs); + return irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops redirect_domain_ops =3D { + .alloc =3D redirect_domain_alloc, + .free =3D redirect_domain_free, + .select =3D msi_lib_irq_domain_select, +}; + +static int redirect_queue_init(struct irde_desc *irde) +{ + struct redirect_queue *inv_queue =3D &irde->inv_queue; + struct folio *folio; + + folio =3D __folio_alloc_node(GFP_KERNEL | __GFP_ZERO, INV_QUEUE_PAGE_ORDE= R, irde->node); + if (!folio) { + pr_err("Node [%d] invalid queue alloc pages failed!\n", irde->node); + return -ENOMEM; + } + + inv_queue->cmd_base =3D folio_address(folio); + inv_queue->head =3D 0; + inv_queue->tail =3D 0; + raw_spin_lock_init(&inv_queue->lock); + + return 0; +} + +static int redirect_table_init(struct irde_desc *irde) +{ + struct redirect_table *ird_table =3D &irde->ird_table; + struct folio *folio; + unsigned long *bitmap; + int node =3D irde->node; + + folio =3D __folio_alloc_node(GFP_KERNEL | __GFP_ZERO, IRD_TABLE_PAGE_ORDE= R, node); + if (!folio) { + pr_err("Node [%d] redirect table alloc pages failed!\n", node); + goto fail; + } + ird_table->table =3D folio_address(folio); + + bitmap =3D bitmap_zalloc(IRD_ENTRIES, GFP_KERNEL); + if (!bitmap) { + pr_err("Node [%d] redirect table bitmap alloc pages failed!\n", node); + goto free_pages; + } + + ird_table->bitmap =3D bitmap; + + raw_spin_lock_init(&ird_table->lock); + + return 0; + +free_pages: + folio_put(folio); + ird_table->table =3D NULL; +fail: + return -ENOMEM; +} + +static void redirect_irde_cfg(struct irde_desc *irde) +{ + redirect_write_reg64(irde->node, CFG_DISABLE_IDLE, LOONGARCH_IOCSR_REDIRE= CT_CFG); + redirect_write_reg64(irde->node, __pa(irde->ird_table.table), LOONGARCH_I= OCSR_REDIRECT_TBR); + redirect_write_reg32(irde->node, 0, LOONGARCH_IOCSR_REDIRECT_CQH); + redirect_write_reg32(irde->node, 0, LOONGARCH_IOCSR_REDIRECT_CQT); + redirect_write_reg64(irde->node, ((u64)irde->inv_queue.cmd_base & CQB_ADD= R_MASK) | + CQB_SIZE_MASK, LOONGARCH_IOCSR_REDIRECT_CQB); +} + +static void __redirect_irde_fini(struct irde_desc *irde) +{ + struct redirect_table *ird_table =3D &irde_descs->ird_table; + struct redirect_queue *inv_queue =3D &irde_descs->inv_queue; + + if (ird_table->table) { + folio_put(virt_to_folio(ird_table->table)); + ird_table->table =3D NULL; + } + + if (ird_table->bitmap) { + bitmap_free(ird_table->bitmap); + ird_table->bitmap =3D NULL; + } + + if (inv_queue->cmd_base) { + folio_put(virt_to_folio(inv_queue->cmd_base)); + inv_queue->cmd_base =3D NULL; + } +} + +static inline void redirect_irde_fini(int node) +{ + __redirect_irde_fini(&irde_descs[node]); +} + +static int redirect_irde_init(int node) +{ + struct irde_desc *irde =3D &irde_descs[node]; + int ret; + + irde->node =3D node; + + ret =3D redirect_table_init(irde); + if (ret) + goto fail; + + ret =3D redirect_queue_init(irde); + if (ret) + goto fail_clear; + + redirect_irde_cfg(irde); + + return 0; + +fail_clear: + __redirect_irde_fini(irde); +fail: + return ret; +} + +#ifdef CONFIG_ACPI +static int __init pch_msi_parse_madt(union acpi_subtable_headers *header, = const unsigned long end) +{ + struct acpi_madt_msi_pic *pchmsi_entry =3D (struct acpi_madt_msi_pic *)he= ader; + + msi_base_addr =3D pchmsi_entry->msg_address - AVEC_MSG_OFFSET; + + return pch_msi_acpi_init_avec(redirect_domain); +} + +static int __init acpi_cascade_irqdomain_init(void) +{ + return acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, = 1); +} + +int __init redirect_acpi_init(struct irq_domain *parent) +{ + struct fwnode_handle *fwnode; + int ret =3D -EINVAL, node; + + fwnode =3D irq_domain_alloc_named_fwnode("redirect"); + if (!fwnode) { + pr_err("Unable to alloc redirect domain handle\n"); + goto fail; + } + + redirect_domain =3D irq_domain_create_hierarchy(parent, 0, IRD_ENTRIES, f= wnode, + &redirect_domain_ops, irde_descs); + if (!redirect_domain) { + pr_err("Unable to alloc redirect domain\n"); + goto out_free_fwnode; + } + + + for_each_node_mask(node, node_possible_map) { + ret =3D redirect_irde_init(node); + if (ret) + goto out_clear_irde; + } + + ret =3D acpi_cascade_irqdomain_init(); + if (ret < 0) + pr_err("Failed to cascade IRQ domain, ret=3D%d\n", ret); + + pr_info("loongarch irq redirect modules init succeeded\n"); + return 0; + +out_clear_irde: + for_each_node_mask(node, node_possible_map) + redirect_irde_fini(node); + + irq_domain_remove(redirect_domain); +out_free_fwnode: + irq_domain_free_fwnode(fwnode); +fail: + return ret; +} +#endif diff --git a/drivers/irqchip/irq-loongson.h b/drivers/irqchip/irq-loongson.h index 11fa138d1f44..1f11d799bf0a 100644 --- a/drivers/irqchip/irq-loongson.h +++ b/drivers/irqchip/irq-loongson.h @@ -6,6 +6,17 @@ #ifndef _DRIVERS_IRQCHIP_IRQ_LOONGSON_H #define _DRIVERS_IRQCHIP_IRQ_LOONGSON_H =20 +#define AVEC_MSG_OFFSET 0x100000 + +struct avecintc_data { + struct list_head entry; + unsigned int cpu; + unsigned int vec; + unsigned int prev_cpu; + unsigned int prev_vec; + unsigned int moving; +}; + int find_pch_pic(u32 gsi); =20 int liointc_acpi_init(struct irq_domain *parent, @@ -24,4 +35,12 @@ int pch_msi_acpi_init(struct irq_domain *parent, struct acpi_madt_msi_pic *acpi_pchmsi); int pch_msi_acpi_init_avec(struct irq_domain *parent); =20 +int redirect_acpi_init(struct irq_domain *parent); + +#ifdef CONFIG_SMP +void avecintc_sync(struct avecintc_data *adata); +#else +static inline void avecintc_sync(struct avecintc_data *adata) {} +#endif + #endif /* _DRIVERS_IRQCHIP_IRQ_LOONGSON_H */ --=20 2.41.0