From: Xuyang Dong <dongxuyang@eswincomputing.com> The link [1] provides the official documentation for the EIC7700. Section 3.2 covers the clock subsystem. [1] https://www.sifive.com/document-file/eic7700x-datasheet Updates: Changes in v8: - Added clock-tree link in cover-letter. - Updated YAML file - Added "Acked-by: Troy Mitchell <troy.mitchell@linux.dev>" for bindings. - Updated driver file - Changed Kconfig symbol type from bool to tristate to build this driver as module. - Updated MAINTAINERS file - Added entry "ESWIN EIC7700 CLOCK DRIVER". - Link to v7: https://lore.kernel.org/all/20251023071658.455-1-dongxuyang@eswincomputing.com/ Changes in v7: - Updated YAML file - Added "Acked-by: Conor Dooley <conor.dooley@microchip.com>" for bindings. - Updated driver file - Added description for clk of eswin_calc_pll(). - Added macro EIC7700_MUX_TBL to manage mux clock-tree. - Added eswin_clk_register_mux_tbl() to register mux clocks with discontinuous parent indexes. - Link to v6: https://lore.kernel.org/all/20251009092029.140-1-dongxuyang@eswincomputing.com/ Changes in v6: - Removed config option patch dependency from cover letter, because the patch was applied. - Updated YAML file - Added an oscillator as the clock input, named xtal24m. - Added clocks property. - Updated driver file - Replaced fixed_rate_clk_xtal_24m with xtal24m. - Dropped fixed_rate_clk_xtal_24m from driver. Because clock xtal24m was registered by fixed-clock as oscillator. - Link to v5: https://lore.kernel.org/all/20250923084637.1223-1-dongxuyang@eswincomputing.com/ Changes in v5: - Removed vendor prefix patch dependency from cover letter, because the patch was applied. - Updated YAML file - Placed the required after all properties. - Removed patternProperties. Also removed compatible of eswin,pll-clock, eswin,mux-clock, eswin,divider-clock and eswin,gate-clock as we have moved clock tree from DTS to Linux driver. - Removed the clock tree from DTS. Used clock-controller to manage all clock. Removed all child nodes in clock-controller. - Removed '#address-cells' and '#size-cells' properties, because the clock controller did not need to define these properties. - Removed eic7700-clocks.dtsi. - Added dt-bindings header for clock IDs. Because used the IDs to register clocks. - Updated driver file - Modified the commit for clock driver. Dropped indentation in commit. - Removed CLK_OF_DECLARE(). Used *clk_hw_register* to register clocks. Used devm_of_clk_add_hw_provider. - Dropped singletons. - Checked the value right after obtaining it. - Removed the definitions of macro frequency in clk.h like CLK_FREQ_24M. - Modified description of help in Kconfig. - Added COMPILE_TEST. Added COMMON_CLK_ESWIN for clk.o. And added "select COMMON_CLK_ESWIN" for clk-eic7700.c. Without COMMON_CLK_EIC7700, clk.c could not be compiled. - Used .determined_rate. - Added macro definitions of EIC7700_DIV, EIC7700_FIXED, EIC7700_FACTOR, EIC7700_MUX and EIC7700_PLL to manage clock tree. - Added clk-eic7700.h to place eic7700 SoC clock registers. - Removed refdiv_val and postdiv1_val from clk_pll_recalc_rate(). Because these values were unused. - Link to v4: https://lore.kernel.org/all/20250815093539.975-1-dongxuyang@eswincomputing.com/ Changes in v4: - Updated YAML file - Changed name from cpu-default-frequency to cpu-default-freq-hz. - Dropped $ref of cpu-default-frequency. - Added cpu-default-frequency for required. - Removed cpu-default-frequency in updated file, because there was no need to add cpu-default-frequency. - Moved DIVIDER to DIV. - Arranged the IDs in order. - Dropped EIC7700_NR_CLKS. - Removed dt-bindings eswin,eic7700-clock.h. Because IDs was not used, and used clock device nodes. - According to the updated driver codes, the YAML has been updated. - Updated driver file - Remove undocumented parameters "cpu_no_boost_1_6ghz" and "cpu-default-frequency". - Modified the comment and used the correct Linux coding style. - Removed codes of voltage, because it was not the clock driver. - Updated the formula of clock frequency calculation. Removed the logic that only used register selection. - Used CLK_OF_DECLARE() to register clocks. Registered pll-clock, mux-clock, divider-clock, and gate-clock in clk-eic7700.c. The specific implementation of clock registration was in clk.c. - Added eic7700-clocks.dtsi. - Moved device information to DTS. Put all clocks' node in the eic7700-clocks.dtsi. - Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/ Changes in v3: - Update example, drop child node and add '#clock-cells' to the parent node. - Change parent node from sys-crg to clock-controller for this yaml. - Drop "syscon", "simple-mfd" to clear warnings/errors by using "make dt_binding_check". And these are not necessary. - Add "cpu-default-frequency" definition in yaml for "undocumented ABI". - Drop Reviewed-by, this is misunderstanding. We have not received such an email. - Link to v2: https://lore.kernel.org/all/20250523090747.1830-1-dongxuyang@eswincomputing.com/ Changes in v2: - Update example, drop child node. - Clear warnings/errors for using "make dt_binding_check". - Change to the correct format. - Drop some non-stanard code. - Use dev_err_probe() in probe functions. - Link to v1: https://lore.kernel.org/all/20250514002233.187-1-dongxuyang@eswincomputing.com/ Xuyang Dong (3): dt-bindings: clock: eswin: Documentation for eic7700 SoC clock: eswin: Add eic7700 clock driver MAINTAINERS: Add entry for ESWIN EIC7700 clock driver .../bindings/clock/eswin,eic7700-clock.yaml | 46 + MAINTAINERS | 8 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 15 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 1033 +++++++++++++++++ drivers/clk/eswin/clk-eic7700.h | 122 ++ drivers/clk/eswin/clk.c | 481 ++++++++ drivers/clk/eswin/clk.h | 256 ++++ .../dt-bindings/clock/eswin,eic7700-clock.h | 280 +++++ 11 files changed, 2251 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk-eic7700.h create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/clk.h create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.dev> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- .../bindings/clock/eswin,eic7700-clock.yaml | 46 +++ .../dt-bindings/clock/eswin,eic7700-clock.h | 280 ++++++++++++++++++ 2 files changed, 326 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC clock controller + +maintainers: + - Yifeng Huang <huangyifeng@eswincomputing.com> + - Xuyang Dong <dongxuyang@eswincomputing.com> + +description: + The clock controller generates and supplies clock to all the modules + for eic7700 SoC. + +properties: + compatible: + const: eswin,eic7700-clock + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x51828000 0x300>; + clocks = <&xtal24m>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/dt-bindings/clock/eswin,eic7700-clock.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Device Tree binding constants for EIC7700 clock controller. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ +#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ + +#define EIC7700_CLK_XTAL_32K 0 +#define EIC7700_CLK_PLL_CPU 1 +#define EIC7700_CLK_SPLL0_FOUT1 2 +#define EIC7700_CLK_SPLL0_FOUT2 3 +#define EIC7700_CLK_SPLL0_FOUT3 4 +#define EIC7700_CLK_SPLL1_FOUT1 5 +#define EIC7700_CLK_SPLL1_FOUT2 6 +#define EIC7700_CLK_SPLL1_FOUT3 7 +#define EIC7700_CLK_SPLL2_FOUT1 8 +#define EIC7700_CLK_SPLL2_FOUT2 9 +#define EIC7700_CLK_SPLL2_FOUT3 10 +#define EIC7700_CLK_VPLL_FOUT1 11 +#define EIC7700_CLK_VPLL_FOUT2 12 +#define EIC7700_CLK_VPLL_FOUT3 13 +#define EIC7700_CLK_APLL_FOUT1 14 +#define EIC7700_CLK_APLL_FOUT2 15 +#define EIC7700_CLK_APLL_FOUT3 16 +#define EIC7700_CLK_EXT_MCLK 17 +#define EIC7700_CLK_LPDDR_REF_BAK 18 +#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19 +#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20 +#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21 +#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25 +#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26 +#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27 +#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28 +#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29 +#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30 +#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31 +#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32 +#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33 +#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34 +#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35 +#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36 +#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37 +#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38 +#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39 +#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40 +#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41 +#define EIC7700_CLK_MUX_RMII_REF_2MUX 42 +#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43 +#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44 +#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45 +#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46 +#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47 +#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48 +#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49 +#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50 +#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51 +#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52 +#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53 +#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54 +#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60 +#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61 +#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62 +#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63 +#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64 +#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65 +#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66 +#define EIC7700_CLK_DIV_VI_DVP_DYNM 67 +#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74 +#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75 +#define EIC7700_CLK_DIV_IESMCLK_DYNM 76 +#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77 +#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78 +#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79 +#define EIC7700_CLK_DIV_JD_DYNM 80 +#define EIC7700_CLK_DIV_JE_DYNM 81 +#define EIC7700_CLK_DIV_VE_DYNM 82 +#define EIC7700_CLK_DIV_VD_DYNM 83 +#define EIC7700_CLK_DIV_G2D_DYNM 84 +#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85 +#define EIC7700_CLK_DIV_CRYPTO_DYNM 86 +#define EIC7700_CLK_DIV_VI_DW_DYNM 87 +#define EIC7700_CLK_DIV_NPU_E31_DYNM 88 +#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89 +#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90 +#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91 +#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92 +#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93 +#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94 +#define EIC7700_CLK_DIV_AON_RTC_DYNM 95 +#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96 +#define EIC7700_CLK_DIV_VO_CEC_DYNM 97 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105 +#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106 +#define EIC7700_CLK_GATE_SPLL0_FOUT2 107 +#define EIC7700_CLK_GATE_NOC_NSP_CLK 108 +#define EIC7700_CLK_GATE_BOOTSPI 109 +#define EIC7700_CLK_GATE_BOOTSPI_CFG 110 +#define EIC7700_CLK_GATE_SCPU_CORE 111 +#define EIC7700_CLK_GATE_SCPU_BUS 112 +#define EIC7700_CLK_GATE_LPCPU_CORE 113 +#define EIC7700_CLK_GATE_LPCPU_BUS 114 +#define EIC7700_CLK_GATE_GPU_ACLK 115 +#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116 +#define EIC7700_CLK_GATE_GPU_CFG_CLK 117 +#define EIC7700_CLK_GATE_DSPT_ACLK 118 +#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119 +#define EIC7700_CLK_GATE_D2D_ACLK 120 +#define EIC7700_CLK_GATE_D2D_CFG_CLK 121 +#define EIC7700_CLK_GATE_TCU_ACLK 122 +#define EIC7700_CLK_GATE_TCU_CFG_CLK 123 +#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124 +#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125 +#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126 +#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127 +#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128 +#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129 +#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130 +#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131 +#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132 +#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133 +#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134 +#define EIC7700_CLK_GATE_TIMER_CLK_0 135 +#define EIC7700_CLK_GATE_TIMER_CLK_1 136 +#define EIC7700_CLK_GATE_TIMER_CLK_2 137 +#define EIC7700_CLK_GATE_TIMER_CLK_3 138 +#define EIC7700_CLK_GATE_TIMER_PCLK_0 139 +#define EIC7700_CLK_GATE_TIMER_PCLK_1 140 +#define EIC7700_CLK_GATE_TIMER_PCLK_2 141 +#define EIC7700_CLK_GATE_TIMER_PCLK_3 142 +#define EIC7700_CLK_GATE_TIMER3_CLK8 143 +#define EIC7700_CLK_GATE_PCIET_ACLK 144 +#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145 +#define EIC7700_CLK_GATE_PCIET_CR_CLK 146 +#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147 +#define EIC7700_CLK_GATE_NPU_ACLK 148 +#define EIC7700_CLK_GATE_NPU_CFG_CLK 149 +#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150 +#define EIC7700_CLK_GATE_NPU_CLK 151 +#define EIC7700_CLK_GATE_NPU_E31_CLK 152 +#define EIC7700_CLK_GATE_VI_ACLK 153 +#define EIC7700_CLK_GATE_VI_DVP_CLK 154 +#define EIC7700_CLK_GATE_VI_CFG_CLK 155 +#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156 +#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157 +#define EIC7700_CLK_GATE_VI_SHUTTER_0 158 +#define EIC7700_CLK_GATE_VI_SHUTTER_1 159 +#define EIC7700_CLK_GATE_VI_SHUTTER_2 160 +#define EIC7700_CLK_GATE_VI_SHUTTER_3 161 +#define EIC7700_CLK_GATE_VI_SHUTTER_4 162 +#define EIC7700_CLK_GATE_VI_SHUTTER_5 163 +#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164 +#define EIC7700_CLK_GATE_VI_PHY_CFG 165 +#define EIC7700_CLK_GATE_VO_ACLK 166 +#define EIC7700_CLK_GATE_VO_CFG_CLK 167 +#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168 +#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169 +#define EIC7700_CLK_GATE_VO_I2S_MCLK 170 +#define EIC7700_CLK_GATE_HSP_CFG_CLK 171 +#define EIC7700_CLK_GATE_VC_ACLK 172 +#define EIC7700_CLK_GATE_VC_CFG_CLK 173 +#define EIC7700_CLK_GATE_VC_JE_CLK 174 +#define EIC7700_CLK_GATE_VC_JD_CLK 175 +#define EIC7700_CLK_GATE_VC_VE_CLK 176 +#define EIC7700_CLK_GATE_VC_VD_CLK 177 +#define EIC7700_CLK_GATE_G2D_CFG_CLK 178 +#define EIC7700_CLK_GATE_G2D_CLK 179 +#define EIC7700_CLK_GATE_G2D_ACLK 180 +#define EIC7700_CLK_GATE_AONDMA_CFG 181 +#define EIC7700_CLK_GATE_AONDMA_ACLK 182 +#define EIC7700_CLK_GATE_AON_ACLK 183 +#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184 +#define EIC7700_CLK_GATE_VO_CR_CLK 185 +#define EIC7700_CLK_GATE_HSP_ACLK 186 +#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187 +#define EIC7700_CLK_GATE_RTC_CFG 188 +#define EIC7700_CLK_GATE_RTC 189 +#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190 +#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191 +#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192 +#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193 +#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194 +#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195 +#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196 +#define EIC7700_CLK_GATE_PKA_CFG 197 +#define EIC7700_CLK_GATE_SPACC_CFG 198 +#define EIC7700_CLK_GATE_CRYPTO 199 +#define EIC7700_CLK_GATE_TRNG_CFG 200 +#define EIC7700_CLK_GATE_OTP_CFG 201 +#define EIC7700_CLK_GATE_MAILBOX_0 202 +#define EIC7700_CLK_GATE_MAILBOX_1 203 +#define EIC7700_CLK_GATE_MAILBOX_2 204 +#define EIC7700_CLK_GATE_MAILBOX_3 205 +#define EIC7700_CLK_GATE_MAILBOX_4 206 +#define EIC7700_CLK_GATE_MAILBOX_5 207 +#define EIC7700_CLK_GATE_MAILBOX_6 208 +#define EIC7700_CLK_GATE_MAILBOX_7 209 +#define EIC7700_CLK_GATE_MAILBOX_8 210 +#define EIC7700_CLK_GATE_MAILBOX_9 211 +#define EIC7700_CLK_GATE_MAILBOX_10 212 +#define EIC7700_CLK_GATE_MAILBOX_11 213 +#define EIC7700_CLK_GATE_MAILBOX_12 214 +#define EIC7700_CLK_GATE_MAILBOX_13 215 +#define EIC7700_CLK_GATE_MAILBOX_14 216 +#define EIC7700_CLK_GATE_MAILBOX_15 217 +#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218 +#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219 +#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220 +#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221 +#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222 +#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223 +#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224 +#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225 +#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226 +#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227 +#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228 +#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229 +#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230 +#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231 +#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232 +#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233 +#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234 +#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235 +#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236 +#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237 +#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238 +#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239 +#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240 +#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241 +#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242 +#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243 +#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244 +#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245 +#define EIC7700_CLK_GATE_VC_JE_PCLK 246 +#define EIC7700_CLK_GATE_VC_JD_PCLK 247 +#define EIC7700_CLK_GATE_VC_VE_PCLK 248 +#define EIC7700_CLK_GATE_VC_VD_PCLK 249 +#define EIC7700_CLK_GATE_VC_MON_PCLK 250 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252 +#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253 +#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254 +#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255 +#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256 +#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257 +#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260 +#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261 +#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262 + +#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */ -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add clock drivers for the EIC7700 SoC. The clock controller on the ESWIN EIC7700 provides various clocks to different IP blocks within the SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 15 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 1033 +++++++++++++++++++++++++++++++ drivers/clk/eswin/clk-eic7700.h | 122 ++++ drivers/clk/eswin/clk.c | 481 ++++++++++++++ drivers/clk/eswin/clk.h | 256 ++++++++ 8 files changed, 1917 insertions(+) create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk-eic7700.h create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/clk.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -XXX,XX +XXX,XX @@ source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" source "drivers/clk/bcm/Kconfig" +source "drivers/clk/eswin/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" source "drivers/clk/imx/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +obj-$(CONFIG_ARCH_ESWIN) += eswin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-y += imx/ diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Kconfig @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 + +config COMMON_CLK_ESWIN + bool + +config COMMON_CLK_EIC7700 + tristate "EIC7700 Clock Driver" + depends on ARCH_ESWIN || COMPILE_TEST + select COMMON_CLK_ESWIN + default ARCH_ESWIN + help + This driver provides support for clock controller on ESWIN EIC7700 + SoC. The clock controller can generates and supplies clock to various + peripherals within the SoC. + Say yes here to support the clock controller on the EIC7700 SoC. diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Makefile @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Eswin Clock specific Makefile +# + +obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o + +obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o diff --git a/drivers/clk/eswin/clk-eic7700.c b/drivers/clk/eswin/clk-eic7700.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk-eic7700.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * ESWIN EIC7700 Clk Provider Driver + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/kernel.h> + +#include <dt-bindings/clock/eswin,eic7700-clock.h> + +#include "clk.h" +#include "clk-eic7700.h" + +#define EIC7700_NR_CLKS (EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 + 1) + +/* clock parent list */ +PNAME(mux_cpu_root_3mux1_gfree_p) = { "clk_pll_cpu", + "fixed_factor_u84_core_lp_div2", + "xtal24m" }; +PNAME(mux_cpu_aclk_2mux1_gfree_p) = { "fixed_factor_cpu_div2", + "mux_cpu_root_3mux1_gfree" }; +PNAME(dsp_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll2_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(d2d_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll2_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(ddr_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll2_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mshcore_root_3mux1_0_mux_p) = { "fixed_rate_clk_spll0_fout3", + "fixed_rate_clk_spll2_fout3" }; +PNAME(mshcore_root_3mux1_1_mux_p) = { "fixed_rate_clk_spll0_fout3", + "fixed_rate_clk_spll2_fout3" }; +PNAME(mshcore_root_3mux1_2_mux_p) = { "fixed_rate_clk_spll0_fout3", + "fixed_rate_clk_spll2_fout3" }; +PNAME(npu_llclk_3mux1_gfree_mux_p) = { "divider_npu_llc_src0_div_dynm", + "divider_npu_llc_src1_div_dynm", + "fixed_rate_clk_vpll_fout1" }; +PNAME(npu_core_3mux1_gfree_mux_p) = { "fixed_rate_clk_spll1_fout1", + "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll2_fout2" }; +PNAME(npu_e31_3mux1_gfree_mux_p) = { "fixed_rate_clk_spll1_fout1", + "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll2_fout2" }; +PNAME(vi_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_vi_dw_root_2mux1_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mux_vi_dvp_root_2mux1_gfree_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mux_vi_dig_isp_root_2mux1_gfree_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mux_vo_aclk_root_2mux1_gfree_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_vo_pixel_root_2mux1_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll2_fout2" }; +PNAME(mux_vcdec_root_2mux1_gfree_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_vcaclk_root_2mux1_gfree_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_syscfg_clk_root_2mux1_gfree_p) = { "divider_sys_cfg_div_dynm", + "xtal24m" }; +PNAME(mux_bootspi_clk_2mux1_gfree_p) = { "divider_bootspi_div_dynm", + "xtal24m" }; +PNAME(mux_scpu_core_clk_2mux1_gfree_p) = { "divider_scpu_core_div_dynm", + "xtal24m" }; +PNAME(mux_lpcpu_core_clk_2mux1_gfree_p) = { "divider_lpcpu_core_div_dynm", + "xtal24m" }; +PNAME(mux_vo_mclk_2mux_ext_mclk_p) = { "divider_vo_mclk_div_dynm", + "fixed_rate_ext_mclk" }; +PNAME(mux_aondma_axi2mux1_gfree_p) = { "divider_aondma_axi_div_dynm", + "xtal24m" }; +PNAME(mux_rmii_ref_2mux1_p) = { "fixed_factor_hsp_rmii_ref_div6", + "fixed_rate_lpddr_ref_bak" }; +PNAME(mux_eth_core_2mux1_p) = { "fixed_rate_clk_spll1_fout3", + "fixed_rate_lpddr_ref_bak" }; +PNAME(mux_sata_phy_2mux1_p) = { "divider_sata_phy_ref_div_dynm", + "fixed_rate_lpddr_ref_bak" }; + +/* fixed rate clocks */ +static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = { + EIC7700_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", NULL, 0, + 32768), + EIC7700_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", + NULL, 0, 1600000000), + EIC7700_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", + NULL, 0, 800000000), + EIC7700_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", + NULL, 0, 400000000), + EIC7700_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", + NULL, 0, 1500000000), + EIC7700_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", + NULL, 0, 300000000), + EIC7700_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", + NULL, 0, 250000000), + EIC7700_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", + NULL, 0, 2080000000), + EIC7700_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", + NULL, 0, 1040000000), + EIC7700_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", + NULL, 0, 416000000), + EIC7700_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", + NULL, 0, 1188000000), + EIC7700_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", + NULL, 0, 594000000), + EIC7700_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", + NULL, 0, 49500000), + EIC7700_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", + NULL, 0, 0), + EIC7700_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", + NULL, 0, 0), + EIC7700_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", NULL, 0, 0), + EIC7700_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", + NULL, 0, 50000000), +}; + +/* pll clocks */ +static struct eswin_pll_clock eic7700_pll_clks[] = { + EIC7700_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", NULL, + EIC7700_REG_OFFSET_APLL_CFG_0, 0, 1, 12, 6, 20, 12, + EIC7700_REG_OFFSET_APLL_CFG_1, 4, 24, + EIC7700_REG_OFFSET_APLL_CFG_2, 1, 3, 16, 3, + EIC7700_REG_OFFSET_PLL_STATUS, 4, 1), + EIC7700_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", NULL, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 0, 1, 12, 6, 20, 12, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4, 24, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2, 1, 3, 16, 3, + EIC7700_REG_OFFSET_PLL_STATUS, 5, 1), +}; + +/* fixed factor clocks */ +static struct eswin_fixed_factor_clock eic7700_fixed_factor_clks[] = { + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2, + "fixed_factor_cpu_div2", "mux_cpu_root_3mux1_gfree", 1, + 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, + "fixed_factor_clk_1m_div24", "xtal24m", 1, 24, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, + "fixed_factor_mipi_txesc_div10", + "mux_syscfg_clk_root_2mux1_gfree", 1, 10, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2, + "fixed_factor_u84_core_lp_div2", "gate_clk_spll0_fout2", + 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2, + "fixed_factor_scpu_bus_div2", + "mux_scpu_core_clk_2mux1_gfree", 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2, + "fixed_factor_lpcpu_bus_div2", + "mux_lpcpu_core_clk_2mux1_gfree", 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2, + "fixed_factor_pcie_cr_div2", + "mux_syscfg_clk_root_2mux1_gfree", 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4, + "fixed_factor_pcie_aux_div4", + "mux_syscfg_clk_root_2mux1_gfree", 1, 4, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, + "fixed_factor_pvt_div20", "xtal24m", 1, 20, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6, + "fixed_factor_hsp_rmii_ref_div6", + "fixed_rate_clk_spll1_fout2", 1, 6, 0), +}; + +/* mux clocks */ +static struct eswin_mux_clock eic7700_mux_clks[] = { + EIC7700_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + "mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p, + ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 0, 2, 0), + EIC7700_MUX(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE, + "mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p, + ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 20, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, + "mux_dsp_aclk_root_2mux1_gfree", + dsp_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, + "mux_d2d_aclk_root_2mux1_gfree", + d2d_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, + "mux_ddr_aclk_root_2mux1_gfree", + ddr_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR_CTRL, 16, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0, + "mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC0_CORE_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1, + "mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC1_CORE_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2, + "mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC2_CORE_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE, + "mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC_CTRL, 0, 2, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE, + "mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 0, 2, 0), + EIC7700_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, + "mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 8, 2, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, + "mux_vi_aclk_root_2mux1_gfree", + vi_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1", + mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, + "mux_vi_dvp_root_2mux1_gfree", + mux_vi_dvp_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, + "mux_vi_dig_isp_root_2mux1_gfree", + mux_vi_dig_isp_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, + "mux_vo_aclk_root_2mux1_gfree", + mux_vo_aclk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, + "mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p, + ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, + "mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, + "mux_vcaclk_root_2mux1_gfree", + mux_vcaclk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + "mux_syscfg_clk_root_2mux1_gfree", + mux_syscfg_clk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE, + "mux_bootspi_clk_2mux1_gfree", + mux_bootspi_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, + "mux_scpu_core_clk_2mux1_gfree", + mux_scpu_core_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, + "mux_lpcpu_core_clk_2mux1_gfree", + mux_lpcpu_core_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK, + "mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p, + ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, + "mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p, + ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA_CTRL, 20, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1", + mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL, 2, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1", + mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL, 1, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1", + mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB_CTRL, 9, + 1, 0), +}; + +/* divider clocks */ +static struct eswin_divider_clock eic7700_div_clks[] = { + EIC7700_DIV(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm", + "fixed_rate_clk_spll0_fout3", 0, + EIC7700_REG_OFFSET_SYSCFG_CTRL, 4, 3, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm", + "fixed_rate_clk_spll2_fout1", 0, + EIC7700_REG_OFFSET_NOC_CTRL, 0, 3, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm", + "gate_clk_spll0_fout2", 0, EIC7700_REG_OFFSET_BOOTSPI_CTRL, + 4, 6, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_SCPU_CORE_DYNM, + "divider_scpu_core_div_dynm", "fixed_rate_clk_spll0_fout1", + 0, EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_LPCPU_CORE_DYNM, + "divider_lpcpu_core_div_dynm", "fixed_rate_clk_spll0_fout1", + 0, EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_GPU_ACLK_DYNM, "divider_gpu_aclk_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_GPU_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_D2D_ACLK_DYNM, "divider_d2d_aclk_div_dynm", + "mux_d2d_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_ACLK_DYNM, "divider_dsp_aclk_div_dynm", + "mux_d2d_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_DDR_ACLK_DYNM, "divider_ddr_aclk_div_dynm", + "mux_ddr_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_DDR_CTRL, 20, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_HSP_ACLK_DYNM, "divider_hsp_aclk_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, + "divider_eth_txclk_div_dynm_0", "mux_eth_core_2mux1", 0, + EIC7700_REG_OFFSET_ETH0_CTRL, 4, 7, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, + "divider_eth_txclk_div_dynm_1", "mux_eth_core_2mux1", 0, + EIC7700_REG_OFFSET_ETH1_CTRL, 4, 7, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, + "divider_mshc_core_div_dynm_0", "mux_mshcore_root_3mux1_0", + 0, EIC7700_REG_OFFSET_MSHC0_CORE_CTRL, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, + "divider_mshc_core_div_dynm_1", "mux_mshcore_root_3mux1_1", + 0, EIC7700_REG_OFFSET_MSHC1_CORE_CTRL, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, + "divider_mshc_core_div_dynm_2", "mux_mshcore_root_3mux1_2", + 0, EIC7700_REG_OFFSET_MSHC2_CORE_CTRL, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_PCIE_ACLK_DYNM, + "divider_pcie_aclk_div_dynm", "fixed_rate_clk_spll2_fout2", + 0, EIC7700_REG_OFFSET_PCIE_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_ACLK_DYNM, "divider_npu_aclk_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM, + "divider_npu_llc_src0_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_NPU_LLC_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM, + "divider_npu_llc_src1_div_dynm", + "fixed_rate_clk_spll2_fout1", 0, + EIC7700_REG_OFFSET_NPU_LLC_CTRL, 8, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_CORECLK_DYNM, + "divider_npu_coreclk_div_dynm", "mux_npu_core_3mux1_gfree", + 0, EIC7700_REG_OFFSET_NPU_CORE_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm", + "mux_npu_e31_3mux1_gfree", 0, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 12, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm", + "mux_vi_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VI_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm", + "mux_vi_dw_root_2mux1", 0, + EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm", + "mux_vi_dvp_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VI_DVP_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, + "divider_vi_dig_isp_div_dynm", + "mux_vi_dig_isp_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, + "divider_vi_shutter_div_dynm_0", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, + "divider_vi_shutter_div_dynm_1", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, + "divider_vi_shutter_div_dynm_2", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, + "divider_vi_shutter_div_dynm_3", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, + "divider_vi_shutter_div_dynm_4", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, + "divider_vi_shutter_div_dynm_5", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm", + "mux_vo_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VO_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm", + "fixed_rate_clk_spll0_fout3", 0, + EIC7700_REG_OFFSET_VO_IESMCLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_PIXEL_DYNM, "divider_vo_pixel_div_dynm", + "mux_vo_pixel_root_2mux1", 0, + EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 4, 6, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm", + "clk_apll_fout1", 0, EIC7700_REG_OFFSET_VO_MCLK_CTRL, 4, 8, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VO_PHY_CLKCTRL, 16, 16, + CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm", + "mux_vcaclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VC_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_JD_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_JE_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_VE_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_VD_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm", + "mux_dsp_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_G2D_CTRL, 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_AONDMA_AXI_DYNM, + "divider_aondma_axi_div_dynm", "fixed_rate_clk_spll0_fout1", + 0, EIC7700_REG_OFFSET_AON_DMA_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_SPACC_CTRL, 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM, + "divider_sata_phy_ref_div_dynm", + "fixed_rate_clk_spll1_fout2", 0, + EIC7700_REG_OFFSET_SATA_OOB_CTRL, 0, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM, + "divider_dsp_0_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 19, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM, + "divider_dsp_1_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 20, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM, + "divider_dsp_2_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 21, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM, + "divider_dsp_3_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 22, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm", + "fixed_factor_clk_1m_div24", 0, EIC7700_REG_OFFSET_RTC_CTRL, + 21, 11, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM, + "divider_u84_rtc_toggle_dynm", "xtal24m", 0, + EIC7700_REG_OFFSET_RTC_CTRL, 16, 5, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), +}; + +/* gate clocks */ +static struct eswin_gate_clock eic7700_gate_clks[] = { + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0, + "gate_clk_cpu_ext_src_core_clk_0", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 28, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1, + "gate_clk_cpu_ext_src_core_clk_1", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 29, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2, + "gate_clk_cpu_ext_src_core_clk_2", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3, + "gate_clk_cpu_ext_src_core_clk_3", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0, + "gate_clk_cpu_trace_clk_0", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 24, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1, + "gate_clk_cpu_trace_clk_1", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 25, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2, + "gate_clk_cpu_trace_clk_2", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 26, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3, + "gate_clk_cpu_trace_clk_3", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 27, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK, + "gate_clk_cpu_trace_com_clk", "mux_cpu_aclk_2mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 23, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2", + "fixed_rate_clk_spll0_fout2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk", + "divider_noc_nsp_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NOC_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi", + "mux_bootspi_clk_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_BOOTSPI_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_BOOTSPI_CFGCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core", + "mux_scpu_core_clk_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus", + "fixed_factor_scpu_bus_div2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SCPU_BUSCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core", + "mux_lpcpu_core_clk_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus", + "fixed_factor_lpcpu_bus_div2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LPCPU_BUSCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk", + "divider_gpu_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", + "xtal24m", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_GRAY_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk", + "divider_dsp_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DSP_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk", + "divider_d2d_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_D2D_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TCU_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TCU_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 9, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk", + "divider_hsp_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk", + "divider_pcie_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk", + "fixed_factor_pcie_cr_div2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk", + "fixed_factor_pcie_aux_div4", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk", + "divider_npu_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk", + "mux_npu_llclk_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_LLC_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk", + "divider_npu_coreclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk", + "divider_npu_e31_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk", + "divider_vi_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_ACLK_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk", + "divider_vi_dw_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk", + "divider_vi_dvp_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DVP_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk", + "divider_vi_dig_isp_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0", + "divider_vi_shutter_div_dynm_0", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1", + "divider_vi_shutter_div_dynm_1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2", + "divider_vi_shutter_div_dynm_2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3", + "divider_vi_shutter_div_dynm_3", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4", + "divider_vi_shutter_div_dynm_4", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5", + "divider_vi_shutter_div_dynm_5", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC, "gate_vi_phy_txclkesc", + "fixed_factor_mipi_txesc_div10", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_PHY_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk", + "divider_vo_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_ACLK_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK, "gate_vo_hdmi_iesmclk", + "divider_iesmclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_IESMCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk", + "divider_vo_pixel_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk", + "mux_vo_mclk_2mux_ext_mclk", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_MCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk", + "fixed_factor_mipi_txesc_div10", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PHY_CLKCTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk", + "divider_vc_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk", + "divider_je_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_JE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk", + "divider_jd_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_JD_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk", + "divider_ve_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk", + "divider_vd_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VD_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D_CTRL, 28, 0), + EIC7700_GATE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk", + "divider_g2d_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk", + "divider_g2d_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_AON_DMA_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk", + "mux_aondma_axi2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_AON_DMA_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk", + "mux_aondma_axi2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_AON_DMA_CTRL, 29, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 3, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8", + "fixed_rate_clk_vpll_fout3", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_RTC_CTRL, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc", + "divider_aon_rtc_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_RTC_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PKA_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPACC_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto", + "divider_crypto_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPACC_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TRNG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_OTP_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 3, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 9, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 10, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 11, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 12, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 13, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 14, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 15, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 9, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 10, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 11, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 12, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 13, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 14, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 15, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 28, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 29, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 26, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 27, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 17, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 18, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 19, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 20, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 21, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 25, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk", + "fixed_factor_pvt_div20", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk", + "fixed_factor_pvt_div20", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 17, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 3, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK, + "gate_hsp_mshc0_core_clk", "divider_mshc_core_div_dynm_0", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC0_CORE_CTRL, + 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK, + "gate_hsp_mshc1_core_clk", "divider_mshc_core_div_dynm_1", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC1_CORE_CTRL, + 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK, + "gate_hsp_mshc2_core_clk", "divider_mshc_core_div_dynm_2", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC2_CORE_CTRL, + 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK, "gate_hsp_sata_rbc_clk", + "fixed_rate_clk_spll1_fout2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SATA_RBC_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK, "gate_hsp_sata_oob_clk", + "mux_sata_phy_2mux1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SATA_OOB_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST, + "gate_hsp_dma0_clk_test", "gate_clk_hsp_aclk", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 1, + 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk", + "gate_clk_hsp_aclk", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK, + "gate_hsp_eth0_core_clk", "divider_eth_txclk_div_dynm_0", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK, + "gate_hsp_eth1_core_clk", "divider_eth_txclk_div_dynm_1", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH1_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0", + "mux_rmii_ref_2mux1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH0_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1", + "mux_rmii_ref_2mux1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH1_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_I2C0_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_I2C1_CTRL, 31, 0), +}; + +static int eic7700_clk_probe(struct platform_device *pdev) +{ + struct eswin_clock_data *clk_data; + struct device *dev = &pdev->dev; + + clk_data = eswin_clk_init(dev, EIC7700_NR_CLKS); + if (!clk_data) + return dev_err_probe(dev, -EAGAIN, "failed to get clk data!\n"); + + eswin_clk_register_fixed_rate(eic7700_fixed_rate_clks, + ARRAY_SIZE(eic7700_fixed_rate_clks), + clk_data, dev); + + eswin_clk_register_pll(eic7700_pll_clks, ARRAY_SIZE(eic7700_pll_clks), + clk_data, dev); + + eswin_clk_register_fixed_factor(eic7700_fixed_factor_clks, + ARRAY_SIZE(eic7700_fixed_factor_clks), + clk_data, dev); + + eswin_clk_register_mux(eic7700_mux_clks, ARRAY_SIZE(eic7700_mux_clks), + clk_data, dev); + + eswin_clk_register_divider(eic7700_div_clks, + ARRAY_SIZE(eic7700_div_clks), clk_data, dev); + + eswin_clk_register_gate(eic7700_gate_clks, + ARRAY_SIZE(eic7700_gate_clks), clk_data, dev); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &clk_data->clk_data); +} + +static const struct of_device_id eic7700_clock_dt_ids[] = { + { .compatible = "eswin,eic7700-clock", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids); + +static struct platform_driver eic7700_clock_driver = { + .probe = eic7700_clk_probe, + .driver = { + .name = "eic7700-clock", + .of_match_table = eic7700_clock_dt_ids, + }, +}; +module_platform_driver(eic7700_clock_driver); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Yifeng Huang<huangyifeng@eswincomputing.com>"); +MODULE_AUTHOR("Xuyang Dong<dongxuyang@eswincomputing.com>"); +MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver"); diff --git a/drivers/clk/eswin/clk-eic7700.h b/drivers/clk/eswin/clk-eic7700.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk-eic7700.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __CLK_EIC7700_H__ +#define __CLK_EIC7700_H__ + +/* REG OFFSET OF SYS-CRG */ +#define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0 +#define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4 +#define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8 +#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC +#define EIC7700_REG_OFFSET_SPLL0_SSC 0x10 +#define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14 +#define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18 +#define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C +#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20 +#define EIC7700_REG_OFFSET_SPLL1_SSC 0x24 +#define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28 +#define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C +#define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30 +#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34 +#define EIC7700_REG_OFFSET_SPLL2_SSC 0x38 +#define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C +#define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40 +#define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44 +#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48 +#define EIC7700_REG_OFFSET_VPLL_SSC 0x4C +#define EIC7700_REG_OFFSET_APLL_CFG_0 0x50 +#define EIC7700_REG_OFFSET_APLL_CFG_1 0x54 +#define EIC7700_REG_OFFSET_APLL_CFG_2 0x58 +#define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C +#define EIC7700_REG_OFFSET_APLL_SSC 0x60 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C +#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70 +#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74 +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78 +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80 +#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84 +#define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88 +#define EIC7700_REG_OFFSET_PLL_STATUS 0xA4 +#define EIC7700_REG_OFFSET_NOC_CTRL 0x100 +#define EIC7700_REG_OFFSET_BOOTSPI_CTRL 0x104 +#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK_CTRL 0x108 +#define EIC7700_REG_OFFSET_SCPU_CORE_CTRL 0x10C +#define EIC7700_REG_OFFSET_SCPU_BUSCLK_CTRL 0x110 +#define EIC7700_REG_OFFSET_LPCPU_CORE_CTRL 0x114 +#define EIC7700_REG_OFFSET_LPCPU_BUSCLK_CTRL 0x118 +#define EIC7700_REG_OFFSET_TCU_ACLK_CTRL 0x11C +#define EIC7700_REG_OFFSET_TCU_CFG_CTRL 0x120 +#define EIC7700_REG_OFFSET_DDR_CTRL 0x124 +#define EIC7700_REG_OFFSET_DDR1_CTRL 0x128 +#define EIC7700_REG_OFFSET_GPU_ACLK_CTRL 0x12C +#define EIC7700_REG_OFFSET_GPU_CFG_CTRL 0x130 +#define EIC7700_REG_OFFSET_GPU_GRAY_CTRL 0x134 +#define EIC7700_REG_OFFSET_DSP_ACLK_CTRL 0x138 +#define EIC7700_REG_OFFSET_DSP_CFG_CTRL 0x13C +#define EIC7700_REG_OFFSET_D2D_ACLK_CTRL 0x140 +#define EIC7700_REG_OFFSET_D2D_CFG_CTRL 0x144 +#define EIC7700_REG_OFFSET_HSP_ACLK_CTRL 0x148 +#define EIC7700_REG_OFFSET_HSP_CFG_CTRL 0x14C +#define EIC7700_REG_OFFSET_SATA_RBC_CTRL 0x150 +#define EIC7700_REG_OFFSET_SATA_OOB_CTRL 0x154 +#define EIC7700_REG_OFFSET_ETH0_CTRL 0x158 +#define EIC7700_REG_OFFSET_ETH1_CTRL 0x15C +#define EIC7700_REG_OFFSET_MSHC0_CORE_CTRL 0x160 +#define EIC7700_REG_OFFSET_MSHC1_CORE_CTRL 0x164 +#define EIC7700_REG_OFFSET_MSHC2_CORE_CTRL 0x168 +#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C +#define EIC7700_REG_OFFSET_PCIE_ACLK_CTRL 0x170 +#define EIC7700_REG_OFFSET_PCIE_CFG_CTRL 0x174 +#define EIC7700_REG_OFFSET_NPU_ACLK_CTRL 0x178 +#define EIC7700_REG_OFFSET_NPU_LLC_CTRL 0x17C +#define EIC7700_REG_OFFSET_NPU_CORE_CTRL 0x180 +#define EIC7700_REG_OFFSET_VI_DWCLK_CTRL 0x184 +#define EIC7700_REG_OFFSET_VI_ACLK_CTRL 0x188 +#define EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL 0x18C +#define EIC7700_REG_OFFSET_VI_DVP_CTRL 0x190 +#define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194 +#define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198 +#define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C +#define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0 +#define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4 +#define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8 +#define EIC7700_REG_OFFSET_VI_PHY_CTRL 0x1AC +#define EIC7700_REG_OFFSET_VO_ACLK_CTRL 0x1B0 +#define EIC7700_REG_OFFSET_VO_IESMCLK_CTRL 0x1B4 +#define EIC7700_REG_OFFSET_VO_PIXEL_CTRL 0x1B8 +#define EIC7700_REG_OFFSET_VO_MCLK_CTRL 0x1BC +#define EIC7700_REG_OFFSET_VO_PHY_CLKCTRL 0x1C0 +#define EIC7700_REG_OFFSET_VC_ACLK_CTRL 0x1C4 +#define EIC7700_REG_OFFSET_VCDEC_ROOT_CTRL 0x1C8 +#define EIC7700_REG_OFFSET_G2D_CTRL 0x1CC +#define EIC7700_REG_OFFSET_VC_CLKEN_CTRL 0x1D0 +#define EIC7700_REG_OFFSET_JE_CTRL 0x1D4 +#define EIC7700_REG_OFFSET_JD_CTRL 0x1D8 +#define EIC7700_REG_OFFSET_VD_CTRL 0x1DC +#define EIC7700_REG_OFFSET_VE_CTRL 0x1E0 +#define EIC7700_REG_OFFSET_AON_DMA_CTRL 0x1E4 +#define EIC7700_REG_OFFSET_TIMER_CTRL 0x1E8 +#define EIC7700_REG_OFFSET_RTC_CTRL 0x1EC +#define EIC7700_REG_OFFSET_PKA_CTRL 0x1F0 +#define EIC7700_REG_OFFSET_SPACC_CTRL 0x1F4 +#define EIC7700_REG_OFFSET_TRNG_CTRL 0x1F8 +#define EIC7700_REG_OFFSET_OTP_CTRL 0x1FC +#define EIC7700_REG_OFFSET_LSP_EN0 0x200 +#define EIC7700_REG_OFFSET_LSP_EN1 0x204 +#define EIC7700_REG_OFFSET_U84_CTRL 0x208 +#define EIC7700_REG_OFFSET_SYSCFG_CTRL 0x20C +#define EIC7700_REG_OFFSET_I2C0_CTRL 0x210 +#define EIC7700_REG_OFFSET_I2C1_CTRL 0x214 + +#endif /* __CLK_EIC7700_H__ */ diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/math.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/eswin,eic7700-clock.h> + +#include "clk.h" + +struct eswin_clock_data *eswin_clk_init(struct device *dev, + int nr_clks) +{ + struct eswin_clock_data *eclk_data; + + eclk_data = devm_kzalloc(dev, struct_size(eclk_data, clk_data.hws, + nr_clks), GFP_KERNEL); + if (!eclk_data) + return NULL; + + eclk_data->base = devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(eclk_data->base)) { + dev_err(dev, "failed to map clock registers\n"); + return NULL; + } + + eclk_data->clk_data.num = nr_clks; + /* Avoid returning NULL for unused id */ + memset_p((void **)eclk_data->clk_data.hws, ERR_PTR(-ENOENT), nr_clks); + spin_lock_init(&eclk_data->lock); + + return eclk_data; +} + +/** + * eswin_calc_pll - calculate PLL values + * @frac_val: fractional divider + * @fbdiv_val: feedback divider + * @rate: reference rate + * @clk: PLL clock + * + * Calculate PLL values for frac and fbdiv + */ +static int eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, u64 rate, + const struct eswin_clk_pll *clk) +{ + u64 rem = 0; + u32 tmp1 = 0, tmp2 = 0; + + if (clk->id == EIC7700_CLK_APLL_FOUT1 || + clk->id == EIC7700_CLK_PLL_CPU) { + rate = rate * 4; + rem = do_div(rate, 1000); + if (rem) + tmp1 = rem; + + rem = do_div(rate, 1000); + if (rem) + tmp2 = rem; + + rem = do_div(rate, 24); + /* fbdiv = rate * 4 / 24000000 */ + *fbdiv_val = rate; + /* frac = rate * 4 % 24000000 * (2 ^ 24) */ + *frac_val = (u64)((1000 * (1000 * rem + tmp2) + tmp1) << 24) + / 24 / 1000000; + } else { + pr_err("Invalid pll set req, rate %lld, clk id %d\n", rate, + clk->id); + return -EINVAL; + } + + return 0; +} + +static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw) +{ + return container_of(hw, struct eswin_clk_pll, hw); +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + struct clk *clk_cpu_lp_pll = NULL; + struct clk *clk_cpu_mux = NULL; + struct clk *clk_cpu_pll = NULL; + u32 postdiv1_val = 0, refdiv_val = 1; + u32 frac_val, fbdiv_val, val; + bool lock_flag = false; + int try_count = 0; + int ret; + + ret = eswin_calc_pll(&frac_val, &fbdiv_val, (u64)rate, clk); + if (ret) + return ret; + + /* Must switch the CPU to other CLK before we change the CPU PLL. */ + if (clk->id == EIC7700_CLK_PLL_CPU) { + clk_cpu_mux = __clk_lookup("mux_cpu_root_3mux1_gfree"); + if (!clk_cpu_mux) { + pr_err("failed to get clk: %s\n", + "mux_cpu_root_3mux1_gfree"); + return -EINVAL; + } + + clk_cpu_lp_pll = __clk_lookup("fixed_factor_u84_core_lp_div2"); + if (!clk_cpu_lp_pll) { + pr_err("failed to get clk: %s\n", + "fixed_factor_u84_core_lp_div2"); + return -EINVAL; + } + + ret = clk_prepare_enable(clk_cpu_lp_pll); + if (ret) { + pr_err("failed to enable clk: %s, ret = %d\n", + "fixed_factor_u84_core_lp_div2", ret); + return ret; + } + + clk_cpu_pll = __clk_lookup("clk_pll_cpu"); + if (!clk_cpu_pll) { + pr_err("failed to get clk: %s\n", "clk_pll_cpu"); + clk_disable_unprepare(clk_cpu_lp_pll); + return -EINVAL; + } + + ret = clk_set_parent(clk_cpu_mux, clk_cpu_lp_pll); + if (ret) { + pr_err("failed to switch %s to %s, ret %d\n", + "mux_cpu_root_3mux1_gfree", + "fixed_factor_u84_core_lp_div2", ret); + clk_disable_unprepare(clk_cpu_lp_pll); + return -EPERM; + } + } + + /* First, disable pll */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift); + val |= 0 << clk->pllen_shift; + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift); + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift); + val |= refdiv_val << clk->refdiv_shift; + val |= fbdiv_val << clk->fbdiv_shift; + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg1); + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); + val |= frac_val << clk->frac_shift; + writel_relaxed(val, clk->ctrl_reg1); + + val = readl_relaxed(clk->ctrl_reg2); + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); + val |= postdiv1_val << clk->postdiv1_shift; + writel_relaxed(val, clk->ctrl_reg2); + + /* Last, enable pll */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift); + val |= 1 << clk->pllen_shift; + writel_relaxed(val, clk->ctrl_reg0); + + /* Usually the pll will lock in 50us */ + do { + usleep_range(refdiv_val * 80, refdiv_val * 80 * 2); + val = readl_relaxed(clk->status_reg); + if (val & 1 << clk->lock_shift) { + lock_flag = true; + break; + } + } while (try_count++ < 10); + + if (!lock_flag) { + pr_err("failed to lock the cpu pll!\n"); + return -EBUSY; + } + + if (clk->id == EIC7700_CLK_PLL_CPU) { + ret = clk_set_parent(clk_cpu_mux, clk_cpu_pll); + if (ret) { + pr_err("failed to switch %s to %s, ret %d\n", + "mux_cpu_root_3mux1_gfree", "clk_pll_cpu", ret); + return -EPERM; + } + clk_disable_unprepare(clk_cpu_lp_pll); + } + + return ret; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + u64 fbdiv_val, frac_val, rem, tmp; + u32 val; + u64 rate = 0; + + val = readl_relaxed(clk->ctrl_reg0); + val = val >> clk->fbdiv_shift; + val &= ((1 << clk->fbdiv_width) - 1); + fbdiv_val = val; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->frac_shift; + val &= ((1 << clk->frac_width) - 1); + frac_val = val; + + /* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */ + if (clk->id == EIC7700_CLK_APLL_FOUT1 || + clk->id == EIC7700_CLK_PLL_CPU) { + tmp = 1000 * frac_val; + rem = do_div(tmp, BIT(24)); + if (rem) + rate = (u64)(6000 * (1000 * fbdiv_val + tmp) + + ((6000 * rem) >> 24) + 1); + else + rate = (u64)(6000 * 1000 * fbdiv_val); + } else { + pr_err("unknown clk id %d\n", clk->id); + } + + return rate; +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + + switch (clk->id) { + case EIC7700_CLK_APLL_FOUT1: + req->rate = clamp(req->rate, APLL_LOW_FREQ, APLL_HIGH_FREQ); + req->min_rate = APLL_LOW_FREQ; + req->max_rate = APLL_HIGH_FREQ; + break; + case EIC7700_CLK_PLL_CPU: + req->rate = clamp(req->rate, PLL_LOW_FREQ, PLL_HIGH_FREQ); + req->min_rate = PLL_LOW_FREQ; + req->max_rate = PLL_HIGH_FREQ; + break; + default: + pr_err("unknown clk id %d\n", clk->id); + break; + } + + return 0; +} + +int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + clks[i].rate); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +static const struct clk_ops eswin_clk_pll_ops = { + .set_rate = clk_pll_set_rate, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, +}; + +void eswin_clk_register_pll(const struct eswin_pll_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev) +{ + struct eswin_clk_pll *p_clk = NULL; + struct clk_init_data init; + struct clk_hw *clk_hw; + int i, ret; + + p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); + if (!p_clk) + return; + + for (i = 0; i < nums; i++) { + p_clk->id = clks[i].id; + p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0; + p_clk->pllen_shift = clks[i].pllen_shift; + p_clk->pllen_width = clks[i].pllen_width; + p_clk->refdiv_shift = clks[i].refdiv_shift; + p_clk->refdiv_width = clks[i].refdiv_width; + p_clk->fbdiv_shift = clks[i].fbdiv_shift; + p_clk->fbdiv_width = clks[i].fbdiv_width; + + p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1; + p_clk->frac_shift = clks[i].frac_shift; + p_clk->frac_width = clks[i].frac_width; + + p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2; + p_clk->postdiv1_shift = clks[i].postdiv1_shift; + p_clk->postdiv1_width = clks[i].postdiv1_width; + p_clk->postdiv2_shift = clks[i].postdiv2_shift; + p_clk->postdiv2_width = clks[i].postdiv2_width; + + p_clk->status_reg = data->base + clks[i].status_reg; + p_clk->lock_shift = clks[i].lock_shift; + p_clk->lock_width = clks[i].lock_width; + + init.name = clks[i].name; + init.flags = 0; + init.parent_names = clks[i].parent_name ? + &clks[i].parent_name : NULL; + init.num_parents = clks[i].parent_name ? 1 : 0; + init.ops = &eswin_clk_pll_ops; + p_clk->hw.init = &init; + + clk_hw = &p_clk->hw; + ret = devm_clk_hw_register(dev, clk_hw); + if (ret) { + dev_err(dev, "failed to register clock %s\n", + clks[i].name); + continue; + } + + data->clk_data.hws[clks[i].id] = clk_hw; + p_clk++; + } +} + +int eswin_clk_register_fixed_factor(const struct eswin_fixed_factor_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_fixed_factor(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + clks[i].mult, + clks[i].div); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_mux(const struct eswin_mux_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_mux(dev, clks[i].name, + clks[i].parent_names, + clks[i].num_parents, + clks[i].flags, + data->base + clks[i].offset, + clks[i].shift, + clks[i].width, + clks[i].mux_flags, + &data->lock); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_mux_tbl(const struct eswin_mux_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = clk_hw_register_mux_table(dev, clks[i].name, + clks[i].parent_names, + clks[i].num_parents, + clks[i].flags, + data->base + clks[i].offset, + clks[i].shift, + BIT(clks[i].width) - 1, + clks[i].mux_flags, + clks[i].table, &data->lock); + + if (IS_ERR(clk_hw)) { + while (i--) + clk_hw_unregister_mux + (data->clk_data.hws[clks[i].id]); + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + } + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_divider(const struct eswin_divider_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_divider(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + data->base + + clks[i].offset, + clks[i].shift, + clks[i].width, + clks[i].div_flags, + &data->lock); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_gate(const struct eswin_gate_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_gate(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + data->base + clks[i].offset, + clks[i].bit_idx, + clks[i].gate_flags, + &data->lock); + + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} diff --git a/drivers/clk/eswin/clk.h b/drivers/clk/eswin/clk.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __ESWIN_CLK_H__ +#define __ESWIN_CLK_H__ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#define APLL_HIGH_FREQ 983040000 +#define APLL_LOW_FREQ 225792000 +#define PLL_HIGH_FREQ 1800000000 +#define PLL_LOW_FREQ 24000000 + +struct eswin_clock_data { + void __iomem *base; + spinlock_t lock; /* protect register read-modify-write cycle */ + struct clk_hw_onecell_data clk_data; +}; + +struct eswin_divider_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 div_flags; +}; + +struct eswin_fixed_rate_clock { + unsigned int id; + char *name; + const char *parent_name; + unsigned long flags; + unsigned long rate; +}; + +struct eswin_fixed_factor_clock { + unsigned int id; + char *name; + const char *parent_name; + unsigned long mult; + unsigned long div; + unsigned long flags; +}; + +struct eswin_gate_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 bit_idx; + u8 gate_flags; +}; + +struct eswin_mux_clock { + unsigned int id; + const char *name; + const char *const *parent_names; + u8 num_parents; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 mux_flags; + u32 *table; +}; + +struct eswin_pll_clock { + u32 id; + const char *name; + const char *parent_name; + const u32 ctrl_reg0; + const u8 pllen_shift; + const u8 pllen_width; + const u8 refdiv_shift; + const u8 refdiv_width; + const u8 fbdiv_shift; + const u8 fbdiv_width; + + const u32 ctrl_reg1; + const u8 frac_shift; + const u8 frac_width; + + const u32 ctrl_reg2; + const u8 postdiv1_shift; + const u8 postdiv1_width; + const u8 postdiv2_shift; + const u8 postdiv2_width; + + const u32 status_reg; + const u8 lock_shift; + const u8 lock_width; +}; + +struct eswin_clk_pll { + struct clk_hw hw; + u32 id; + void __iomem *ctrl_reg0; + u8 pllen_shift; + u8 pllen_width; + u8 refdiv_shift; + u8 refdiv_width; + u8 fbdiv_shift; + u8 fbdiv_width; + + void __iomem *ctrl_reg1; + u8 frac_shift; + u8 frac_width; + + void __iomem *ctrl_reg2; + u8 postdiv1_shift; + u8 postdiv1_width; + u8 postdiv2_shift; + u8 postdiv2_width; + + void __iomem *status_reg; + u8 lock_shift; + u8 lock_width; +}; + +struct eswin_clock_data *eswin_clk_init(struct device *dev, int nr_clks); +int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +void eswin_clk_register_pll(const struct eswin_pll_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev); +int eswin_clk_register_fixed_factor(const struct eswin_fixed_factor_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +int eswin_clk_register_mux(const struct eswin_mux_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev); +int eswin_clk_register_mux_tbl(const struct eswin_mux_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +int eswin_clk_register_divider(const struct eswin_divider_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +int eswin_clk_register_gate(const struct eswin_gate_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev); + +#define PNAME(x) static const char *const x[] __initconst + +#define EIC7700_DIV(_id, _name, _pname, _flags, _offset, _shift, _width, \ + _dflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = _flags, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _dflags, \ + } + +#define EIC7700_FACTOR(_id, _name, _pname, _mult, _div, _flags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .mult = _mult, \ + .div = _div, \ + .flags = _flags, \ + } + +#define EIC7700_FIXED(_id, _name, _pname, _flags, _rate) \ +{ \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = _flags, \ + .rate = _rate, \ +} + +#define EIC7700_GATE(_id, _name, _pname, _flags, _offset, _idx, _gflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = _flags, \ + .offset = _offset, \ + .bit_idx = _idx, \ + .gate_flags = _gflags, \ + } + +#define EIC7700_MUX(_id, _name, _pnames, _num_parents, _flags, _offset, \ + _shift, _width, _mflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_names = _pnames, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + } + +#define EIC7700_MUX_TBL(_id, _name, _pnames, _num_parents, _flags, _offset, \ + _shift, _width, _mflags, _table) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_names = _pnames, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + .table = _table, \ + } + +#define EIC7700_PLL(_id, _name, _pname, _reg0, _en_shift, _en_width, \ + _ref_shift, _ref_width, _fb_shift, _fb_width, _reg1,\ + _frac_shift, _frac_width, _reg2, _post1_shift, \ + _post1_width, _post2_shift, _post2_width, _reg, \ + _lock_shift, _lock_width) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .ctrl_reg0 = _reg0, \ + .pllen_shift = _en_shift, \ + .pllen_width = _en_width, \ + .refdiv_shift = _ref_shift, \ + .refdiv_width = _ref_width, \ + .fbdiv_shift = _fb_shift, \ + .fbdiv_width = _fb_width, \ + .ctrl_reg1 = _reg1, \ + .frac_shift = _frac_shift, \ + .frac_width = _frac_width, \ + .ctrl_reg2 = _reg2, \ + .postdiv1_shift = _post1_shift, \ + .postdiv1_width = _post1_width, \ + .postdiv2_shift = _post2_shift, \ + .postdiv2_width = _post2_width, \ + .status_reg = _reg, \ + .lock_shift = _lock_shift, \ + .lock_width = _lock_width, \ + } + +#endif /* __ESWIN_CLK_H__ */ -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add Yifeng Huang and myself as maintainer of ESWIN EIC7700 clock driver. Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ T: git https://github.com/eswincomputing/linux-next.git F: Documentation/devicetree/bindings/riscv/eswin.yaml F: arch/riscv/boot/dts/eswin/ +ESWIN EIC7700 CLOCK DRIVER +M: Xuyang Dong <dongxuyang@eswincomputing.com> +M: Yifeng Huang <huangyifeng@eswincomputing.com> +S: Maintained +F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml +F: drivers/clk/eswin/ +F: include/dt-bindings/clock/eswin,eic7700-clock.h + ET131X NETWORK DRIVER M: Mark Einon <mark.einon@gmail.com> S: Odd Fixes -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> The link [1] provides the official documentation for the EIC7700. Section 3.2 covers the clock subsystem. [1] https://www.sifive.com/document-file/eic7700x-datasheet Updates: Change in v14: - Updated driver file - Change the error code returned from eswin_clk_init() from -EAGAIN to PTR_ERR(clk_data). - In eswin_clk_init(), replace NULL returns with appropriate error pointers: - Use ERR_PTR(-ENOMEM) for devm_kzalloc() failure. - Use ERR_PTR(-EINVAL) for devm_platform_ioremap_resource() failure and remove dev_err(). - Add the CLK_IGNORE_UNUSED flag to gate clocks. When clk_ignore_unused is dropped during testing, these clocks should remain enabled. - Modify the frac calculation formula to: frac = (rate * 4 % parent_rate * (2^24)) / parent_rate - Add step-by-step calculation descriptions in eswin_calc_pll. Remove the tmp1 and temp2 variables, using only 'rem = do_div(tmp, parent_rate)' to calculate frac. The previous calculation formula was overly complex. - Rename offset to reg in clock structures. Also, rename reg to ctrl_reg in the divider clock structure. - All lines are limited to 80 characters. In cases with long function call parameter lists, lines may extend to 100 characters to preserve readability. - Drop linux/delay.h header file. - Add devm_clk_hw_register_divider_parent_data() to clk-provider.h (preparatory patch). - Replace clk_hw_register_divider_parent_data() with devm_clk_hw_register_divider_parent_data. - Link to v13: https://lore.kernel.org/all/20260214101421.228-1-dongxuyang@eswincomputing.com/ Change in v13: - Updated driver file - Modify commit subject from "clock: eswin: ..." to "clk: eswin: ...". - Use parent rate to calculate PLL clock rate. - Use GENMASK() to define PLL mask macros and use FIELD_PREP() to simplify bitwise operations. - Remove shift and width references for pll enable, refdiv, fbdiv, frac and postdiv. (Use only the PLL macros to match the functionality) - Set postdiv1 and postdiv2 in clk_pll_set_rate function. - Link to v12: https://lore.kernel.org/all/20260213094112.115-1-dongxuyang@eswincomputing.com/ Change in v12: - Updated driver file - Add CLK_MUX_ROUND_CLOSEST to the mux clocks since they need a more accurate clock frequency. - Change 'rem' from u64 to u32 for function 'eswin_calc_pll' and function 'clk_pll_recalc_rate'. - Change 'rate' from u64 to unsigned long for function 'clk_pll_recalc_rate'. - Fix build error with u64 divisor for function `clk_pll_set_rate'. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202602111424.mhTAakDX-lkp@intel.com/ - Link to v11: https://lore.kernel.org/all/20260210095008.726-1-dongxuyang@eswincomputing.com/ Change in v11: - Updated driver file - Add "Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77" tag. - Fix build error in function eswin_clk_register_clks. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202602060520.p4Hg35Ja-lkp@intel.com/ - Link to v10: https://lore.kernel.org/all/20260205093322.1030-1-dongxuyang@eswincomputing.com/ Changes in v10: - Updated driver file - Add a private clock divider API named 'eswin_register_clkdiv' to register divider clocks with private flag. Define 'ESWIN_PRIV_DIV_MIN_2' private flag for registering the clock dividers whose division ratio start from 2. Implement the private set_rate, recalc_rate, and determine_rate accordingly. - Add CLK_DIVIDER_ALLOW_ZERO flag to the clock dividers whose division ratio start from 0. - Replace CONFIG_ARCH_ESWIN with CONFIG_COMMON_CLK_ESWIN in the Makefile. - Modify the help description of COMMON_CLK_EIC7700. - Move register offset definitions from 'clk-eic7700.h' to 'clk-eic7700.c' and remove the 'clk-eic7700.h'. Remove '_CTRL' from the offset names. - Remove all unused headers. - Use devm_platform_ioremap_resource() instead of devm_of_iomap(). - Export the functions from clk.c as symbols. - Use readl_poll_timeout(). - Use 'clk_parent_data' and '.hw' instead of string parent names. - Rename the header file from clk.h to common.h. - Rename macros from EIC7700_* to ESWIN_* in common.h. - Add a new function, 'eswin_clk_register_clks', which can register divider, mux, gate, and fixed-factor clocks based on their types. - Add structure 'eswin_clk_info' to manage the clocks that need to be registered in a specific order. - Add macros 'ESWIN_*_TYPE' to define divider, mux, gate, and fixed-factor clocks with type. Add enum 'eswin_clk_type' for these types. - Remove 'eswin_clk_register_mux_tbl'. Use 'eswin_clk_register_mux' to register mux clocks with or without table. - Add xtal24m as the parent clock of the PLL. - Change 2025 to 2026 in all files. - Link to v9: https://lore.kernel.org/all/20251229105844.1089-1-dongxuyang@eswincomputing.com/ Changes in v9: - Updated driver file - Checked return values of eswin_clk_register_*() in the probe function. - Removed binding IDs check from pll functions in clk.c, as these functions were exclusively used by pll clocks and did not require ID validation. - The PLL structure has been extended with max_rate and min_rate fields to explicitly define the frequency operating range of the PLL. These limits were now utilized by the clk_pll_determine_rate() function. - Removed __clk_lookup() in clk_pll_set_rate. Added clk_notifier support in clk-eic7700.c. - Added five previously missing clocks from [1]. - Link to v8: https://lore.kernel.org/all/20251113013637.1109-1-dongxuyang@eswincomputing.com/ Changes in v8: - Updated YAML file - Added "Acked-by: Troy Mitchell <troy.mitchell@linux.dev>" - Updated driver file - Changed Kconfig from bool to tristate. - Updated MAINTAINERS file - Added "ESWIN SOC SERIES CLOCK DRIVER" - Link to v7: https://lore.kernel.org/all/20251023071658.455-1-dongxuyang@eswincomputing.com/ Changes in v7: - Updated YAML file - Added "Acked-by: Conor Dooley <conor.dooley@microchip.com>" for bindings. - Updated driver file - Added description for clk of eswin_calc_pll(). - Added macro EIC7700_MUX_TBL to manage mux clock-tree. - Added eswin_clk_register_mux_tbl() to register mux clocks with discontinuous parent indexes. - Link to v6: https://lore.kernel.org/all/20251009092029.140-1-dongxuyang@eswincomputing.com/ Changes in v6: - Removed config option patch dependency from cover letter, because the patch was applied. - Updated YAML file - Added an oscillator as the clock input, named xtal24m. - Added clocks property. - Updated driver file - Replaced fixed_rate_clk_xtal_24m with xtal24m. - Dropped fixed_rate_clk_xtal_24m from driver. Because clock xtal24m was registered by fixed-clock as oscillator. - Link to v5: https://lore.kernel.org/all/20250923084637.1223-1-dongxuyang@eswincomputing.com/ Changes in v5: - Removed vendor prefix patch dependency from cover letter, because the patch was applied. - Updated YAML file - Placed the required after all properties. - Removed patternProperties. Also removed compatible of eswin,pll-clock, eswin,mux-clock, eswin,divider-clock and eswin,gate-clock as we have moved clock tree from DTS to Linux driver. - Removed the clock tree from DTS. Used clock-controller to manage all clock. Removed all child nodes in clock-controller. - Removed '#address-cells' and '#size-cells' properties, because the clock controller did not need to define these properties. - Removed eic7700-clocks.dtsi. - Added dt-bindings header for clock IDs. Because used the IDs to register clocks. - Updated driver file - Modified the commit for clock driver. Dropped indentation in commit. - Removed CLK_OF_DECLARE(). Used *clk_hw_register* to register clocks. Used devm_of_clk_add_hw_provider. - Dropped singletons. - Checked the value right after obtaining it. - Removed the definitions of macro frequency in clk.h like CLK_FREQ_24M. - Modified description of help in Kconfig. - Added COMPILE_TEST. Added COMMON_CLK_ESWIN for clk.o. And added "select COMMON_CLK_ESWIN" for clk-eic7700.c. Without COMMON_CLK_EIC7700, clk.c could not be compiled. - Used .determined_rate. - Added macro definitions of EIC7700_DIV, EIC7700_FIXED, EIC7700_FACTOR, EIC7700_MUX and EIC7700_PLL to manage clock tree. - Added clk-eic7700.h to place eic7700 SoC clock registers. - Removed refdiv_val and postdiv1_val from clk_pll_recalc_rate(). Because these values were unused. - Link to v4: https://lore.kernel.org/all/20250815093539.975-1-dongxuyang@eswincomputing.com/ Changes in v4: - Updated YAML file - Changed name from cpu-default-frequency to cpu-default-freq-hz. - Dropped $ref of cpu-default-frequency. - Added cpu-default-frequency for required. - Removed cpu-default-frequency in updated file, because there was no need to add cpu-default-frequency. - Moved DIVIDER to DIV. - Arranged the IDs in order. - Dropped EIC7700_NR_CLKS. - Removed dt-bindings eswin,eic7700-clock.h. Because IDs was not used, and used clock device nodes. - According to the updated driver codes, the YAML has been updated. - Updated driver file - Remove undocumented parameters "cpu_no_boost_1_6ghz" and "cpu-default-frequency". - Modified the comment and used the correct Linux coding style. - Removed codes of voltage, because it was not the clock driver. - Updated the formula of clock frequency calculation. Removed the logic that only used register selection. - Used CLK_OF_DECLARE() to register clocks. Registered pll-clock, mux-clock, divider-clock, and gate-clock in clk-eic7700.c. The specific implementation of clock registration was in clk.c. - Added eic7700-clocks.dtsi. - Moved device information to DTS. Put all clocks' node in the eic7700-clocks.dtsi. - Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/ Changes in v3: - Update example, drop child node and add '#clock-cells' to the parent node. - Change parent node from sys-crg to clock-controller for this yaml. - Drop "syscon", "simple-mfd" to clear warnings/errors by using "make dt_binding_check". And these are not necessary. - Add "cpu-default-frequency" definition in yaml for "undocumented ABI". - Drop Reviewed-by, this is misunderstanding. We have not received such an email. - Link to v2: https://lore.kernel.org/all/20250523090747.1830-1-dongxuyang@eswincomputing.com/ Changes in v2: - Update example, drop child node. - Clear warnings/errors for using "make dt_binding_check". - Change to the correct format. - Drop some non-stanard code. - Use dev_err_probe() in probe functions. - Link to v1: https://lore.kernel.org/all/20250514002233.187-1-dongxuyang@eswincomputing.com/ Xuyang Dong (4): dt-bindings: clock: eswin: Documentation for eic7700 SoC clk: divider: Add devm_clk_hw_register_divider_parent_data clk: eswin: Add eic7700 clock driver MAINTAINERS: Add entry for ESWIN EIC7700 clock driver .../bindings/clock/eswin,eic7700-clock.yaml | 46 + MAINTAINERS | 8 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 15 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 1376 +++++++++++++++++ drivers/clk/eswin/clk.c | 588 +++++++ drivers/clk/eswin/common.h | 340 ++++ .../dt-bindings/clock/eswin,eic7700-clock.h | 285 ++++ include/linux/clk-provider.h | 20 + 11 files changed, 2688 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/common.h create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h -- 2.34.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.dev> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- .../bindings/clock/eswin,eic7700-clock.yaml | 46 +++ .../dt-bindings/clock/eswin,eic7700-clock.h | 285 ++++++++++++++++++ 2 files changed, 331 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC clock controller + +maintainers: + - Yifeng Huang <huangyifeng@eswincomputing.com> + - Xuyang Dong <dongxuyang@eswincomputing.com> + +description: + The clock controller generates and supplies clock to all the modules + for eic7700 SoC. + +properties: + compatible: + const: eswin,eic7700-clock + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x51828000 0x300>; + clocks = <&xtal24m>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/dt-bindings/clock/eswin,eic7700-clock.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Device Tree binding constants for EIC7700 clock controller. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ +#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ + +#define EIC7700_CLK_XTAL_32K 0 +#define EIC7700_CLK_PLL_CPU 1 +#define EIC7700_CLK_SPLL0_FOUT1 2 +#define EIC7700_CLK_SPLL0_FOUT2 3 +#define EIC7700_CLK_SPLL0_FOUT3 4 +#define EIC7700_CLK_SPLL1_FOUT1 5 +#define EIC7700_CLK_SPLL1_FOUT2 6 +#define EIC7700_CLK_SPLL1_FOUT3 7 +#define EIC7700_CLK_SPLL2_FOUT1 8 +#define EIC7700_CLK_SPLL2_FOUT2 9 +#define EIC7700_CLK_SPLL2_FOUT3 10 +#define EIC7700_CLK_VPLL_FOUT1 11 +#define EIC7700_CLK_VPLL_FOUT2 12 +#define EIC7700_CLK_VPLL_FOUT3 13 +#define EIC7700_CLK_APLL_FOUT1 14 +#define EIC7700_CLK_APLL_FOUT2 15 +#define EIC7700_CLK_APLL_FOUT3 16 +#define EIC7700_CLK_EXT_MCLK 17 +#define EIC7700_CLK_LPDDR_REF_BAK 18 +#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19 +#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20 +#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21 +#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25 +#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26 +#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27 +#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28 +#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29 +#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30 +#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31 +#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32 +#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33 +#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34 +#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35 +#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36 +#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37 +#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38 +#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39 +#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40 +#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41 +#define EIC7700_CLK_MUX_RMII_REF_2MUX 42 +#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43 +#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44 +#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45 +#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46 +#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47 +#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48 +#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49 +#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50 +#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51 +#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52 +#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53 +#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54 +#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60 +#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61 +#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62 +#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63 +#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64 +#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65 +#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66 +#define EIC7700_CLK_DIV_VI_DVP_DYNM 67 +#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74 +#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75 +#define EIC7700_CLK_DIV_IESMCLK_DYNM 76 +#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77 +#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78 +#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79 +#define EIC7700_CLK_DIV_JD_DYNM 80 +#define EIC7700_CLK_DIV_JE_DYNM 81 +#define EIC7700_CLK_DIV_VE_DYNM 82 +#define EIC7700_CLK_DIV_VD_DYNM 83 +#define EIC7700_CLK_DIV_G2D_DYNM 84 +#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85 +#define EIC7700_CLK_DIV_CRYPTO_DYNM 86 +#define EIC7700_CLK_DIV_VI_DW_DYNM 87 +#define EIC7700_CLK_DIV_NPU_E31_DYNM 88 +#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89 +#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90 +#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91 +#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92 +#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93 +#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94 +#define EIC7700_CLK_DIV_AON_RTC_DYNM 95 +#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96 +#define EIC7700_CLK_DIV_VO_CEC_DYNM 97 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105 +#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106 +#define EIC7700_CLK_GATE_SPLL0_FOUT2 107 +#define EIC7700_CLK_GATE_NOC_NSP_CLK 108 +#define EIC7700_CLK_GATE_BOOTSPI 109 +#define EIC7700_CLK_GATE_BOOTSPI_CFG 110 +#define EIC7700_CLK_GATE_SCPU_CORE 111 +#define EIC7700_CLK_GATE_SCPU_BUS 112 +#define EIC7700_CLK_GATE_LPCPU_CORE 113 +#define EIC7700_CLK_GATE_LPCPU_BUS 114 +#define EIC7700_CLK_GATE_GPU_ACLK 115 +#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116 +#define EIC7700_CLK_GATE_GPU_CFG_CLK 117 +#define EIC7700_CLK_GATE_DSPT_ACLK 118 +#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119 +#define EIC7700_CLK_GATE_D2D_ACLK 120 +#define EIC7700_CLK_GATE_D2D_CFG_CLK 121 +#define EIC7700_CLK_GATE_TCU_ACLK 122 +#define EIC7700_CLK_GATE_TCU_CFG_CLK 123 +#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124 +#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125 +#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126 +#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127 +#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128 +#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129 +#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130 +#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131 +#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132 +#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133 +#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134 +#define EIC7700_CLK_GATE_TIMER_CLK_0 135 +#define EIC7700_CLK_GATE_TIMER_CLK_1 136 +#define EIC7700_CLK_GATE_TIMER_CLK_2 137 +#define EIC7700_CLK_GATE_TIMER_CLK_3 138 +#define EIC7700_CLK_GATE_TIMER_PCLK_0 139 +#define EIC7700_CLK_GATE_TIMER_PCLK_1 140 +#define EIC7700_CLK_GATE_TIMER_PCLK_2 141 +#define EIC7700_CLK_GATE_TIMER_PCLK_3 142 +#define EIC7700_CLK_GATE_TIMER3_CLK8 143 +#define EIC7700_CLK_GATE_PCIET_ACLK 144 +#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145 +#define EIC7700_CLK_GATE_PCIET_CR_CLK 146 +#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147 +#define EIC7700_CLK_GATE_NPU_ACLK 148 +#define EIC7700_CLK_GATE_NPU_CFG_CLK 149 +#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150 +#define EIC7700_CLK_GATE_NPU_CLK 151 +#define EIC7700_CLK_GATE_NPU_E31_CLK 152 +#define EIC7700_CLK_GATE_VI_ACLK 153 +#define EIC7700_CLK_GATE_VI_DVP_CLK 154 +#define EIC7700_CLK_GATE_VI_CFG_CLK 155 +#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156 +#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157 +#define EIC7700_CLK_GATE_VI_SHUTTER_0 158 +#define EIC7700_CLK_GATE_VI_SHUTTER_1 159 +#define EIC7700_CLK_GATE_VI_SHUTTER_2 160 +#define EIC7700_CLK_GATE_VI_SHUTTER_3 161 +#define EIC7700_CLK_GATE_VI_SHUTTER_4 162 +#define EIC7700_CLK_GATE_VI_SHUTTER_5 163 +#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164 +#define EIC7700_CLK_GATE_VI_PHY_CFG 165 +#define EIC7700_CLK_GATE_VO_ACLK 166 +#define EIC7700_CLK_GATE_VO_CFG_CLK 167 +#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168 +#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169 +#define EIC7700_CLK_GATE_VO_I2S_MCLK 170 +#define EIC7700_CLK_GATE_HSP_CFG_CLK 171 +#define EIC7700_CLK_GATE_VC_ACLK 172 +#define EIC7700_CLK_GATE_VC_CFG_CLK 173 +#define EIC7700_CLK_GATE_VC_JE_CLK 174 +#define EIC7700_CLK_GATE_VC_JD_CLK 175 +#define EIC7700_CLK_GATE_VC_VE_CLK 176 +#define EIC7700_CLK_GATE_VC_VD_CLK 177 +#define EIC7700_CLK_GATE_G2D_CFG_CLK 178 +#define EIC7700_CLK_GATE_G2D_CLK 179 +#define EIC7700_CLK_GATE_G2D_ACLK 180 +#define EIC7700_CLK_GATE_AONDMA_CFG 181 +#define EIC7700_CLK_GATE_AONDMA_ACLK 182 +#define EIC7700_CLK_GATE_AON_ACLK 183 +#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184 +#define EIC7700_CLK_GATE_VO_CR_CLK 185 +#define EIC7700_CLK_GATE_HSP_ACLK 186 +#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187 +#define EIC7700_CLK_GATE_RTC_CFG 188 +#define EIC7700_CLK_GATE_RTC 189 +#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190 +#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191 +#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192 +#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193 +#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194 +#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195 +#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196 +#define EIC7700_CLK_GATE_PKA_CFG 197 +#define EIC7700_CLK_GATE_SPACC_CFG 198 +#define EIC7700_CLK_GATE_CRYPTO 199 +#define EIC7700_CLK_GATE_TRNG_CFG 200 +#define EIC7700_CLK_GATE_OTP_CFG 201 +#define EIC7700_CLK_GATE_MAILBOX_0 202 +#define EIC7700_CLK_GATE_MAILBOX_1 203 +#define EIC7700_CLK_GATE_MAILBOX_2 204 +#define EIC7700_CLK_GATE_MAILBOX_3 205 +#define EIC7700_CLK_GATE_MAILBOX_4 206 +#define EIC7700_CLK_GATE_MAILBOX_5 207 +#define EIC7700_CLK_GATE_MAILBOX_6 208 +#define EIC7700_CLK_GATE_MAILBOX_7 209 +#define EIC7700_CLK_GATE_MAILBOX_8 210 +#define EIC7700_CLK_GATE_MAILBOX_9 211 +#define EIC7700_CLK_GATE_MAILBOX_10 212 +#define EIC7700_CLK_GATE_MAILBOX_11 213 +#define EIC7700_CLK_GATE_MAILBOX_12 214 +#define EIC7700_CLK_GATE_MAILBOX_13 215 +#define EIC7700_CLK_GATE_MAILBOX_14 216 +#define EIC7700_CLK_GATE_MAILBOX_15 217 +#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218 +#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219 +#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220 +#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221 +#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222 +#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223 +#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224 +#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225 +#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226 +#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227 +#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228 +#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229 +#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230 +#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231 +#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232 +#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233 +#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234 +#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235 +#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236 +#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237 +#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238 +#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239 +#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240 +#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241 +#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242 +#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243 +#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244 +#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245 +#define EIC7700_CLK_GATE_VC_JE_PCLK 246 +#define EIC7700_CLK_GATE_VC_JD_PCLK 247 +#define EIC7700_CLK_GATE_VC_VE_PCLK 248 +#define EIC7700_CLK_GATE_VC_VD_PCLK 249 +#define EIC7700_CLK_GATE_VC_MON_PCLK 250 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252 +#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253 +#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254 +#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255 +#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256 +#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257 +#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260 +#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261 +#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262 +#define EIC7700_CLK_DIV_NOC_WDREF_DYNM 263 +#define EIC7700_CLK_GATE_DDR0_TRACE 264 +#define EIC7700_CLK_GATE_DDR1_TRACE 265 +#define EIC7700_CLK_GATE_RNOC_NSP 266 +#define EIC7700_CLK_GATE_NOC_WDREF 267 + +#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */ -- 2.34.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add the devres variant of clk_hw_register_divider_parent_data() for registering a divider clock with parent clk data instead of parent name. Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- include/linux/clk-provider.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index XXXXXXX..XXXXXXX 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -XXX,XX +XXX,XX @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, (parent_hw), NULL, (flags), (reg), \ (shift), (width), (clk_divider_flags), \ NULL, (lock)) +/** + * devm_clk_hw_register_divider_parent_data - register a divider clock with the + * clock framework + * @dev: device registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags + * @reg: register address to adjust divider + * @shift: number of bits to shift the bitfield + * @width: width of the bitfield + * @clk_divider_flags: divider-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \ + flags, reg, shift, width, \ + clk_divider_flags, lock) \ + __devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (shift), \ + (width), (clk_divider_flags), NULL, \ + (lock)) /** * devm_clk_hw_register_divider_table - register a table based divider clock * with the clock framework (devres variant) -- 2.34.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add clock drivers for the EIC7700 SoC. The clock controller on the ESWIN EIC7700 provides various clocks to different IP blocks within the SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 15 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 1376 +++++++++++++++++++++++++++++++ drivers/clk/eswin/clk.c | 588 +++++++++++++ drivers/clk/eswin/common.h | 340 ++++++++ 7 files changed, 2329 insertions(+) create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/common.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -XXX,XX +XXX,XX @@ source "drivers/clk/analogbits/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/baikal-t1/Kconfig" source "drivers/clk/bcm/Kconfig" +source "drivers/clk/eswin/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" source "drivers/clk/imx/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +obj-$(CONFIG_COMMON_CLK_ESWIN) += eswin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-y += imx/ diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Kconfig @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 + +config COMMON_CLK_ESWIN + bool + +config COMMON_CLK_EIC7700 + tristate "EIC7700 Clock Driver" + depends on ARCH_ESWIN || COMPILE_TEST + select COMMON_CLK_ESWIN + default ARCH_ESWIN + help + This driver provides support for clock controller on ESWIN EIC7700 + SoC. The clock controller generates and supplies clocks to various + peripherals within the SoC. + Say yes here to support the clock controller on the EIC7700 SoC. diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Makefile @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Eswin Clock specific Makefile +# + +obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o + +obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o diff --git a/drivers/clk/eswin/clk-eic7700.c b/drivers/clk/eswin/clk-eic7700.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk-eic7700.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * ESWIN EIC7700 Clk Provider Driver + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/eswin,eic7700-clock.h> + +#include "common.h" + +/* REG OFFSET OF SYS-CRG */ +#define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0 +#define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4 +#define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8 +#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC +#define EIC7700_REG_OFFSET_SPLL0_SSC 0x10 +#define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14 +#define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18 +#define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C +#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20 +#define EIC7700_REG_OFFSET_SPLL1_SSC 0x24 +#define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28 +#define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C +#define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30 +#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34 +#define EIC7700_REG_OFFSET_SPLL2_SSC 0x38 +#define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C +#define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40 +#define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44 +#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48 +#define EIC7700_REG_OFFSET_VPLL_SSC 0x4C +#define EIC7700_REG_OFFSET_APLL_CFG_0 0x50 +#define EIC7700_REG_OFFSET_APLL_CFG_1 0x54 +#define EIC7700_REG_OFFSET_APLL_CFG_2 0x58 +#define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C +#define EIC7700_REG_OFFSET_APLL_SSC 0x60 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C +#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70 +#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74 +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78 +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80 +#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84 +#define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88 +#define EIC7700_REG_OFFSET_PLL_STATUS 0xA4 +#define EIC7700_REG_OFFSET_NOC 0x100 +#define EIC7700_REG_OFFSET_BOOTSPI 0x104 +#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK 0x108 +#define EIC7700_REG_OFFSET_SCPU_CORE 0x10C +#define EIC7700_REG_OFFSET_SCPU_BUSCLK 0x110 +#define EIC7700_REG_OFFSET_LPCPU_CORE 0x114 +#define EIC7700_REG_OFFSET_LPCPU_BUSCLK 0x118 +#define EIC7700_REG_OFFSET_TCU_ACLK 0x11C +#define EIC7700_REG_OFFSET_TCU_CFG 0x120 +#define EIC7700_REG_OFFSET_DDR 0x124 +#define EIC7700_REG_OFFSET_DDR1 0x128 +#define EIC7700_REG_OFFSET_GPU_ACLK 0x12C +#define EIC7700_REG_OFFSET_GPU_CFG 0x130 +#define EIC7700_REG_OFFSET_GPU_GRAY 0x134 +#define EIC7700_REG_OFFSET_DSP_ACLK 0x138 +#define EIC7700_REG_OFFSET_DSP_CFG 0x13C +#define EIC7700_REG_OFFSET_D2D_ACLK 0x140 +#define EIC7700_REG_OFFSET_D2D_CFG 0x144 +#define EIC7700_REG_OFFSET_HSP_ACLK 0x148 +#define EIC7700_REG_OFFSET_HSP_CFG 0x14C +#define EIC7700_REG_OFFSET_SATA_RBC 0x150 +#define EIC7700_REG_OFFSET_SATA_OOB 0x154 +#define EIC7700_REG_OFFSET_ETH0 0x158 +#define EIC7700_REG_OFFSET_ETH1 0x15C +#define EIC7700_REG_OFFSET_MSHC0_CORE 0x160 +#define EIC7700_REG_OFFSET_MSHC1_CORE 0x164 +#define EIC7700_REG_OFFSET_MSHC2_CORE 0x168 +#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C +#define EIC7700_REG_OFFSET_PCIE_ACLK 0x170 +#define EIC7700_REG_OFFSET_PCIE_CFG 0x174 +#define EIC7700_REG_OFFSET_NPU_ACLK 0x178 +#define EIC7700_REG_OFFSET_NPU_LLC 0x17C +#define EIC7700_REG_OFFSET_NPU_CORE 0x180 +#define EIC7700_REG_OFFSET_VI_DWCLK 0x184 +#define EIC7700_REG_OFFSET_VI_ACLK 0x188 +#define EIC7700_REG_OFFSET_VI_DIG_ISP 0x18C +#define EIC7700_REG_OFFSET_VI_DVP 0x190 +#define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194 +#define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198 +#define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C +#define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0 +#define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4 +#define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8 +#define EIC7700_REG_OFFSET_VI_PHY 0x1AC +#define EIC7700_REG_OFFSET_VO_ACLK 0x1B0 +#define EIC7700_REG_OFFSET_VO_IESMCLK 0x1B4 +#define EIC7700_REG_OFFSET_VO_PIXEL 0x1B8 +#define EIC7700_REG_OFFSET_VO_MCLK 0x1BC +#define EIC7700_REG_OFFSET_VO_PHY_CLK 0x1C0 +#define EIC7700_REG_OFFSET_VC_ACLK 0x1C4 +#define EIC7700_REG_OFFSET_VCDEC_ROOT 0x1C8 +#define EIC7700_REG_OFFSET_G2D 0x1CC +#define EIC7700_REG_OFFSET_VC_CLKEN 0x1D0 +#define EIC7700_REG_OFFSET_JE 0x1D4 +#define EIC7700_REG_OFFSET_JD 0x1D8 +#define EIC7700_REG_OFFSET_VD 0x1DC +#define EIC7700_REG_OFFSET_VE 0x1E0 +#define EIC7700_REG_OFFSET_AON_DMA 0x1E4 +#define EIC7700_REG_OFFSET_TIMER 0x1E8 +#define EIC7700_REG_OFFSET_RTC 0x1EC +#define EIC7700_REG_OFFSET_PKA 0x1F0 +#define EIC7700_REG_OFFSET_SPACC 0x1F4 +#define EIC7700_REG_OFFSET_TRNG 0x1F8 +#define EIC7700_REG_OFFSET_OTP 0x1FC +#define EIC7700_REG_OFFSET_LSP_EN0 0x200 +#define EIC7700_REG_OFFSET_LSP_EN1 0x204 +#define EIC7700_REG_OFFSET_U84 0x208 +#define EIC7700_REG_OFFSET_SYSCFG 0x20C +#define EIC7700_REG_OFFSET_I2C0 0x210 +#define EIC7700_REG_OFFSET_I2C1 0x214 + +#define EIC7700_NR_CLKS (EIC7700_CLK_GATE_NOC_WDREF + 1) + +/* + * The 24 MHz oscillator, the root of most of the clock tree. + */ +static const struct clk_parent_data xtal24M[] = { + { .index = 0, } +}; + +/* fixed rate clocks */ +static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = { + ESWIN_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", 0, 32768), + ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", 0, + 1600000000), + ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", 0, + 800000000), + ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", 0, + 400000000), + ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", 0, + 1500000000), + ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", 0, + 300000000), + ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", 0, + 250000000), + ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", 0, + 2080000000), + ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", 0, + 1040000000), + ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", 0, + 416000000), + ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", 0, + 1188000000), + ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", 0, + 594000000), + ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", 0, + 49500000), + ESWIN_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", 0, 0), + ESWIN_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", 0, 0), + ESWIN_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", 0, 0), + ESWIN_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", 0, + 50000000), +}; + +/* pll clocks */ +static struct eswin_pll_clock eic7700_pll_clks[] = { + ESWIN_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", xtal24M, + EIC7700_REG_OFFSET_APLL_CFG_0, 20, + EIC7700_REG_OFFSET_APLL_CFG_1, 4, + EIC7700_REG_OFFSET_APLL_CFG_2, EIC7700_REG_OFFSET_PLL_STATUS, + 4, 1, APLL_HIGH_FREQ, APLL_LOW_FREQ), + ESWIN_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", xtal24M, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 20, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2, + EIC7700_REG_OFFSET_PLL_STATUS, 5, 1, PLL_HIGH_FREQ, + PLL_LOW_FREQ), +}; + +/* fixed factor clocks */ +static struct eswin_fixed_factor_clock eic7700_factor_clks[] = { + ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, + "fixed_factor_clk_1m_div24", xtal24M, 1, 24, 0), + ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, + "fixed_factor_pvt_div20", xtal24M, 1, 20, 0), +}; + +/* divider clocks */ +static struct eswin_divider_clock eic7700_div_clks[] = { + ESWIN_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM, + "divider_u84_rtc_toggle_dynm", xtal24M, 0, + EIC7700_REG_OFFSET_RTC, 16, 5, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), + ESWIN_DIV(EIC7700_CLK_DIV_NOC_WDREF_DYNM, "divider_noc_wdref_dynm", + xtal24M, 0, EIC7700_REG_OFFSET_NOC, 4, 16, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), +}; + +/* gate clocks */ +static struct eswin_gate_clock eic7700_gate_clks[] = { + ESWIN_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", xtal24M, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_GRAY, 31, 0), + ESWIN_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", xtal24M, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 1, 0), + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", xtal24M, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 0, 0), + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", xtal24M, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 1, 0), + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", xtal24M, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 2, 0), + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", xtal24M, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 3, 0), +}; + +/* Define the early clocks as the parent clocks of the mux clocks. */ +static struct eswin_clk_info eic7700_early_clks[] = { + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6, + "fixed_factor_hsp_rmii_ref_div6", + EIC7700_CLK_SPLL1_FOUT2, 1, 6, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM, + "divider_npu_llc_src0_div_dynm", + EIC7700_CLK_SPLL0_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC, + 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM, + "divider_npu_llc_src1_div_dynm", + EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC, + 8, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2", + EIC7700_CLK_SPLL0_FOUT2, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm", + EIC7700_CLK_GATE_SPLL0_FOUT2, 0, + EIC7700_REG_OFFSET_BOOTSPI, 4, 6, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SCPU_CORE_DYNM, + "divider_scpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, + EIC7700_REG_OFFSET_SCPU_CORE, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_LPCPU_CORE_DYNM, + "divider_lpcpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, + 0, EIC7700_REG_OFFSET_LPCPU_CORE, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm", + EIC7700_CLK_APLL_FOUT1, 0, EIC7700_REG_OFFSET_VO_MCLK, 4, + 8, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AONDMA_AXI_DYNM, + "divider_aondma_axi_div_dynm", EIC7700_CLK_SPLL0_FOUT1, + 0, EIC7700_REG_OFFSET_AON_DMA, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM, + "divider_sata_phy_ref_div_dynm", + EIC7700_CLK_SPLL1_FOUT2, 0, EIC7700_REG_OFFSET_SATA_OOB, + 0, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm", + EIC7700_CLK_SPLL0_FOUT3, 0, EIC7700_REG_OFFSET_SYSCFG, 4, + 3, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2, + "fixed_factor_u84_core_lp_div2", + EIC7700_CLK_GATE_SPLL0_FOUT2, 1, 2, 0), +}; + +static const struct clk_parent_data dsp_aclk_root_2mux1_gfree_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[7].hw }, + { .hw = &eic7700_fixed_rate_clks[1].hw }, +}; + +static const struct clk_parent_data d2d_aclk_root_2mux1_gfree_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[7].hw }, + { .hw = &eic7700_fixed_rate_clks[1].hw }, +}; + +static const struct clk_parent_data ddr_aclk_root_2mux1_gfree_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[7].hw }, + { .hw = &eic7700_fixed_rate_clks[1].hw }, +}; + +static const struct clk_parent_data mshcore_root_3mux1_0_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[3].hw }, + { .hw = &eic7700_fixed_rate_clks[9].hw }, +}; + +static const struct clk_parent_data mshcore_root_3mux1_1_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[3].hw }, + { .hw = &eic7700_fixed_rate_clks[9].hw }, +}; + +static const struct clk_parent_data mshcore_root_3mux1_2_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[3].hw }, + { .hw = &eic7700_fixed_rate_clks[9].hw }, +}; + +static const struct clk_parent_data npu_core_3mux1_gfree_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[4].hw }, + { .hw = &eic7700_fixed_rate_clks[10].hw }, + { .hw = &eic7700_fixed_rate_clks[8].hw }, +}; + +static const struct clk_parent_data npu_e31_3mux1_gfree_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[4].hw }, + { .hw = &eic7700_fixed_rate_clks[10].hw }, + { .hw = &eic7700_fixed_rate_clks[8].hw }, +}; + +static const struct clk_parent_data vi_aclk_root_2mux1_gfree_mux_p[] = { + { .hw = &eic7700_fixed_rate_clks[1].hw }, + { .hw = &eic7700_fixed_rate_clks[7].hw }, +}; + +static const struct clk_parent_data mux_vi_dw_root_2mux1_p[] = { + { .hw = &eic7700_fixed_rate_clks[10].hw }, + { .hw = &eic7700_fixed_rate_clks[1].hw }, +}; + +static const struct clk_parent_data mux_vi_dvp_root_2mux1_gfree_p[] = { + { .hw = &eic7700_fixed_rate_clks[10].hw }, + { .hw = &eic7700_fixed_rate_clks[1].hw }, +}; + +static const struct clk_parent_data mux_vi_dig_isp_root_2mux1_gfree_p[] = { + { .hw = &eic7700_fixed_rate_clks[10].hw }, + { .hw = &eic7700_fixed_rate_clks[1].hw }, +}; + +static const struct clk_parent_data mux_vo_aclk_root_2mux1_gfree_p[] = { + { .hw = &eic7700_fixed_rate_clks[1].hw }, + { .hw = &eic7700_fixed_rate_clks[7].hw }, +}; + +static const struct clk_parent_data mux_vo_pixel_root_2mux1_p[] = { + { .hw = &eic7700_fixed_rate_clks[10].hw }, + { .hw = &eic7700_fixed_rate_clks[8].hw }, +}; + +static const struct clk_parent_data mux_vcdec_root_2mux1_gfree_p[] = { + { .hw = &eic7700_fixed_rate_clks[1].hw }, + { .hw = &eic7700_fixed_rate_clks[7].hw }, +}; + +static const struct clk_parent_data mux_vcaclk_root_2mux1_gfree_p[] = { + { .hw = &eic7700_fixed_rate_clks[1].hw }, + { .hw = &eic7700_fixed_rate_clks[7].hw }, +}; + +static const struct clk_parent_data npu_llclk_3mux1_gfree_mux_p[] = { + { .hw = &eic7700_early_clks[1].hw }, + { .hw = &eic7700_early_clks[2].hw }, + { .hw = &eic7700_fixed_rate_clks[10].hw }, +}; + +static const struct clk_parent_data mux_bootspi_clk_2mux1_gfree_p[] = { + { .hw = &eic7700_early_clks[4].hw }, + { .index = 0 }, +}; + +static const struct clk_parent_data mux_scpu_core_clk_2mux1_gfree_p[] = { + { .hw = &eic7700_early_clks[5].hw }, + { .index = 0 }, +}; + +static const struct clk_parent_data mux_lpcpu_core_clk_2mux1_gfree_p[] = { + { .hw = &eic7700_early_clks[6].hw }, + { .index = 0 }, +}; + +static const struct clk_parent_data mux_vo_mclk_2mux_ext_mclk_p[] = { + { .hw = &eic7700_early_clks[7].hw }, + { .hw = &eic7700_fixed_rate_clks[15].hw }, +}; + +static const struct clk_parent_data mux_aondma_axi2mux1_gfree_p[] = { + { .hw = &eic7700_early_clks[8].hw }, + { .index = 0 }, +}; + +static const struct clk_parent_data mux_rmii_ref_2mux1_p[] = { + { .hw = &eic7700_early_clks[0].hw }, + { .hw = &eic7700_fixed_rate_clks[16].hw }, +}; + +static const struct clk_parent_data mux_eth_core_2mux1_p[] = { + { .hw = &eic7700_fixed_rate_clks[6].hw }, + { .hw = &eic7700_fixed_rate_clks[16].hw }, +}; + +static const struct clk_parent_data mux_sata_phy_2mux1_p[] = { + { .hw = &eic7700_early_clks[9].hw }, + { .hw = &eic7700_fixed_rate_clks[16].hw }, +}; + +static const struct clk_parent_data mux_syscfg_clk_root_2mux1_gfree_p[] = { + { .hw = &eic7700_early_clks[10].hw }, + { .index = 0 }, +}; + +static const struct clk_parent_data mux_cpu_root_3mux1_gfree_p[] = { + { .hw = &eic7700_pll_clks[1].hw }, + { .hw = &eic7700_early_clks[11].hw }, + { .index = 0 }, +}; + +static struct eswin_mux_clock eic7700_mux_clks[] = { + ESWIN_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + "mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p, + ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 0, 2, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1", + mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 2, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, + "mux_dsp_aclk_root_2mux1_gfree", + dsp_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, + "mux_d2d_aclk_root_2mux1_gfree", + d2d_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, + "mux_ddr_aclk_root_2mux1_gfree", + ddr_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 16, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0, + "mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC0_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1, + "mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC1_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2, + "mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC2_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE, + "mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 0, 2, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE, + "mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE, 0, 2, CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, + "mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE, 8, 2, CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, + "mux_vi_aclk_root_2mux1_gfree", + vi_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1", + mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, + "mux_vi_dvp_root_2mux1_gfree", + mux_vi_dvp_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, + "mux_vi_dig_isp_root_2mux1_gfree", + mux_vi_dig_isp_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, + "mux_vo_aclk_root_2mux1_gfree", + mux_vo_aclk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, + "mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p, + ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PIXEL, 0, 1, CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, + "mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, + "mux_vcaclk_root_2mux1_gfree", + mux_vcaclk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + "mux_syscfg_clk_root_2mux1_gfree", + mux_syscfg_clk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE, + "mux_bootspi_clk_2mux1_gfree", + mux_bootspi_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, + "mux_scpu_core_clk_2mux1_gfree", + mux_scpu_core_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, + "mux_lpcpu_core_clk_2mux1_gfree", + mux_lpcpu_core_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK, + "mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p, + ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, + "mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p, + ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 0, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1", + mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 1, 1, + CLK_MUX_ROUND_CLOSEST), + ESWIN_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1", + mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 9, 1, + CLK_MUX_ROUND_CLOSEST), +}; + +static const struct clk_parent_data mux_cpu_aclk_2mux1_gfree_p[] = { + { .hw = &eic7700_mux_clks[1].hw }, + { .hw = &eic7700_mux_clks[0].hw }, +}; + +static struct eswin_clk_info eic7700_clks[] = { + ESWIN_MUX_TYPE(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE, + "mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p, + ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 20, 1, + CLK_MUX_ROUND_CLOSEST, NULL), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK, + "gate_clk_cpu_trace_com_clk", + EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 23, 0), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2, + "fixed_factor_cpu_div2", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 1, 2, 0), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, + "fixed_factor_mipi_txesc_div10", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 10, + 0), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2, + "fixed_factor_scpu_bus_div2", + EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2, + "fixed_factor_lpcpu_bus_div2", + EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2, + "fixed_factor_pcie_cr_div2", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 2, 0), + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4, + "fixed_factor_pcie_aux_div4", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 4, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_D2D_ACLK_DYNM, + "divider_d2d_aclk_div_dynm", + EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_D2D_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_ACLK_DYNM, + "divider_dsp_aclk_div_dynm", + EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_DSP_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DDR_ACLK_DYNM, + "divider_ddr_aclk_div_dynm", + EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_DDR, 20, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, + "divider_eth_txclk_div_dynm_0", + EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0, + EIC7700_REG_OFFSET_ETH0, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, + "divider_eth_txclk_div_dynm_1", + EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0, + EIC7700_REG_OFFSET_ETH1, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, + "divider_mshc_core_div_dynm_0", + EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0, + 0, EIC7700_REG_OFFSET_MSHC0_CORE, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, + "divider_mshc_core_div_dynm_1", + EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1, + 0, EIC7700_REG_OFFSET_MSHC1_CORE, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, + "divider_mshc_core_div_dynm_2", + EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2, + 0, EIC7700_REG_OFFSET_MSHC2_CORE, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_CORECLK_DYNM, + "divider_npu_coreclk_div_dynm", + EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE, + 0, EIC7700_REG_OFFSET_NPU_CORE, 4, 4, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm", + EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, 0, + EIC7700_REG_OFFSET_NPU_CORE, 12, 4, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm", + EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VI_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm", + EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, 0, + EIC7700_REG_OFFSET_VI_DWCLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm", + EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VI_DVP, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, + "divider_vi_dig_isp_div_dynm", + EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VI_DIG_ISP, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm", + EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VO_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_PIXEL_DYNM, + "divider_vo_pixel_div_dynm", + EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, 0, + EIC7700_REG_OFFSET_VO_PIXEL, 4, 6, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm", + EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VC_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm", + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_JD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm", + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_JE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm", + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm", + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_VD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm", + EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0, + EIC7700_REG_OFFSET_G2D, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm", + EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NOC, 0, 3, + 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_GPU_ACLK_DYNM, + "divider_gpu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, + EIC7700_REG_OFFSET_GPU_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_HSP_ACLK_DYNM, + "divider_hsp_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, + EIC7700_REG_OFFSET_HSP_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_PCIE_ACLK_DYNM, + "divider_pcie_aclk_div_dynm", EIC7700_CLK_SPLL2_FOUT2, 0, + EIC7700_REG_OFFSET_PCIE_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_ACLK_DYNM, + "divider_npu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, + EIC7700_REG_OFFSET_NPU_ACLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, + "divider_vi_shutter_div_dynm_0", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, + "divider_vi_shutter_div_dynm_1", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, + "divider_vi_shutter_div_dynm_2", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, + "divider_vi_shutter_div_dynm_3", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, + "divider_vi_shutter_div_dynm_4", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, + "divider_vi_shutter_div_dynm_5", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm", + EIC7700_CLK_SPLL0_FOUT3, 0, + EIC7700_REG_OFFSET_VO_IESMCLK, 4, 4, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm", + EIC7700_CLK_VPLL_FOUT2, 0, + EIC7700_REG_OFFSET_VO_PHY_CLK, 16, 16, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm", + EIC7700_CLK_SPLL0_FOUT1, 0, + EIC7700_REG_OFFSET_SPACC, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm", + EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, 0, + EIC7700_REG_OFFSET_RTC, 21, 11, 0, + ESWIN_PRIV_DIV_MIN_2), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk", + EIC7700_CLK_DIV_DSP_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DSP_ACLK, 31, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM, + "divider_dsp_0_aclk_div_dynm", + EIC7700_CLK_GATE_DSPT_ACLK, 0, + EIC7700_REG_OFFSET_DSP_CFG, 19, 1, 0, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM, + "divider_dsp_1_aclk_div_dynm", + EIC7700_CLK_GATE_DSPT_ACLK, 0, + EIC7700_REG_OFFSET_DSP_CFG, 20, 1, 0, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM, + "divider_dsp_2_aclk_div_dynm", + EIC7700_CLK_GATE_DSPT_ACLK, 0, + EIC7700_REG_OFFSET_DSP_CFG, 21, 1, 0, 0), + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM, + "divider_dsp_3_aclk_div_dynm", + EIC7700_CLK_GATE_DSPT_ACLK, 0, + EIC7700_REG_OFFSET_DSP_CFG, 22, 1, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0, + "gate_clk_cpu_ext_src_core_clk_0", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_U84, 28, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1, + "gate_clk_cpu_ext_src_core_clk_1", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_U84, 29, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2, + "gate_clk_cpu_ext_src_core_clk_2", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_U84, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3, + "gate_clk_cpu_ext_src_core_clk_3", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_U84, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0, + "gate_clk_cpu_trace_clk_0", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 24, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1, + "gate_clk_cpu_trace_clk_1", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 25, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2, + "gate_clk_cpu_trace_clk_2", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 26, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3, + "gate_clk_cpu_trace_clk_3", + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 27, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk", + EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NOC, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi", + EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CFGCLK, + 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core", + EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 31, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus", + EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_BUSCLK, 31, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core", + EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 31, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus", + EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_BUSCLK, + 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk", + EIC7700_CLK_DIV_GPU_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_CFG, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_CFG, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk", + EIC7700_CLK_DIV_D2D_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_D2D_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_CFG, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TCU_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TCU_CFG, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 9, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR, 4, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR, 5, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR, 6, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR, 7, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR, 8, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR1, 4, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR1, 5, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR1, 6, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR1, 7, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_DDR1, 8, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk", + EIC7700_CLK_DIV_HSP_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_CFG, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk", + EIC7700_CLK_DIV_PCIE_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 31, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk", + EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk", + EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 1, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk", + EIC7700_CLK_DIV_NPU_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_ACLK, 30, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk", + EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk", + EIC7700_CLK_DIV_NPU_CORECLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk", + EIC7700_CLK_DIV_NPU_E31_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk", + EIC7700_CLK_DIV_VI_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk", + EIC7700_CLK_DIV_VI_DW_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DWCLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk", + EIC7700_CLK_DIV_VI_DVP_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DVP, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk", + EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DIG_ISP, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0", + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1", + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2", + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3", + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4", + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5", + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC, + "gate_vi_phy_txclkesc", + EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk", + EIC7700_CLK_DIV_VO_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK, + "gate_vo_hdmi_iesmclk", EIC7700_CLK_DIV_IESMCLK_DYNM, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_IESMCLK, 31, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk", + EIC7700_CLK_DIV_VO_PIXEL_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PIXEL, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk", + EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk", + EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_PHY_CLK, 1, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk", + EIC7700_CLK_DIV_VC_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_ACLK, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk", + EIC7700_CLK_DIV_JE_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_JE, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk", + EIC7700_CLK_DIV_JD_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_JD, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk", + EIC7700_CLK_DIV_VE_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VE, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk", + EIC7700_CLK_DIV_VD_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VD, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_G2D, 28, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk", + EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk", + EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk", + EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk", + EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 29, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 4, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 5, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 6, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 7, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8", + EIC7700_CLK_VPLL_FOUT3, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER, 8, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_RTC, 2, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc", + EIC7700_CLK_DIV_AON_RTC_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_RTC, 1, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0", + EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH0, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1", + EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH1, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PKA, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SPACC, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto", + EIC7700_CLK_DIV_CRYPTO_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPACC, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TRNG, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_OTP, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 1, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 2, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 3, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 4, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 5, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 6, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 7, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 8, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 9, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 10, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 11, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 12, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 13, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 14, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 15, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 7, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 8, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 9, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 10, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 11, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 12, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 13, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 14, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 15, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 16, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 28, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 29, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 30, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 26, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 27, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_LSP_EN0, 17, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 18, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_LSP_EN0, 19, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 20, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 21, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + EIC7700_REG_OFFSET_LSP_EN0, 25, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 1, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk", + EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 16, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk", + EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 17, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 2, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 1, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 5, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 4, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 3, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK, + "gate_hsp_mshc0_core_clk", + EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC0_CORE, 16, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK, + "gate_hsp_mshc1_core_clk", + EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC1_CORE, 16, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK, + "gate_hsp_mshc2_core_clk", + EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC2_CORE, 16, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK, + "gate_hsp_sata_rbc_clk", EIC7700_CLK_SPLL1_FOUT2, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_RBC, + 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK, + "gate_hsp_sata_oob_clk", EIC7700_CLK_MUX_SATA_PHY_2MUX1, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 31, + 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST, + "gate_hsp_dma0_clk_test", EIC7700_CLK_GATE_HSP_ACLK, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK, 1, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk", + EIC7700_CLK_GATE_HSP_ACLK, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_ACLK, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK, + "gate_hsp_eth0_core_clk", + EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH0, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK, + "gate_hsp_eth1_core_clk", + EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH1, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C0, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk", + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C1, 31, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR0_TRACE, "gate_ddr0_trace", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR1_TRACE, "gate_ddr1_trace", + EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1, 0, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RNOC_NSP, "gate_rnoc_nsp", + EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NOC, 29, 0), + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_WDREF, "gate_noc_wdref", + EIC7700_CLK_DIV_NOC_WDREF_DYNM, CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NOC, 30, 0), +}; + +/* + * This clock notifier is called when the rate of clk_pll_cpu clock is to be + * changed. The mux_cpu_root_3mux1_gfree clock should save the current parent + * clock and switch its parent clock to fixed_factor_u84_core_lp_div2 before + * clk_pll_cpu rate will be changed. Then switch its parent clock back after + * the clk_pll_cpu rate is completed. + */ +static int eic7700_clk_pll_cpu_notifier_cb(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct eswin_clock_data *pdata; + struct clk_hw *mux_clk; + struct clk_hw *lp_clk; + int ret = 0; + + pdata = container_of(nb, struct eswin_clock_data, pll_nb); + + mux_clk = &eic7700_mux_clks[0].hw; + lp_clk = &eic7700_early_clks[11].hw; + + if (action == PRE_RATE_CHANGE) { + pdata->original_clk = clk_hw_get_parent(mux_clk); + ret = clk_hw_set_parent(mux_clk, lp_clk); + } else if (action == POST_RATE_CHANGE) { + ret = clk_hw_set_parent(mux_clk, pdata->original_clk); + } + + return notifier_from_errno(ret); +} + +static int eic7700_clk_probe(struct platform_device *pdev) +{ + struct eswin_clock_data *clk_data; + struct device *dev = &pdev->dev; + struct clk *pll_clk; + int ret; + + clk_data = eswin_clk_init(pdev, EIC7700_NR_CLKS); + if (IS_ERR(clk_data)) + return dev_err_probe(dev, PTR_ERR(clk_data), + "failed to get clk data!\n"); + + ret = eswin_clk_register_fixed_rate(dev, eic7700_fixed_rate_clks, + ARRAY_SIZE(eic7700_fixed_rate_clks), + clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register fixed rate clock\n"); + + ret = eswin_clk_register_pll(dev, eic7700_pll_clks, + ARRAY_SIZE(eic7700_pll_clks), + clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register pll clock\n"); + + pll_clk = devm_clk_hw_get_clk(dev, &eic7700_pll_clks[1].hw, + "clk_pll_cpu"); + if (IS_ERR(pll_clk)) + return dev_err_probe(dev, PTR_ERR(pll_clk), + "failed to get clk_pll_cpu\n"); + + clk_data->pll_nb.notifier_call = eic7700_clk_pll_cpu_notifier_cb; + ret = devm_clk_notifier_register(dev, pll_clk, &clk_data->pll_nb); + if (ret) + return ret; + + ret = eswin_clk_register_fixed_factor(dev, eic7700_factor_clks, + ARRAY_SIZE(eic7700_factor_clks), + clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register fixed factor clock\n"); + + ret = eswin_clk_register_divider(dev, eic7700_div_clks, + ARRAY_SIZE(eic7700_div_clks), + clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register divider clock\n"); + + ret = eswin_clk_register_gate(dev, eic7700_gate_clks, + ARRAY_SIZE(eic7700_gate_clks), clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register gate clock\n"); + + ret = eswin_clk_register_clks(dev, eic7700_early_clks, + ARRAY_SIZE(eic7700_early_clks), clk_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register clock\n"); + + ret = eswin_clk_register_mux(dev, eic7700_mux_clks, + ARRAY_SIZE(eic7700_mux_clks), clk_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register mux clock\n"); + + ret = eswin_clk_register_clks(dev, eic7700_clks, + ARRAY_SIZE(eic7700_clks), clk_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register clock\n"); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &clk_data->clk_data); +} + +static const struct of_device_id eic7700_clock_dt_ids[] = { + { .compatible = "eswin,eic7700-clock", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids); + +static struct platform_driver eic7700_clock_driver = { + .probe = eic7700_clk_probe, + .driver = { + .name = "eic7700-clock", + .of_match_table = eic7700_clock_dt_ids, + }, +}; +module_platform_driver(eic7700_clock_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Yifeng Huang<huangyifeng@eswincomputing.com>"); +MODULE_AUTHOR("Xuyang Dong<dongxuyang@eswincomputing.com>"); +MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver"); diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/iopoll.h> +#include <linux/math.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "common.h" + +#define PLL_EN_MASK GENMASK(1, 0) +#define PLL_REFDIV_MASK GENMASK(17, 12) +#define PLL_FBDIV_MASK GENMASK(31, 20) +#define PLL_FRAC_MASK GENMASK(27, 4) +#define PLL_POSTDIV1_MASK GENMASK(10, 8) +#define PLL_POSTDIV2_MASK GENMASK(18, 16) + +struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev, + size_t nr_clks) +{ + struct eswin_clock_data *eclk_data; + + eclk_data = devm_kzalloc(&pdev->dev, + struct_size(eclk_data, clk_data.hws, nr_clks), + GFP_KERNEL); + if (!eclk_data) + return ERR_PTR(-ENOMEM); + + eclk_data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(eclk_data->base)) + return ERR_PTR(-EINVAL); + + eclk_data->clk_data.num = nr_clks; + /* Avoid returning NULL for unused id */ + memset_p((void **)eclk_data->clk_data.hws, ERR_PTR(-ENOENT), nr_clks); + spin_lock_init(&eclk_data->lock); + + return eclk_data; +} +EXPORT_SYMBOL_GPL(eswin_clk_init); + +/** + * eswin_calc_pll - calculate PLL values + * @frac_val: fractional divider + * @fbdiv_val: feedback divider + * @rate: reference rate + * @parent_rate: parent rate + * + * Calculate PLL values for frac and fbdiv: + * fbdiv = rate * 4 / parent_rate + * frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate + */ +static void eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, unsigned long rate, + unsigned long parent_rate) +{ + u32 rem; + u64 tmp; + + /* step 1: rate * 4 */ + tmp = rate * 4; + /* step 2: use do_div() to get the quotient(tmp) and remainder(rem) */ + rem = do_div(tmp, (u32)parent_rate); + /* fbdiv = rate * 4 / parent_rate */ + *fbdiv_val = (u32)tmp; + /* + * step 3: rem << 24 + * 24: 24-bit fractional accuracy + */ + tmp = (u64)rem << 24; + /* step 4: use do_div() to get the quotient(tmp) */ + do_div(tmp, (u32)parent_rate); + /* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate */ + *frac_val = (u32)tmp; +} + +static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw) +{ + return container_of(hw, struct eswin_clk_pll, hw); +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + u32 frac_val, fbdiv_val, val, mask; + int ret; + + eswin_calc_pll(&frac_val, &fbdiv_val, rate, parent_rate); + + /* First, disable pll */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~PLL_EN_MASK; + val |= FIELD_PREP(PLL_EN_MASK, 0); + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK); + val |= FIELD_PREP(PLL_FBDIV_MASK, fbdiv_val); + val |= FIELD_PREP(PLL_REFDIV_MASK, 1); + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg1); + val &= ~PLL_FRAC_MASK; + val |= FIELD_PREP(PLL_FRAC_MASK, frac_val); + writel_relaxed(val, clk->ctrl_reg1); + + val = readl_relaxed(clk->ctrl_reg2); + val &= ~(PLL_POSTDIV1_MASK | PLL_POSTDIV2_MASK); + val |= FIELD_PREP(PLL_POSTDIV1_MASK, 1); + val |= FIELD_PREP(PLL_POSTDIV2_MASK, 1); + writel_relaxed(val, clk->ctrl_reg2); + + /* Last, enable pll */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~PLL_EN_MASK; + val |= FIELD_PREP(PLL_EN_MASK, 1); + writel_relaxed(val, clk->ctrl_reg0); + + /* Usually the pll will lock in 50us */ + mask = GENMASK(clk->lock_shift + clk->lock_width - 1, clk->lock_shift); + ret = readl_poll_timeout(clk->status_reg, val, val & mask, 1, 50 * 2); + if (ret) + pr_err("failed to lock the pll!\n"); + + return ret; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + u64 fbdiv_val, frac_val, tmp; + u32 rem, val; + + val = readl_relaxed(clk->ctrl_reg0); + val &= PLL_FBDIV_MASK; + fbdiv_val = (val >> clk->fbdiv_shift); + + val = readl_relaxed(clk->ctrl_reg1); + val &= PLL_FRAC_MASK; + frac_val = (val >> clk->frac_shift); + + /* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */ + tmp = parent_rate * frac_val; + rem = do_div(tmp, BIT(24)); + if (rem) + tmp = parent_rate * fbdiv_val + tmp + 1; + else + tmp = parent_rate * fbdiv_val + tmp; + + do_div(tmp, 4); + + return tmp; +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + + req->rate = clamp(req->rate, clk->min_rate, clk->max_rate); + req->min_rate = clk->min_rate; + req->max_rate = clk->max_rate; + + return 0; +} + +int eswin_clk_register_fixed_rate(struct device *dev, + struct eswin_fixed_rate_clock *clks, + int nums, struct eswin_clock_data *data) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name, + NULL, clks[i].flags, + clks[i].rate); + if (IS_ERR(clk_hw)) + return PTR_ERR(clk_hw); + + clks[i].hw = *clk_hw; + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate); + +static const struct clk_ops eswin_clk_pll_ops = { + .set_rate = clk_pll_set_rate, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, +}; + +int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks, + int nums, struct eswin_clock_data *data) +{ + struct eswin_clk_pll *p_clk = NULL; + struct clk_init_data init; + struct clk_hw *clk_hw; + int i, ret; + + p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); + if (!p_clk) + return -ENOMEM; + + for (i = 0; i < nums; i++) { + p_clk->id = clks[i].id; + p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0; + p_clk->fbdiv_shift = clks[i].fbdiv_shift; + + p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1; + p_clk->frac_shift = clks[i].frac_shift; + + p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2; + + p_clk->status_reg = data->base + clks[i].status_reg; + p_clk->lock_shift = clks[i].lock_shift; + p_clk->lock_width = clks[i].lock_width; + + p_clk->max_rate = clks[i].max_rate; + p_clk->min_rate = clks[i].min_rate; + + init.name = clks[i].name; + init.flags = 0; + init.parent_data = clks[i].parent_data; + init.num_parents = 1; + init.ops = &eswin_clk_pll_ops; + p_clk->hw.init = &init; + + clk_hw = &p_clk->hw; + + ret = devm_clk_hw_register(dev, clk_hw); + if (ret) + return ret; + + clks[i].hw = *clk_hw; + data->clk_data.hws[clks[i].id] = clk_hw; + p_clk++; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_pll); + +int eswin_clk_register_fixed_factor(struct device *dev, + struct eswin_fixed_factor_clock *clks, + int nums, struct eswin_clock_data *data) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_fixed_factor_index(dev, clks[i].name, + clks[i].parent_data->index, + clks[i].flags, clks[i].mult, + clks[i].div); + + if (IS_ERR(clk_hw)) + return PTR_ERR(clk_hw); + + clks[i].hw = *clk_hw; + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_factor); + +int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks, + int nums, struct eswin_clock_data *data) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_mux_parent_data_table(dev, clks[i].name, + clks[i].parent_data, + clks[i].num_parents, + clks[i].flags, + data->base + clks[i].reg, + clks[i].shift, clks[i].width, + clks[i].mux_flags, + clks[i].table, &data->lock); + + if (IS_ERR(clk_hw)) + return PTR_ERR(clk_hw); + + clks[i].hw = *clk_hw; + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_mux); + +static unsigned int _eswin_get_val(unsigned int div, unsigned long flags, + u8 width) +{ + unsigned int maxdiv; + + maxdiv = clk_div_mask(width); + div = div > maxdiv ? maxdiv : div; + + if (flags & ESWIN_PRIV_DIV_MIN_2) + return (div < 2) ? 2 : div; + + return div; +} + +static unsigned int eswin_div_get_val(unsigned long rate, + unsigned long parent_rate, u8 width, + unsigned long flags) +{ + unsigned int div; + + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + + return _eswin_get_val(div, flags, width); +} + +static inline struct eswin_divider_clock *to_div_clk(struct clk_hw *hw) +{ + return container_of(hw, struct eswin_divider_clock, hw); +} + +static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct eswin_divider_clock *dclk = to_div_clk(hw); + unsigned long flags; + unsigned int value; + u32 val; + + value = eswin_div_get_val(rate, parent_rate, dclk->width, + dclk->priv_flag); + + spin_lock_irqsave(dclk->lock, flags); + + val = readl_relaxed(dclk->ctrl_reg); + val &= ~(clk_div_mask(dclk->width) << dclk->shift); + val |= (u32)value << dclk->shift; + writel_relaxed(val, dclk->ctrl_reg); + + spin_unlock_irqrestore(dclk->lock, flags); + + return 0; +} + +static unsigned long clk_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct eswin_divider_clock *dclk = to_div_clk(hw); + unsigned int div, val; + + val = readl_relaxed(dclk->ctrl_reg) >> dclk->shift; + val &= clk_div_mask(dclk->width); + div = _eswin_get_val(val, dclk->priv_flag, dclk->width); + + return DIV_ROUND_UP_ULL((u64)parent_rate, div); +} + +static int eswin_clk_bestdiv(unsigned long rate, + unsigned long best_parent_rate, u8 width, + unsigned long flags) +{ + unsigned long bestdiv, up_rate, down_rate; + int up, down; + + if (!rate) + rate = 1; + + /* closest round */ + up = DIV_ROUND_UP_ULL((u64)best_parent_rate, rate); + down = best_parent_rate / rate; + + up_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, up); + down_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, down); + + bestdiv = (rate - up_rate) <= (down_rate - rate) ? up : down; + + return bestdiv; +} + +static int clk_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct eswin_divider_clock *dclk = to_div_clk(hw); + int div; + + div = eswin_clk_bestdiv(req->rate, req->best_parent_rate, dclk->width, + dclk->priv_flag); + div = _eswin_get_val(div, dclk->priv_flag, dclk->width); + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} + +static const struct clk_ops eswin_clk_div_ops = { + .set_rate = clk_div_set_rate, + .recalc_rate = clk_div_recalc_rate, + .determine_rate = clk_div_determine_rate, +}; + +struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id, + const char *name, + const struct clk_hw *parent_hw, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, + unsigned long clk_divider_flags, + unsigned long priv_flag, spinlock_t *lock) +{ + struct eswin_divider_clock *dclk; + struct clk_init_data init; + struct clk_hw *clk_hw; + int ret; + + dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL); + if (!dclk) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &eswin_clk_div_ops; + init.flags = flags; + init.parent_hws = &parent_hw; + init.num_parents = 1; + + /* struct clk_divider assignments */ + dclk->id = id; + dclk->ctrl_reg = reg; + dclk->shift = shift; + dclk->width = width; + dclk->div_flags = clk_divider_flags; + dclk->priv_flag = priv_flag; + dclk->lock = lock; + dclk->hw.init = &init; + + /* register the clock */ + clk_hw = &dclk->hw; + ret = devm_clk_hw_register(dev, clk_hw); + if (ret) { + dev_err(dev, "failed to register divider clock!\n"); + return ERR_PTR(ret); + } + + return clk_hw; +} +EXPORT_SYMBOL_GPL(eswin_register_clkdiv); + +int eswin_clk_register_divider(struct device *dev, + struct eswin_divider_clock *clks, + int nums, struct eswin_clock_data *data) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_divider_parent_data(dev, clks[i].name, + clks[i].parent_data, + clks[i].flags, + data->base + clks[i].reg, + clks[i].shift, clks[i].width, + clks[i].div_flags, &data->lock); + + if (IS_ERR(clk_hw)) + return PTR_ERR(clk_hw); + + clks[i].hw = *clk_hw; + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_divider); + +int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks, + int nums, struct eswin_clock_data *data) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_gate_parent_data(dev, clks[i].name, + clks[i].parent_data, + clks[i].flags, + data->base + clks[i].reg, + clks[i].bit_idx, clks[i].gate_flags, + &data->lock); + + if (IS_ERR(clk_hw)) + return PTR_ERR(clk_hw); + + clks[i].hw = *clk_hw; + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_gate); + +int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks, + int nums, struct eswin_clock_data *data) +{ + struct eswin_clk_info *info; + const struct clk_hw *phw = NULL; + struct clk_hw *hw; + int i; + + for (i = 0; i < nums; i++) { + info = &clks[i]; + switch (info->type) { + case CLK_FIXED_FACTOR: { + const struct eswin_fixed_factor_clock *factor; + + factor = &info->data.factor; + phw = data->clk_data.hws[info->pid]; + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, factor->name, phw, + factor->flags, + factor->mult, + factor->div); + break; + } + case CLK_MUX: { + const struct eswin_mux_clock *mux = &info->data.mux; + + hw = devm_clk_hw_register_mux_parent_data_table(dev, mux->name, + mux->parent_data, + mux->num_parents, + mux->flags, + data->base + mux->reg, + mux->shift, mux->width, + mux->mux_flags, + mux->table, &data->lock); + break; + } + case CLK_DIVIDER: { + const struct eswin_divider_clock *div = &info->data.div; + + phw = data->clk_data.hws[info->pid]; + if (div->priv_flag) + hw = eswin_register_clkdiv(dev, div->id, div->name, phw, + div->flags, data->base + div->reg, + div->shift, div->width, div->div_flags, + div->priv_flag, &data->lock); + else + hw = devm_clk_hw_register_divider_parent_hw(dev, div->name, phw, + div->flags, + data->base + div->reg, + div->shift, div->width, + div->div_flags, + &data->lock); + break; + } + case CLK_GATE: { + const struct eswin_gate_clock *gate = &info->data.gate; + + phw = data->clk_data.hws[info->pid]; + hw = devm_clk_hw_register_gate_parent_hw(dev, gate->name, phw, + gate->flags, + data->base + gate->reg, + gate->bit_idx, gate->gate_flags, + &data->lock); + break; + } + default: + dev_err(dev, "Unidentifiable clock type!\n"); + return -EINVAL; + } + if (IS_ERR(hw)) + return PTR_ERR(hw); + + info->hw = *hw; + data->clk_data.hws[info->id] = hw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(eswin_clk_register_clks); diff --git a/drivers/clk/eswin/common.h b/drivers/clk/eswin/common.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/common.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __ESWIN_COMMON_H__ +#define __ESWIN_COMMON_H__ + +#define APLL_HIGH_FREQ 983040000 +#define APLL_LOW_FREQ 225792000 +#define PLL_HIGH_FREQ 1800000000 +#define PLL_LOW_FREQ 24000000 + +/* + * ESWIN_PRIV_DIV_MIN_2: If ESWIN_PRIV_DIV_MIN_2 is set, the minimum value of + * the register is 2, i.e. the minimum division ratio is 2. + */ +#define ESWIN_PRIV_DIV_MIN_2 BIT(0) + +enum eswin_clk_type { + CLK_FIXED_FACTOR, + CLK_MUX, + CLK_DIVIDER, + CLK_GATE, +}; + +struct eswin_clock_data { + void __iomem *base; + struct clk_hw *original_clk; + struct notifier_block pll_nb; + spinlock_t lock; /* protect register read-modify-write cycle */ + struct clk_hw_onecell_data clk_data; +}; + +struct eswin_divider_clock { + struct clk_hw hw; + unsigned int id; + const char *name; + const struct clk_parent_data *parent_data; + void __iomem *ctrl_reg; /* register address of the divider clock */ + unsigned long flags; + unsigned long reg; /* register offset */ + u8 shift; + u8 width; + unsigned long div_flags; + unsigned long priv_flag; + spinlock_t *lock; /* protect register read-modify-write cycle */ +}; + +struct eswin_fixed_rate_clock { + struct clk_hw hw; + unsigned int id; + const char *name; + unsigned long flags; + unsigned long rate; +}; + +struct eswin_fixed_factor_clock { + struct clk_hw hw; + unsigned int id; + const char *name; + const struct clk_parent_data *parent_data; + unsigned long mult; + unsigned long div; + unsigned long flags; +}; + +struct eswin_gate_clock { + struct clk_hw hw; + unsigned int id; + const char *name; + const struct clk_parent_data *parent_data; + unsigned long flags; + unsigned long reg; + u8 bit_idx; + u8 gate_flags; +}; + +struct eswin_mux_clock { + struct clk_hw hw; + unsigned int id; + const char *name; + const struct clk_parent_data *parent_data; + u8 num_parents; + unsigned long flags; + unsigned long reg; + u8 shift; + u8 width; + u8 mux_flags; + u32 *table; +}; + +struct eswin_pll_clock { + struct clk_hw hw; + u32 id; + const char *name; + const struct clk_parent_data *parent_data; + const u32 ctrl_reg0; + const u8 fbdiv_shift; + + const u32 ctrl_reg1; + const u8 frac_shift; + + const u32 ctrl_reg2; + + const u32 status_reg; + const u8 lock_shift; + const u8 lock_width; + + const u64 max_rate; + const u64 min_rate; +}; + +struct eswin_clk_pll { + struct clk_hw hw; + u32 id; + void __iomem *ctrl_reg0; + u8 fbdiv_shift; + + void __iomem *ctrl_reg1; + u8 frac_shift; + + void __iomem *ctrl_reg2; + + void __iomem *status_reg; + u8 lock_shift; + u8 lock_width; + + u64 max_rate; + u64 min_rate; +}; + +struct eswin_clk_info { + unsigned int type; + unsigned int pid; + unsigned int id; + struct clk_hw hw; + union { + struct eswin_divider_clock div; + struct eswin_fixed_factor_clock factor; + struct eswin_gate_clock gate; + struct eswin_mux_clock mux; + } data; +}; + +struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev, + size_t nr_clks); +int eswin_clk_register_fixed_rate(struct device *dev, + struct eswin_fixed_rate_clock *clks, + int nums, struct eswin_clock_data *data); +int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks, + int nums, struct eswin_clock_data *data); +int eswin_clk_register_fixed_factor(struct device *dev, + struct eswin_fixed_factor_clock *clks, + int nums, struct eswin_clock_data *data); +int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks, + int nums, struct eswin_clock_data *data); +int eswin_clk_register_divider(struct device *dev, + struct eswin_divider_clock *clks, + int nums, struct eswin_clock_data *data); +int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks, + int nums, struct eswin_clock_data *data); +int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks, + int nums, struct eswin_clock_data *data); +struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id, + const char *name, + const struct clk_hw *parent_hw, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, + unsigned long clk_divider_flags, + unsigned long priv_flag, spinlock_t *lock); + +#define ESWIN_DIV(_id, _name, _pdata, _flags, _reg, _shift, _width, \ + _dflags, _pflag) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_data = _pdata, \ + .flags = _flags, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _dflags, \ + .priv_flag = _pflag, \ + } + +#define ESWIN_DIV_TYPE(_id, _name, _pid, _flags, _reg, _shift, _width, \ + _dflags, _pflag) \ + { \ + .type = CLK_DIVIDER, \ + .pid = _pid, \ + .id = _id, \ + .data = { \ + .div = { \ + .name = _name, \ + .flags = _flags, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _dflags, \ + .priv_flag = _pflag, \ + }, \ + }, \ + } + +#define ESWIN_FACTOR(_id, _name, _pdata, _mult, _div, _flags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_data = _pdata, \ + .mult = _mult, \ + .div = _div, \ + .flags = _flags, \ + } + +#define ESWIN_FACTOR_TYPE(_id, _name, _pid, _mult, _div, _flags) \ + { \ + .type = CLK_FIXED_FACTOR, \ + .pid = _pid, \ + .id = _id, \ + .data = { \ + .factor = { \ + .name = _name, \ + .mult = _mult, \ + .div = _div, \ + .flags = _flags, \ + }, \ + }, \ + } + +#define ESWIN_FIXED(_id, _name, _flags, _rate) \ + { \ + .id = _id, \ + .name = _name, \ + .flags = _flags, \ + .rate = _rate, \ + } + +#define ESWIN_GATE(_id, _name, _pdata, _flags, _reg, _idx, _gflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_data = _pdata, \ + .flags = _flags, \ + .reg = _reg, \ + .bit_idx = _idx, \ + .gate_flags = _gflags, \ + } + +#define ESWIN_GATE_TYPE(_id, _name, _pid, _flags, _reg, _idx, _gflags) \ + { \ + .type = CLK_GATE, \ + .pid = _pid, \ + .id = _id, \ + .data = { \ + .gate = { \ + .name = _name, \ + .flags = _flags, \ + .reg = _reg, \ + .bit_idx = _idx, \ + .gate_flags = _gflags, \ + }, \ + }, \ + } + +#define ESWIN_MUX(_id, _name, _pdata, _num_parents, _flags, _reg, \ + _shift, _width, _mflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_data = _pdata, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + .table = NULL, \ + } + +#define ESWIN_MUX_TBL(_id, _name, _pdata, _num_parents, _flags, _reg, \ + _shift, _width, _mflags, _table) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_data = _pdata, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + .table = _table, \ + } + +#define ESWIN_MUX_TYPE(_id, _name, _pdata, _num_parents, _flags, _reg, \ + _shift, _width, _mflags, _table) \ + { \ + .type = CLK_MUX, \ + .id = _id, \ + .data = { \ + .mux = { \ + .name = _name, \ + .parent_data = _pdata, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + .table = _table, \ + }, \ + }, \ + } + +#define ESWIN_PLL(_id, _name, _pdata, _reg0, _fb_shift, _reg1, \ + _frac_shift, _reg2, _reg, _lock_shift, _lock_width, \ + _max_rate, _min_rate) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_data = _pdata, \ + .ctrl_reg0 = _reg0, \ + .fbdiv_shift = _fb_shift, \ + .ctrl_reg1 = _reg1, \ + .frac_shift = _frac_shift, \ + .ctrl_reg2 = _reg2, \ + .status_reg = _reg, \ + .lock_shift = _lock_shift, \ + .lock_width = _lock_width, \ + .max_rate = _max_rate, \ + .min_rate = _min_rate, \ + } + +#endif /* __ESWIN_COMMON_H__ */ -- 2.34.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add myself as maintainer of ESWIN EIC7700 clock driver Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ T: git https://github.com/eswincomputing/linux-next.git F: Documentation/devicetree/bindings/riscv/eswin.yaml F: arch/riscv/boot/dts/eswin/ +ESWIN EIC7700 CLOCK DRIVER +M: Yifeng Huang <huangyifeng@eswincomputing.com> +M: Xuyang Dong <dongxuyang@eswincomputing.com> +S: Maintained +F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml +F: drivers/clk/eswin/ +F: include/dt-bindings/clock/eswin,eic7700-clock.h + ET131X NETWORK DRIVER M: Mark Einon <mark.einon@gmail.com> S: Odd Fixes -- 2.34.1