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Wed, 12 Nov 2025 14:57:26 -0800 (PST) From: Antoni Pokusinski To: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, marcelo.schmitt1@gmail.com Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Antoni Pokusinski Subject: [PATCH v4 2/3] iio: mpl3115: add threshold events support Date: Wed, 12 Nov 2025 23:57:00 +0100 Message-Id: <20251112225701.32158-3-apokusinski01@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251112225701.32158-1-apokusinski01@gmail.com> References: <20251112225701.32158-1-apokusinski01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for pressure and temperature rising threshold events. For both channels *_en and *_value (in raw units) attributes are exposed. Since in write_event_config() the ctrl_reg1.active and ctrl_reg4 are modified, accessing the data->ctrl_reg{1,4} in set_trigger_state() and write_event_config() needs to be now guarded by data->lock. Otherwise, it would be possible that 2 concurrent threads executing these functions would access the data->ctrl_reg{1,4} at the same time and then one would overwrite the other's result. Signed-off-by: Antoni Pokusinski --- drivers/iio/pressure/mpl3115.c | 221 +++++++++++++++++++++++++++++++-- 1 file changed, 211 insertions(+), 10 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index 5594256fffbd..aeac1586f12e 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -14,11 +14,13 @@ #include #include #include +#include #include #include #include =20 #include +#include #include #include #include @@ -31,6 +33,8 @@ #define MPL3115_WHO_AM_I 0x0c #define MPL3115_INT_SOURCE 0x12 #define MPL3115_PT_DATA_CFG 0x13 +#define MPL3115_PRESS_TGT 0x16 /* MSB first, 16 bit */ +#define MPL3115_TEMP_TGT 0x18 #define MPL3115_CTRL_REG1 0x26 #define MPL3115_CTRL_REG2 0x27 #define MPL3115_CTRL_REG3 0x28 @@ -43,6 +47,8 @@ #define MPL3115_STATUS_TEMP_RDY BIT(1) =20 #define MPL3115_INT_SRC_DRDY BIT(7) +#define MPL3115_INT_SRC_PTH BIT(3) +#define MPL3115_INT_SRC_TTH BIT(2) =20 #define MPL3115_PT_DATA_EVENT_ALL GENMASK(2, 0) =20 @@ -57,6 +63,8 @@ #define MPL3115_CTRL3_IPOL2 BIT(1) =20 #define MPL3115_CTRL4_INT_EN_DRDY BIT(7) +#define MPL3115_CTRL4_INT_EN_PTH BIT(3) +#define MPL3115_CTRL4_INT_EN_TTH BIT(2) =20 #define MPL3115_CTRL5_INT_CFG_DRDY BIT(7) =20 @@ -84,6 +92,7 @@ struct mpl3115_data { struct iio_trigger *drdy_trig; struct mutex lock; u8 ctrl_reg1; + u8 ctrl_reg4; }; =20 enum mpl3115_irq_pin { @@ -313,6 +322,15 @@ static irqreturn_t mpl3115_trigger_handler(int irq, vo= id *p) return IRQ_HANDLED; } =20 +static const struct iio_event_spec mpl3115_temp_press_event[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_ENABLE) | + BIT(IIO_EV_INFO_VALUE), + }, +}; + static const struct iio_chan_spec mpl3115_channels[] =3D { { .type =3D IIO_PRESSURE, @@ -328,7 +346,9 @@ static const struct iio_chan_spec mpl3115_channels[] = =3D { .storagebits =3D 32, .shift =3D 12, .endianness =3D IIO_BE, - } + }, + .event_spec =3D mpl3115_temp_press_event, + .num_event_specs =3D ARRAY_SIZE(mpl3115_temp_press_event), }, { .type =3D IIO_TEMP, @@ -344,7 +364,9 @@ static const struct iio_chan_spec mpl3115_channels[] = =3D { .storagebits =3D 16, .shift =3D 4, .endianness =3D IIO_BE, - } + }, + .event_spec =3D mpl3115_temp_press_event, + .num_event_specs =3D ARRAY_SIZE(mpl3115_temp_press_event), }, IIO_CHAN_SOFT_TIMESTAMP(2), }; @@ -354,15 +376,46 @@ static irqreturn_t mpl3115_interrupt_handler(int irq,= void *private) struct iio_dev *indio_dev =3D private; struct mpl3115_data *data =3D iio_priv(indio_dev); int ret; + u8 val_press[3]; + __be16 val_temp; =20 ret =3D i2c_smbus_read_byte_data(data->client, MPL3115_INT_SOURCE); if (ret < 0) return IRQ_HANDLED; =20 - if (!(ret & MPL3115_INT_SRC_DRDY)) + if (!(ret & (MPL3115_INT_SRC_TTH | MPL3115_INT_SRC_PTH | + MPL3115_INT_SRC_DRDY))) return IRQ_NONE; =20 - iio_trigger_poll_nested(data->drdy_trig); + if (ret & MPL3115_INT_SRC_DRDY) + iio_trigger_poll_nested(data->drdy_trig); + + if (ret & MPL3115_INT_SRC_PTH) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_PRESSURE, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + + /* Reset the SRC_PTH bit in INT_SOURCE */ + i2c_smbus_read_i2c_block_data(data->client, + MPL3115_OUT_PRESS, + sizeof(val_press), val_press); + } + + if (ret & MPL3115_INT_SRC_TTH) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + + /* Reset the SRC_TTH bit in INT_SOURCE */ + i2c_smbus_read_i2c_block_data(data->client, + MPL3115_OUT_TEMP, + sizeof(val_temp), + (u8 *)&val_temp); + } =20 return IRQ_HANDLED; } @@ -383,6 +436,7 @@ static int mpl3115_config_interrupt(struct mpl3115_data= *data, goto reg1_cleanup; =20 data->ctrl_reg1 =3D ctrl_reg1; + data->ctrl_reg4 =3D ctrl_reg4; =20 return 0; =20 @@ -396,15 +450,22 @@ static int mpl3115_set_trigger_state(struct iio_trigg= er *trig, bool state) { struct iio_dev *indio_dev =3D iio_trigger_get_drvdata(trig); struct mpl3115_data *data =3D iio_priv(indio_dev); - u8 ctrl_reg1 =3D data->ctrl_reg1; - u8 ctrl_reg4 =3D state ? MPL3115_CTRL4_INT_EN_DRDY : 0; + u8 ctrl_reg1, ctrl_reg4; =20 - if (state) + guard(mutex)(&data->lock); + + ctrl_reg1 =3D data->ctrl_reg1; + ctrl_reg4 =3D data->ctrl_reg4; + + if (state) { ctrl_reg1 |=3D MPL3115_CTRL1_ACTIVE; - else - ctrl_reg1 &=3D ~MPL3115_CTRL1_ACTIVE; + ctrl_reg4 |=3D MPL3115_CTRL4_INT_EN_DRDY; + } else { + ctrl_reg4 &=3D ~MPL3115_CTRL4_INT_EN_DRDY; =20 - guard(mutex)(&data->lock); + if (!ctrl_reg4) + ctrl_reg1 &=3D ~MPL3115_CTRL1_ACTIVE; + } =20 return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4); } @@ -413,10 +474,150 @@ static const struct iio_trigger_ops mpl3115_trigger_= ops =3D { .set_trigger_state =3D mpl3115_set_trigger_state, }; =20 +static int mpl3115_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct mpl3115_data *data =3D iio_priv(indio_dev); + + if (chan->type =3D=3D IIO_PRESSURE) + return !!(data->ctrl_reg4 & MPL3115_CTRL4_INT_EN_PTH); + + if (chan->type =3D=3D IIO_TEMP) + return !!(data->ctrl_reg4 & MPL3115_CTRL4_INT_EN_TTH); + + return -EINVAL; +} + +static int mpl3115_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct mpl3115_data *data =3D iio_priv(indio_dev); + u8 int_en_mask; + u8 ctrl_reg1, ctrl_reg4; + + switch (chan->type) { + case IIO_PRESSURE: + int_en_mask =3D MPL3115_CTRL4_INT_EN_PTH; + break; + case IIO_TEMP: + int_en_mask =3D MPL3115_CTRL4_INT_EN_TTH; + break; + default: + return -EINVAL; + } + + guard(mutex)(&data->lock); + + ctrl_reg1 =3D data->ctrl_reg1; + ctrl_reg4 =3D data->ctrl_reg4; + + if (state) { + ctrl_reg1 |=3D MPL3115_CTRL1_ACTIVE; + ctrl_reg4 |=3D int_en_mask; + } else { + ctrl_reg4 &=3D ~int_en_mask; + + if (!ctrl_reg4) + ctrl_reg1 &=3D ~MPL3115_CTRL1_ACTIVE; + } + + return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4); +} + +static int mpl3115_read_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + struct mpl3115_data *data =3D iio_priv(indio_dev); + int ret; + __be16 press_tgt; + + if (info !=3D IIO_EV_INFO_VALUE) + return -EINVAL; + + switch (chan->type) { + case IIO_PRESSURE: + ret =3D i2c_smbus_read_i2c_block_data(data->client, + MPL3115_PRESS_TGT, + sizeof(press_tgt), + (u8 *)&press_tgt); + if (ret < 0) + return ret; + + /* + * Target value for the pressure is 16-bit unsigned value, + * expressed in 2 Pa units + */ + *val =3D be16_to_cpu(press_tgt) << 1; + + return IIO_VAL_INT; + case IIO_TEMP: + ret =3D i2c_smbus_read_byte_data(data->client, MPL3115_TEMP_TGT); + if (ret < 0) + return ret; + + /* Target value for the temperature is 8-bit 2's complement */ + *val =3D sign_extend32(ret, 7); + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int mpl3115_write_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct mpl3115_data *data =3D iio_priv(indio_dev); + __be16 press_tgt; + + if (info !=3D IIO_EV_INFO_VALUE) + return -EINVAL; + + switch (chan->type) { + case IIO_PRESSURE: + val >>=3D 1; + + if (val < 0 || val > U16_MAX) + return -EINVAL; + + press_tgt =3D cpu_to_be16(val); + + return i2c_smbus_write_i2c_block_data(data->client, + MPL3115_PRESS_TGT, + sizeof(press_tgt), + (u8 *)&press_tgt); + case IIO_TEMP: + if (val < S8_MIN || val > S8_MAX) + return -EINVAL; + + return i2c_smbus_write_byte_data(data->client, + MPL3115_TEMP_TGT, val); + default: + return -EINVAL; + } +} + static const struct iio_info mpl3115_info =3D { .read_raw =3D &mpl3115_read_raw, .read_avail =3D &mpl3115_read_avail, .write_raw =3D &mpl3115_write_raw, + .read_event_config =3D mpl3115_read_event_config, + .write_event_config =3D mpl3115_write_event_config, + .read_event_value =3D mpl3115_read_thresh, + .write_event_value =3D mpl3115_write_thresh, }; =20 static int mpl3115_trigger_probe(struct mpl3115_data *data, --=20 2.25.1