From nobody Sun Feb 8 01:51:40 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 688762D879F for ; Wed, 12 Nov 2025 21:12:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762981979; cv=none; b=hZ/wRbTs/DxaWEteheB+7weFJ5yV7O5eki37Eh887AXEnUg9hEbAvx/09FLTdAJIW8isADPDoI+UvoxLUbN5mP4eqdd2ySkTiflB1CO8eFlTZR8ZyN0DZFA0JBGHDLoDOtSgsmeHo9Rm8MO8G6fzeR/REot2nskyaf2+7kl5SL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762981979; c=relaxed/simple; bh=CbgLR+LR4tT+7lEikMxwinz+7xt2UO1RFMUh/9q4YVg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cnEYCKaU2J/bsUc3ay2DV15A5yI3CqXmvSgSunCbE3hWnpT9SmP4ecGXL4KuJTFvuCAPLbvTmdA30JzaXWjCFAGHeiYMNxJYo1rPy743Tr9uDMrFu1B7cAOR6izyQYo6CAHJk9EiYZZAfeZjrSBThveCO195TxC2EYiE92bruro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FstuIoJk; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FstuIoJk" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-29586626fbeso883435ad.0 for ; Wed, 12 Nov 2025 13:12:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762981978; x=1763586778; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IjuDF77Nvin9wqVFgToN8rViAxLn6q03uh/wAmweEAk=; b=FstuIoJk3NFaVJTyNOmmb3FtzXdEMTS0JzvO98sNNyb2+sAuvkF0aJAVX1dSp36v2q FrtKtyufB6/5YhBCLuTdd+ScT8iwbCf/SNbnk2h1m+zL9K81ZANfo447rYZX7aMolRi4 XmyCDflLTuTWSWfqkJCrnPJOznhfXa4lVYgKcM9IixoZ07MhBnUnyIJAbNHDAjP35ySI 8cNvqbXVMZJWJpohd3zoq6R19ZTJCw+UUvDoFQJL/4nmMOh9vhTZsCj03xZxBCL5aqIL C78m6OjwVDFnr/QVXfE2P1qRPHQKdikE7Gyv3OuO3cT+xHH+vZ4NbIX/F/PtH8utjHUy sP7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762981978; x=1763586778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=IjuDF77Nvin9wqVFgToN8rViAxLn6q03uh/wAmweEAk=; b=s4GdGk0PYJJCkM+NnSEH9jv35r9wxbTmj/pg8pb8FBQwxbL/PZnTLQfK+yyXKl/mf+ yb7HIwcIPeV29TgF0RA4aXtUyOOaEc3iI0l70u+i40Hs8LCFQMDBnASzPDrhXIGrKpGP WwLScGm637VUY+Znn1Jxql6narVeDCmGJBh0UcfEa5j9hwx5s6unQqfD4Q0agMMvDX2G +Ru8YKHrSYwQRRekFdTuz8j0oQNxsr9emKOSE9ffyFczYqO/3aNPy/AgMtvOzWvQwqBk q54xIQ9Z1R1WRxf12ff54popF2dnvP00We1eDBuGK2XKLDACpONffem8fK59MnqJInit E0Vg== X-Forwarded-Encrypted: i=1; AJvYcCVzbMlpqQpAmYsKwJMnL0Klzp1HOUHed1PjatC4967Qz+AUjS3yIfZ2+qvaIL0tbO612d8ewq8wq5EA97s=@vger.kernel.org X-Gm-Message-State: AOJu0Ywsw9AJN3pyWSJSo0EqYWLCLXB2FPCH4/r1OsZ+mQrEitZTvKQT eIRFKvxccT6E/59YMsaxc6LBhYY5B6ji9UuXxOeEZwFdqOyyhGIz4eN8 X-Gm-Gg: ASbGnct9RRloNtMW9P8z7h4M6lpKLqiJ8MZz6LPtRWAJtJKXxOiI7OO0g22onuoISIZ g6DDnMpHBWAMWPo3TLa9pQKg+hnrwdJX12QKfscAAh5nASjSdssg/MteXz0k6jJ6iINNP/JflUq vpnON3/qEi5ArzvObDejxdFh+TXn6lgJgvMrDzzyiwRGXF94wIlH1KuFpdlOugc861pZCsbu4HX zv3FgGCQvFDtRUv8RAkfFOy+y6qjpje9fTmTg5K0FomV9mYcR4+ng0AJFegq8+EKk1ojOVqXQN/ eFcu0uinquYdCg6VMjPGwbRftc/lclswM59sYwuF7xelsTqV+MUyx6qjsEdvbPHqrJUCqxrtvnG 7BOY+ncwrwmsC4mmSZnI97T+Zi32eD7J9M7Jk3Bkbvli9WfVSq7e0VCqVHeWE62Mi3Ho= X-Google-Smtp-Source: AGHT+IG+mV9xg3XsxHHZk9IEjI2mp5r4vWAmColXzizBEHkP0uzY8AdSktbXnLxB4bTq6cCi6YDFug== X-Received: by 2002:a17:902:d551:b0:295:6a9:cb62 with SMTP id d9443c01a7336-2984edaa8a2mr55489145ad.35.1762981977752; Wed, 12 Nov 2025 13:12:57 -0800 (PST) Received: from gmail.com ([218.32.81.133]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c245ecdsm1011525ad.32.2025.11.12.13.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Nov 2025 13:12:57 -0800 (PST) From: Peter Shen To: Krzysztof Kozlowski Cc: Andrew Jeffery , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, peter.shen@amd.com, Peter Shen Subject: [PATCH v6 1/2] dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMC Date: Thu, 13 Nov 2025 05:12:47 +0800 Message-Id: <20251112211248.3711889-2-sjg168@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112211248.3711889-1-sjg168@gmail.com> References: <20251112211248.3711889-1-sjg168@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds the compatible string for the Facebook Anacapa BMC which uses an Aspeed AST2600 SoC. This is required before adding the board's device tree source file. Signed-off-by: Peter Shen Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index aedefca7cf4a..bcb874ebd9d2 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -80,6 +80,7 @@ properties: - aspeed,ast2600-evb - aspeed,ast2600-evb-a1 - asus,x4tf-bmc + - facebook,anacapa-bmc - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc base-commit: 24172e0d79900908cf5ebf366600616d29c9b417 --=20 2.34.1 From nobody Sun Feb 8 01:51:40 2026 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAFF82DC791 for ; Wed, 12 Nov 2025 21:13:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762981985; cv=none; b=joh0S2Xc92bkegJhC+C8/7MVsC2AcUYfIy/6rH6PoiFjiY5gnRdlW9TO6EdkeP5KPh8uk4RwTDcstJPpbqsigdjyVr8GNPHUMW5TkiignvVONYdEyMTUQT95mcBYYpWmqbquY9UmoFUUc5XWuZUmLryHbCAqvdcAisMWwqqf5CE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762981985; c=relaxed/simple; bh=pepJil0pIi4TZpRAvD1CjPc9nwebk2mdEFn4aRpCpAo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=cWd0K7fiA1O0jl4ZPEGc3MkvOMV60JoXqtOCIcCtmazbVdlH9X970Wf3XZBOMiEJ1ItqEZMg1B70W0Z8pedWCI970R1tZvxPaBjEdBjI7MS13vtNjZNRuYWG51GGiVmMSjxAfSW/nr0HV/WvlVBnJ6BEXujxfbpkX25PEm/iIqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cWxGcr0E; arc=none smtp.client-ip=209.85.215.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cWxGcr0E" Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-b4755f37c3eso76904a12.3 for ; Wed, 12 Nov 2025 13:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762981981; x=1763586781; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eTsoiWK89dIcEP6g6XZc9eqW22QG3HEkkEpr6wc5uDU=; b=cWxGcr0EThTMF474w3YiiGcfZOUxvNKyyxaRuwNw+81cRHRKVGIcaR4Esc2X+wNdyu cyEOov0LTRnH+km9JlehnRAU/QFfL+rACmyYPyopm14FuzBnSj4wrhfwwG6UWBZkl0R9 fhpg4JrIRj+oV8t0Thgt3t1n7OEO3RhavzUpn0muuZYMe/gWc0PZK8n3ugVrUcYFHaUc odAGPwRi6yIyylD/P3p3YxN85K1Lg5qWoNbi/I6xky3VQIQBHmTLILf+xt8XcZbGwpll GJQmIRNNxYCNBLWFEdCa3h9pF8JZ9RRrBRa6PGEHoo/dndolK4GpVACskdF51hOXw6RR J8LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762981981; x=1763586781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eTsoiWK89dIcEP6g6XZc9eqW22QG3HEkkEpr6wc5uDU=; b=B/+QaqmEPMV0Ejuw78auCcj5KvzDPf2Hvrf9u/U63WjYwN0xxZpIPSatWhScVayOhj YTqZNMDul6dAWzqQUlpTlX4hpoLT0/ijQ0c9Ku6Xrdl/iAHQsPsYUSnlhKPek7yS/fHn C1TRdJrUMHitvS6/BMbeLRkW7F3EoWXzOcfcEe2nYvLebxHsUsgxVYNVniNpjC9RSztp C2H5KsRtHIyn1uo1wMu+DUAT/+UOKqYsobSuKYsE8X8c28T0WqmIxjy/8n0gGaYp87E4 O0tYKhbvA4iWLMnSFOa656663QKtM1BFFy2Siwiai8HTR5nBIq3IogqUjjWMpHdnk2On G3JA== X-Forwarded-Encrypted: i=1; AJvYcCUJLMObu2B/1/Su4NeNuAjwV3rZgon/NrHnq8Nm6i3R8MPogr3AF7SFv5p2AhJunr/m8sv3PImRf6iAUYA=@vger.kernel.org X-Gm-Message-State: AOJu0Yz5aoOsp+ZIxxQTLa/l0B1q4IVYQl37DJOchizeUNWJqEFjCWgY 9B9USzltHU0xYVu4fpHFY42QX3/FGR6uh6YidNTMsbMy2AMKMxUE//Sl X-Gm-Gg: ASbGncvqQW8cYP/3zUpV6nForuS5BWnicg1tK4PeOOr8zIdG+9U7ipb85cBPX9v097U EFCdjiaHN4TjEsPaf7AM4u3Tz1yKMWr6mPuzxUer3LfY2qSCp4nfnFI01EVTg+6SokoiIBAMu8D jeldB1XPRpu8GgBihM4ufR7EsMlrc02DakAVW5edfHLtAhJLICPi2ZNdrDrlTJVlRYKZRxtp7DP xRFUBMyrEj+laYnV2F4uhmOU6YTzuYJt5sNk/RhZqubPZ+Lep6BC9va9cCbpUYCA6W4BO8mI30k 2SjzXHzLnvA9EBg6yqHFnhBDuMAODObkuhILvgOqXixp17lAeU2ZKnoSoKQxmWAAN2OXmZc+cjN p0NW8nRSi6WjyyDi1ybujFbPGuaXInJjAxD5iIaF8oSdxauhnq9Q9iUJZm2LfXdOnerk= X-Google-Smtp-Source: AGHT+IGiAC2fPw/7tlGD3+ZQapoloHtqn0fcCrKwNTPtbq8ZloINcSMTp/Hbs1Wbw9ua1Nmd+hluQg== X-Received: by 2002:a17:903:240e:b0:295:94fe:d5dc with SMTP id d9443c01a7336-2984ed33ef9mr55984315ad.2.1762981980718; Wed, 12 Nov 2025 13:13:00 -0800 (PST) Received: from gmail.com ([218.32.81.133]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c245ecdsm1011525ad.32.2025.11.12.13.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Nov 2025 13:13:00 -0800 (PST) From: Peter Shen To: Krzysztof Kozlowski Cc: Andrew Jeffery , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, peter.shen@amd.com, Peter Shen Subject: [PATCH v6 2/2] ARM: dts: aspeed: Add Device Tree for Facebook Anacapa BMC Date: Thu, 13 Nov 2025 05:12:48 +0800 Message-Id: <20251112211248.3711889-3-sjg168@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112211248.3711889-1-sjg168@gmail.com> References: <20251112211248.3711889-1-sjg168@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the initial device tree source file for the Facebook Anacapa BMC platform, based on the Aspeed AST2600 SoC. This device tree configures the platform-specific peripherals and aliases for OpenBMC usage. Signed-off-by: Peter Shen --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-anacapa.dts | 1223 +++++++++++++++++ 2 files changed, 1224 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index 0f0b5b707654..e1b2fc7b8c08 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-asus-x4tf.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-delta-ahe50dc.dtb \ + aspeed-bmc-facebook-anacapa.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-catalina.dtb \ aspeed-bmc-facebook-clemente.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts new file mode 100644 index 000000000000..e55069a199c8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -0,0 +1,1223 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc", "aspeed,ast2600"; + + aliases { + serial0 =3D &uart1; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + i2c16 =3D &i2c0mux0ch0; + i2c17 =3D &i2c0mux0ch1; + i2c18 =3D &i2c0mux0ch2; + i2c19 =3D &i2c0mux0ch3; + i2c20 =3D &i2c1mux0ch0; + i2c21 =3D &i2c1mux0ch1; + i2c22 =3D &i2c1mux0ch2; + i2c23 =3D &i2c1mux0ch3; + i2c24 =3D &i2c4mux0ch0; + i2c25 =3D &i2c4mux0ch1; + i2c26 =3D &i2c4mux0ch2; + i2c27 =3D &i2c4mux0ch3; + i2c28 =3D &i2c4mux0ch4; + i2c29 =3D &i2c4mux0ch5; + i2c30 =3D &i2c4mux0ch6; + i2c31 =3D &i2c4mux0ch7; + i2c32 =3D &i2c8mux0ch0; + i2c33 =3D &i2c8mux0ch1; + i2c34 =3D &i2c8mux0ch2; + i2c35 =3D &i2c8mux0ch3; + i2c36 =3D &i2c10mux0ch0; + i2c37 =3D &i2c10mux0ch1; + i2c38 =3D &i2c10mux0ch2; + i2c39 =3D &i2c10mux0ch3; + i2c40 =3D &i2c10mux0ch4; + i2c41 =3D &i2c10mux0ch5; + i2c42 =3D &i2c10mux0ch6; + i2c43 =3D &i2c10mux0ch7; + i2c44 =3D &i2c11mux0ch0; + i2c45 =3D &i2c11mux0ch1; + i2c46 =3D &i2c11mux0ch2; + i2c47 =3D &i2c11mux0ch3; + i2c48 =3D &i2c11mux0ch4; + i2c49 =3D &i2c11mux0ch5; + i2c50 =3D &i2c11mux0ch6; + i2c51 =3D &i2c11mux0ch7; + i2c52 =3D &i2c13mux0ch0; + i2c53 =3D &i2c13mux0ch1; + i2c54 =3D &i2c13mux0ch2; + i2c55 =3D &i2c13mux0ch3; + i2c56 =3D &i2c13mux0ch4; + i2c57 =3D &i2c13mux0ch5; + i2c58 =3D &i2c13mux0ch6; + i2c59 =3D &i2c13mux0ch7; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + label =3D "bmc_heartbeat_amber"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led-1 { + label =3D "fp_id_amber"; + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label =3D "power_blue"; + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + video_engine_memory: video { + size =3D <0x02c00000>; + alignment =3D <0x00100000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size =3D <0x01000000>; + alignment =3D <0x01000000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + + pcc_memory: pccbuffer { + no-map; + reg =3D <0xE0000000 0x00001000>; /* 4K */ + }; + }; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-name =3D "p3v3_bmc_aux"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + num-chipselects =3D <1>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + status =3D "okay"; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency =3D <33000000>; + reg =3D <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt =3D <2500000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + status =3D "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt =3D <2500000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc10_default>; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&uhci { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + status =3D "okay"; + m25p,fast-read; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status =3D "okay"; + m25p,fast-read; + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + }; +}; + +&gpio0 { + gpio-line-names =3D + + /* + * A0-A7: "", "", "", "", "", "", "", "" + */ + "SMB_BMC_MM11_SCL", "SMB_BMC_MM11_SDA", + "SMB_BMC_MM12_SCL", "SMB_BMC_MM12_SDA", + "SMB_BMC_MM13_SCL", "SMB_BMC_MM13_SDA", + "SMB_BMC_MM14_SCL", "SMB_BMC_MM14_SDA", + + /* + * B0-B7: "rtc-battery-voltage-read-enable", "", "", "BMC_READY", "", + * =C2=A0 =C2=A0 =C2=A0 =C2=A0"led-identify", "", "" + */ + "BATTERY_DETECT","BMC_GPIOB1", + "BMC_I2C1_FPGA_ALERT","BMC_READY", + "IOEXP_INT_3V3","FM_ID_LED", + "UART_BMC_4_TXD","UART_BMC_4_RXD", + + + /* + * C0-C7: "", "", "", "", "", "", "", "" + */ + "BMC_GPIOC0", "NCSI0_SCM_HPM_TX_EN", + "NCSI0_SCM_HPM_D0", "NCSI0_SCM_HPM_D1", + "PMBUS_REQ_N", "PSU_FW_UPDATE_REQ_N", + "NCSI0_HPM_SCM_CLK", "BMC_I2C_SSIF_ALERT", + + /* + * D0-D7: "", "", "", "", "", "", "", "" + */ + "NCSI0_HPM_SCM_D0", "NCSI0_HPM_SCM_D1", + "NCSI0_HPM_SCM_CRS_DV", "NCSI0_RXER", + "BMC_GPIOD4", "BMC_GPIOD5", + "BMC_GPIOD6", "BMC_GPIOD7", + + /* + * E0-E7: "", "", "", "", "", "", "", "" + */ + "BMC_GPIOE0", "BMC_GPIOE1", + "BMC_GPIOE1", "PD_RGMII4_RXCTL", + "BMC_GPIOE1", "BMC_GPIOE1", + "BMC_GPIOE1", "NCSI1_RXER", + + /* + * F0-F7: "", "", "", "", "", "", "", "" + */ + "BMC_EMMC_CLK", "BMC_EMMC_CMD", + "BMC_EMMC_DT0", "BMC_EMMC_DT1", + "BMC_EMMC_DT2", "BMC_EMMC_DT3", + "BMC_EMMC_CD_N", "BMC_EMMC_WP_N", + + /* + * G0-G7: "FM_MUX1_SEL_R", "", "", "", "", "", "", "" + */ + "FM_MUX1_SEL", "BMC_GPIOG1", + "BMC_EMMC_DT4", "BMC_EMMC_DT5", + "BMC_EMMC_DT6", "BMC_EMMC_DT7", + "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /* + * H0-H7: "", "", "", "", "", "", "", "" + */ + "SGPIO_CLK_1", "SGPIO_LD_1", + "SGPIO_DO_1", "SGPIO_DI_1", + "SMB_BMC_MM15_SCL", "SMB_BMC_MM15_SDA", + "SMB_BMC_MM16_SCL", "SMB_BMC_MM16_SDA", + + /* + * I0-I7: "", "", "", "", "", "", "", "" + */ + "JTAG_1_BMC_TRST", "JTAG_1_BMC_TCK", + "JTAG_1_BMC_TMS", "JTAG_1_BMC_TDI", + "JTAG_1_BMC_TDO", "FLASH_WP_STATUS", + "BMC_JTAG_MUX_SEL", "BMC_GPIOI7", + + /* + * J0-J7: "", "", "", "", "", "", "", "" + */ + "SMB_BMC_MM1_SCL", "SMB_BMC_MM1_SDA", + "SMB_BMC_MM2_SCL", "SMB_BMC_MM2_SDA", + "I3C_5_HV18_SCL", "I3C_5_HV18_SDA", + "I3C_6_HV18_SCL", "I3C_6_HV18_SDA", + + /* + * K0-K7: "", "", "", "", "", "", "", "" + */ + "SMB_BMC_MM5_SCL", "SMB_BMC_MM5_SDA", + "SMB_BMC_MM6_SCL", "SMB_BMC_MM6_SDA", + "SMB_BMC_MM7_SCL", "SMB_BMC_MM7_SDA", + "SMB_BMC_MM8_SCL", "SMB_BMC_MM8_SDA", + + /* + * L0-L7: "", "", "", "", "", "", "", "" + */ + "SMB_BMC_MM9_SCL", "SMB_BMC_MM9_SDA", + "SMB_BMC_MM10_SCL", "SMB_BMC_MM10_SDA", + "UART_BMC_3_TXD", "UART_BMC_3_RXD", + "V_VGAHS", "V_VGAVS", + + /* + * M0-M7: "", "", "", "", "", "", "", "" + */ + "PCIE_EP_RST_EN", "BMC_FRU_WP", + "SCM_HPM_STBY_RST_N", "SCM_HPM_STBY_EN", + "STBY_POWER_PG_3V3", "TH500_SHDN_OK", + "UART_BMC_1_TXD", "UART_BMC_1_RXD", + + /* + * N0-N7: "led-postcode-0", "led-postcode-1", "led-postcode-2", "led-post= code-3", + * =C2=A0 =C2=A0 =C2=A0 "led-postcode-4", "led-postcode-5", "led-postcod= e-6", "led-postcode-7" + */ + "LED_POSTCODE_0", "LED_POSTCODE_1", + "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", + "LED_POSTCODE_6", "LED_POSTCODE_7", + + /* + * O0-O7: "", "", "", "", "", "", "", "" + */ + "RUN_POWER_PG", "PWR_BRAKE", + "CHASSIS_AC_LOSS", "BSM_PRSNT_N", + "PSU_SMB_ALERT", "FM_TPM_PRSNT_0_N", + "PSU_FW_UPDATING_N", "BMC_GPIOO7", + + /* + * P0-P7: "power-button", "", "reset-button", "", "led-power", "", "", "" + */ + "PWR_BTN_BMC_BUF_N", "IPEX_CABLE_PRSNT", + "ID_RST_BTN_BMC_N", "RST_BMC_RSTBTN_OUT_N", + "PWR_LED", "RUN_POWER_EN", + "SHDN_FORCE", "BMC_HEARTBEAT_N", + + /* + * Q0-Q7: "", "", "", "", "", "", "", "" + */ + "IRQ_PCH_TPM_SPI_LV3_N", "USB_OC0_REAR_N", + "UART_MUX_SEL", "I2C_MUX_RESET", + "RSVD_NV_PLT_DETECT", "SPI_TPM_INT", + "CPU_JTAG_MUX_SELECT", "THERM_BB_OVERT", + + /* + * R0-R7: "", "", "", "", "", "", "", "" + */ + "THERM_BB_WARN", "SPI_BMC_FPGA_INT", + "CPU_BOOT_DONE", "PMBUS_GNT", + "CHASSIS_PWR_BRK", "PCIE_WAKE", + "PDB_THERM_OVERT", "SHDN_REQ", + + /* + * S0-S7: "", "", "power-host-control", "", "", "", "", "" + */ + "MDC1_BMC", "MDIO1_BMC", + "SYS_BMC_PWRBTN_N", "FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N", "UID_LED_N", + "SYS_FAULT_LED_N", "RUN_POWER_FAULT", + + /* + * T0-T7: "", "", "", "", "", "", "", "" + */ + "", "", "", "", "", "", "", "", + + /* + * U0-U7: "", "", "", "", "", "", "", "" + */ + "", "", "", "", "", "", "", "", + + /* + * V0-V7: "", "", "", "", "", "", "", "" + */ + "L2_RST_REQ_OUT", "L0L1_RST_REQ_OUT", + "BMC_ID_BEEP_SEL", "BMC_I2C0_FPGA_ALERT", + "SMB_BMC_TMP_ALERT", "PWR_LED_N", + "SYS_RST_OUT", "IRQ_TPM_SPI_N", + + /* + * W0-W7: "", "", "", "", "", "", "", "" + */ + "ESPI_LPC_D0_IO0", "ESPI_LPC_D1_IO1", + "ESPI_LPC_D2_IO2", "ESPI_LPC_D3_IO3", + "ESPI_HOST_LPC_BMC_CLK", + "ESPI_HOST_LPC_BMC_LFRAME_N", + "IRQ_ESPI_LPC_SERIRQ_ALERT0_N", + "RST_ESPI_LPC_BMC_N", + + /* + * X0-X7: "", "", "", "", "", "", "", "" + */ + "BMC_GPIOX0", "BMC_GPIOX1", + "BMC_GPIOX2", "SPI_BMC_OOB_0_CLK", + "SPI_BMC_OOB_0_IO0", "SPI_BMC_OOB_0_IO1", + "SPI_BMC_OOB_0_IO2", "SPI_BMC_OOB_0_IO3", + + /* + * Y0-Y7: "", "", "", "", "", "", "", "" + */ + "RST_WDTRST_PLD_N", "RST_BMC_SELF_HW", + "FM_FLASH_LATCH_N", "BMC_EMMC_RST_N", + "BMC_GPIOY4", "BMC_GPIOY5", + "PU_BMC_FWSPIABR_N", "PU_FWSPIWP_N", + + /* + * Z0-Z7: "", "", "", "", "", "", "", "" + */ + "SPI_BMC_TPM_CS2_N", "PU_SPI1ABR", + "PU_SPI1WP_N", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", + "BMC_GPIOZ6", "BMC_GPIOZ7", +}; + +&gpio1 { + gpio-line-names =3D + /* + * 18A0-18A7: "", "", "", "", "", "", "", "" + */ + "RGMII1TXCK", "RGMII1TXCTL", + "RGMII1TXD0", "RGMII1TXD1", + "RGMII1TXD2", "RGMII1TXD3", + "RGMII1RXCK", "RGMII1RXCTL", + + /* + * 18B0-18B7: "", "", "", "", "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_I= D1", + * "FM_BOARD_BMC_REV_ID2", "" + */ + "RGMII1RXD0", "RGMII1RXD1", + "RGMII1RXD2", "RGMII1RXD3", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "BMC_GPIO18B7", + + /* + * 18C0-18C7: "SPI_BMC_BIOS_ROM_IRQ0_R_N", "", "", "", "", "", "", "" + */ + "BMC_GPIO18C0", "BMC_GPIO18C1", + "SPI_BMC_BIOS_ROM_IRQ0_N", "BMC_GPIO18C3", + "BMC_GPIO18C4", "BMC_GPIO18C5", + "BMC_GPIO18C6", "BMC_GPIO18C7", + + /* + * 18D0-18D7: "", "", "", "", "", "", "", "" + */ + "BMC_GPIO18D0", "BMC_GPIO18D1", + "BMC_GPIO18D2", "BMC_GPIO18D3", + "BMC_GPIO18D4", "BMC_GPIO18D5", + "BMC_GPIO18D6", "BMC_GPIO18D7", + + /* + * 18E0-18E3: "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_R_N", "", "" + */ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", + "BMC_GPIO18E2", "BMC_GPIO18E3" +}; + +// L Bridge Board +&i2c0 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c4mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// AMC +&i2c5 { + status =3D "okay"; +}; + +// MB +&i2c6 { + status =3D "okay"; + + // HPM FRU + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +// SCM +&i2c7 { + status =3D "okay"; + + +}; + +// MB - PDB +&i2c8 { + status =3D "okay"; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + }; + + // R-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + i2c8mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + }; + + // L-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + i2c8mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c8mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// SCM +&i2c9 { + status =3D "okay"; + + // SCM FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible =3D "atmel,24c64"; + reg =3D <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + i2c10mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + i2c11mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status =3D "okay"; +}; + +// MB +&i2c13 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + }; + i2c13mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible =3D "atmel,24c256"; + reg =3D <0x51>; + }; + }; + i2c13mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// SCM +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&lpc_ctrl { + status =3D "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg =3D <0xca8>; + status =3D "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg =3D <0xca2>; + status =3D "okay"; +}; + +&pinctrl { + pinctrl_ncsi3_default: ncsi3_default { + function =3D "RMII3"; + groups =3D "NCSI3"; + }; +}; + +&mac2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out - in - out */ + /*A0-A3 line 0-7*/ + "","FM_CPU0_SYS_RESET_N", + "","CPU0_KBRST_N", + "","FM_CPU0_PROCHOT_trigger_N", + "","FM_CLR_CMOS_R_P0", + /*A4-A7 line 8-15*/ + "","Force_I3C_SEL", + "","SYSTEM_Force_Run_AC_Cycle", + "","", + "","", + /*B0-B3 line 16-23*/ + "Channel0_leakage_EAM3","FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0","FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1","FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage","FM_CPU0_NMI_SYNC_FLOOD_N", + /*B4-B7 line 24-31*/ + "Channel4_leakage_Manifold2","", + "Channel5_leakage_EAM1","", + "Channel6_leakage_CPU_DIMM","", + "Channel7_leakage_EAM2","", + /*C0-C3 line 32-39*/ + "RSVD_RMC_GPIO3","", + "LEAK_DETECT_RMC_N","", + "","", + "","", + /*C4-C7 line 40-47*/ + "","", + "","", + "","", + "","", + /*D0-D3 line 48-55*/ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R","", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R","", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R","", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R","", + /*D4-D7 line 56-63*/ + "AMC_BRD_PRSNT_CPLD_L","", + "","", + "","", + "","", + /*E0-E3 line 64-71*/ + "AMC_PDB_EAMHSC0_CPLD_EN_R","", + "AMC_PDB_EAMHSC1_CPLD_EN_R","", + "AMC_PDB_EAMHSC2_CPLD_EN_R","", + "AMC_PDB_EAMHSC3_CPLD_EN_R","", + /*E4-E7 line 72-79*/ + "","", + "","", + "","", + "","", + /*F0-F3 line 80-87*/ + "PWRGD_PVDDCR_CPU1_P0","SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0","", + "","", + "","", + /*F4-F7 line 88-95*/ + "","", + "","", + "","", + "","", + /*G0-G3 line 96-103*/ + "PWRGD_PVDDCR_SOC_P0","", + "PWRGD_PVDDIO_P0","", + "PWRGD_PVDDIO_MEM_S3_P0","", + "PWRGD_CHMP_CPU0_FPGA","", + /*G4-G7 line 104-111*/ + "PWRGD_CHIL_CPU0_FPGA","", + "PWRGD_CHEH_CPU0_FPGA","", + "PWRGD_CHAD_CPU0_FPGA","FM_BMC_READY_PLD", + "","", + /*H0-H3 line 112-119*/ + "PWRGD_P3V3","", + "P12V_DDR_IP_PWRGD_R","", + "P12V_DDR_AH_PWRGD_R","", + "PWRGD_P12V_VRM1_CPLD_PG_R","", + /*H4-H7 line 120-127*/ + "PWRGD_P12V_VRM0_CPLD_PG_R","", + "PWRGD_PDB_HSC4_CPLD_PG_R","", + "PWRGD_PVDD18_S5_P0_PG","", + "PWRGD_PVDD33_S5_P0_PG","", + /*I0-I3 line 128-135*/ + "EAM0_BRD_PRSNT_R_L","", + "EAM1_BRD_PRSNT_R_L","", + "EAM2_BRD_PRSNT_R_L","", + "EAM3_BRD_PRSNT_R_L","", + /*I4-I7 line 136-143*/ + "EAM0_CPU_MOD_PWR_GD_R","", + "EAM1_CPU_MOD_PWR_GD_R","", + "EAM2_CPU_MOD_PWR_GD_R","", + "EAM3_CPU_MOD_PWR_GD_R","", + /*J0-J3 line 144-151*/ + "PRSNT_L_BIRDGE_R","", + "PRSNT_R_BIRDGE_R","", + "BRIDGE_L_MAIN_PG_R","", + "BRIDGE_R_MAIN_PG_R","", + /*J4-J7 line 152-159*/ + "BRIDGE_L_STBY_PG_R","", + "BRIDGE_R_STBY_PG_R","", + "","", + "","", + /*K0-K3 line 160-167*/ + "ADC_I2C_ALERT_N","", + "TEMP_I2C_ALERT_R_L","", + "CPU0_VR_SMB_ALERT_CPLD_N","", + "COVER_INTRUDER_R_N","", + /*K4-K7 line 168-175*/ + "HANDLE_INTRUDER_CPLD_N","", + "IRQ_MCIO_CPLD_WAKE_R_N","", + "APML_CPU0_ALERT_R_N","", + "PDB_ALERT_R_N","", + /*L0-L3 line 176-183*/ + "CPU0_SP7R1","", + "CPU0_SP7R2","", + "CPU0_SP7R3","", + "CPU0_SP7R4","", + /*L4-L7 line 184-191*/ + "CPU0_CORETYPE0","", + "CPU0_CORETYPE1","", + "CPU0_CORETYPE2","", + "FM_BIOS_POST_CMPLT_R_N","", + /*M0-M3 line 192-199*/ + "EAM0_SMERR_CPLD_R_L","", + "EAM1_SMERR_CPLD_R_L","", + "EAM2_SMERR_CPLD_R_L","", + "EAM3_SMERR_CPLD_R_L","", + /*M4-M7 line 200-207*/ + "CPU0_SMERR_N_R","", + "CPU0_NV_SAVE_N_R","", + "PDB_PWR_LOSS_CPLD_N","", + "IRQ_BMC_SMI_ACTIVE_R_N","", + /*N0-N3 line 208-215*/ + "AMCROT_BMC_S5_RDY_R","", + "AMC_RDY_R","", + "AMC_STBY_PGOOD_R","", + "CPU_AMC_SLP_S5_R_L","", + /*N4-N7 line 216-223*/ + "AMC_CPU_EAMPG_R","", + "","", + "","", + "","", + /*O0-O3 line 224-231*/ + "HPM_PWR_FAIL","Port80_b0", + "FM_DIMM_IP_FAIL","Port80_b1", + "FM_DIMM_AH_FAIL","Port80_b2", + "HPM_AMC_THERMTRIP_R_L","Port80_b3", + /*O4-O7 line 232-239*/ + "FM_CPU0_THERMTRIP_N","Port80_b4", + "PVDDCR_SOC_P0_OCP_L","Port80_b5", + "CPLD_SGPIO_RDY","Port80_b6", + "","Port80_b7", + /*P0-P3 line 240-247*/ + "CPU0_SLP_S5_N_R","NFC_VEN", + "CPU0_SLP_S3_N_R","", + "FM_CPU0_PWRGD","", + "PWRGD_RMC","", + /*P4-P7 line 248-255*/ + "FM_RST_CPU0_RESET_N","", + "FM_PWRGD_CPU0_PWROK","", + "wS5_PWR_Ready","", + "wS0_ON_N","PWRGD_P1V0_AUX"; + status =3D "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2_default>; + status =3D "okay"; + reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "pnor"; + spi-max-frequency =3D <12000000>; + spi-tx-bus-width =3D <2>; + spi-rx-bus-width =3D <2>; + status =3D "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&wdt1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + aspeed,reset-type =3D "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; + status =3D "okay"; +}; + +&vhub { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&video { + status =3D "okay"; + memory-region =3D <&video_engine_memory>; +}; + +&gfx { + status =3D "okay"; + memory-region =3D <&gfx_memory>; +}; --=20 2.34.1