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De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 01/11] cxl/region: Rename misleading variable name @hpa to @hpa_range Date: Wed, 12 Nov 2025 21:31:28 +0100 Message-ID: <20251112203143.1269944-2-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD80:EE_|SA5PPFDC35F96D4:EE_ X-MS-Office365-Filtering-Correlation-Id: eb0d327c-6d63-4fcb-6dfc-08de222a8847 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KEFq111YGPUFKFyDi03x+md7MNjYmDpxasNgodLI4bJ8XX++0HZcb37MnTz4?= =?us-ascii?Q?RXolOvalkKvPTNIUsFitFwUPfkJUJ+9A4HudKb0GVOuY7xrz/U2zYD8K36dP?= =?us-ascii?Q?4kIlLbC0DEVzJ0kI5nFQxhPFb3TnBWXZ56Zq+XK2J9PsTckMNhmmboYTMI4H?= =?us-ascii?Q?w8DVisZTF2osR6rMrq2r0TJP5MrojloLTxrcbn+JZ5QhOTj1CQsxWlS88uEP?= =?us-ascii?Q?VLov717I081T9HsJsB799Ij2Ldkisoe+tqMEITlHMwhnWaFIZ3B8o19T6UDA?= =?us-ascii?Q?qvCn8Me4Hb8WC5aXT998vhV4HMmy/MoSfxMjhJQSZilYfmJoKwKxffY6mVMa?= =?us-ascii?Q?SWbgSAYe5fx7g8BUnXIveTUv/burA0o9OlqEjsRINnWmLWIkW5oL9nsvW/hT?= =?us-ascii?Q?pmEsgiNCB6vEMXc7HlM7ijejjWCVOgeGLO4EEGsroRYVKWxkPbjAg7fKIYQy?= =?us-ascii?Q?jM9SgxdXBf/4E9xYrHRaLrblK+BLQqr6v6UPtuVDH7gJ+jKeDeE1RZYB9iWv?= =?us-ascii?Q?SayuPhD+hueOGKf9RIBVTfMRMB4uH/7fFTjG/rXyYe5ejb/QLU0TBT9p45Rn?= =?us-ascii?Q?SElbyfipiMVDoH2PbP6Ma6Dglusc4gvO7qLYg3eY/Uw7d7W8D1rb7w3xM+5v?= =?us-ascii?Q?gZKsStsUuEsZU2PUXtsE0GSPFEMlYBl3MX0QDqPoAsgRcJS1OzhOBwi5kRvQ?= =?us-ascii?Q?Rhv5IRmR/SVwXZNpdS6ROnPnpW69o4uJJwljfDTeQPlgNWgEv8d2TspKXBpJ?= =?us-ascii?Q?eK9yZasSzCQumHh+oQtz255ZLoAdOL4N1M0u/2j4u3HYjReA+L725cmwxuDs?= =?us-ascii?Q?PHaMoSctdN8a+YqHJnn8DYo6YVjKC+mPcAHUKhlyFMCtuUEgihLKkcQ6sgTa?= =?us-ascii?Q?e3nN1nLmFVrDQv4bumFhKWF/MpYizxE0gLp+GPJTu5fQszHPFQ9NwOhDlVjf?= =?us-ascii?Q?qB0Mf+fJUuVOkbethYztaMgKPsJeaZVxcRhewBdYUhG17Pnq3y92m4MdsjX5?= =?us-ascii?Q?NrZvAOW+rch5W5JXaP4JEfFMHQFf8piVMjEdMjIO3Nq4y19L/eCacW+Q8yqi?= =?us-ascii?Q?AbMXKCJMg5itmNDLlnq9vBsXwEL3d5PRwF+KDVWDlp7MH43ktG6JQywnw7Di?= =?us-ascii?Q?gK3QA1V/bhifOh95mxNnjSHzIRvdDaYNLRomPW2bDPK/Vz0lLDmvm7v5/Kkd?= =?us-ascii?Q?ZwZGqzmuIZHMmOC8n982fhTz00HDf6UYHr0IyBbvqwF+6xFY5toMtUwMk5cg?= =?us-ascii?Q?JCfT9M4/Y/B7peDWrM3T6xkUit+bltg5/vyIRshyhvfbjiPwvQT5G8zN9uc8?= =?us-ascii?Q?xZ5Z972ORPRZS4FuyYG2pr88NncH1+Rw110I1O6jEYAOHKtVQO1weXa6g8t+?= =?us-ascii?Q?uvm+6qZBzZF8Ye/gOL3cMQGlGBRgxYtmbhSEclQIBZnc5baodUow1klvK4UC?= =?us-ascii?Q?wLBlUXFQZhqFcMXzF7P7kTwFf8NCqFxXzJK6ByIceWBjc7qy5PjB5LehDHQo?= =?us-ascii?Q?CvqxYrHYfuF+CTNKxvXam9b95FAArmg62B4hC419JtyiJGrk0EUP3FS2Ybzf?= =?us-ascii?Q?YDla9JTxP1tU1jxvOO8=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:00.3004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb0d327c-6d63-4fcb-6dfc-08de222a8847 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD80.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFDC35F96D4 Content-Type: text/plain; charset="utf-8" @hpa is actually a @hpa_range, rename variables accordingly. Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index a2c2fe6fc131..500aacf66d36 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3463,9 +3463,9 @@ static int match_decoder_by_range(struct device *dev,= const void *data) } =20 static struct cxl_decoder * -cxl_port_find_switch_decoder(struct cxl_port *port, struct range *hpa) +cxl_port_find_switch_decoder(struct cxl_port *port, struct range *hpa_rang= e) { - struct device *cxld_dev =3D device_find_child(&port->dev, hpa, + struct device *cxld_dev =3D device_find_child(&port->dev, hpa_range, match_decoder_by_range); =20 return cxld_dev ? to_cxl_decoder(cxld_dev) : NULL; @@ -3478,14 +3478,14 @@ cxl_find_root_decoder(struct cxl_endpoint_decoder *= cxled) struct cxl_port *port =3D cxled_to_port(cxled); struct cxl_root *cxl_root __free(put_cxl_root) =3D find_cxl_root(port); struct cxl_decoder *root, *cxld =3D &cxled->cxld; - struct range *hpa =3D &cxld->hpa_range; + struct range *hpa_range =3D &cxld->hpa_range; =20 - root =3D cxl_port_find_switch_decoder(&cxl_root->port, hpa); + root =3D cxl_port_find_switch_decoder(&cxl_root->port, hpa_range); if (!root) { dev_err(cxlmd->dev.parent, "%s:%s no CXL window for range %#llx:%#llx\n", dev_name(&cxlmd->dev), dev_name(&cxld->dev), - cxld->hpa_range.start, cxld->hpa_range.end); + hpa_range->start, hpa_range->end); return NULL; } =20 @@ -3551,7 +3551,7 @@ static int __construct_region(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled) { struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); - struct range *hpa =3D &cxled->cxld.hpa_range; + struct range *hpa_range =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; struct resource *res; int rc; @@ -3572,7 +3572,7 @@ static int __construct_region(struct cxl_region *cxlr, if (!res) return -ENOMEM; =20 - *res =3D DEFINE_RES_MEM_NAMED(hpa->start, range_len(hpa), + *res =3D DEFINE_RES_MEM_NAMED(hpa_range->start, range_len(hpa_range), dev_name(&cxlr->dev)); =20 rc =3D cxl_extended_linear_cache_resize(cxlr, res); @@ -3655,11 +3655,12 @@ static struct cxl_region *construct_region(struct c= xl_root_decoder *cxlrd, } =20 static struct cxl_region * -cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, struct range *hpa) +cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, + struct range *hpa_range) { struct device *region_dev; =20 - region_dev =3D device_find_child(&cxlrd->cxlsd.cxld.dev, hpa, + region_dev =3D device_find_child(&cxlrd->cxlsd.cxld.dev, hpa_range, match_region_by_range); if (!region_dev) return NULL; @@ -3669,7 +3670,7 @@ cxl_find_region_by_range(struct cxl_root_decoder *cxl= rd, struct range *hpa) =20 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) { - struct range *hpa =3D &cxled->cxld.hpa_range; + struct range *hpa_range =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; 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Wed, 12 Nov 2025 12:32:00 -0800 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 02/11] cxl/region: Store root decoder in struct cxl_region Date: Wed, 12 Nov 2025 21:31:29 +0100 Message-ID: <20251112203143.1269944-3-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|SA1PR12MB8141:EE_ X-MS-Office365-Filtering-Correlation-Id: 39e3450c-8f4c-45ca-d14a-08de222a8a4a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7F6wJEPZ9yYfI2mDD+ynm1r8gF5b/OoSGrVFN2EhgQB23nGM5ufKqbvAryia?= =?us-ascii?Q?Ooi3xniHubSC5ps7ymVsjhRgNsCGUlmZ10nSfzYgt7t7E5vsh1eBYymp3X2x?= =?us-ascii?Q?1byXHk4oxMxgteIV/UMWIJSK4kHckZ+IakEnP4IgVR9OMKg+YciqpaHt7FXp?= =?us-ascii?Q?hzTlmJhaG0mKC1zM0M5mvnO9uiwbaFD/E2oHxeNPbRDtXNb73enhmisvxP/N?= =?us-ascii?Q?/rG0rd0doHtArTqESLsdkX4uzCxoXIfj5t1QpIN2RUigH8olSwG9zmP2sLcK?= =?us-ascii?Q?I8srjPls1db8nCZiURc5RdzILSInagEejLH3+1jGSACTevZ8BISjaYmy4Rp/?= =?us-ascii?Q?lgRdIBuPjRluLVIY3ouCR37KADUMxwwsS4ITKU8oWTsEfBwT0w9sfilQFlzR?= =?us-ascii?Q?S8jdC5xBoP5v6xNXXQUdtlulcq8R6bcmS79PQmN7ViBnxmT0sQ+RugH137Di?= =?us-ascii?Q?ABXQbDiytrEaP96qQXtI17J8oG3h+gwuKWmeCzmyz9+33tTy/jHRiSFOFwrY?= =?us-ascii?Q?Ecq2BEygakJMKRCt0XtmrPFYGqJuJsJx8evqFaiCtfz27gy3aVgv49GNa9aT?= =?us-ascii?Q?X7IAd1aVArV1nn/6459dQNeKVn+fL6WflriuIvmpL6EgunLGAWW0HbNHVpir?= =?us-ascii?Q?2pDE9cmAgR59GYwi/SdPvXrBfyLDAPF8/VpyYhKsR+jzo08aWnxb589V/axz?= =?us-ascii?Q?JV2CiHvK6WnpKHTEiw5F1JX9mFHZXxyPkmfDlgQNASXNUJgi5nm/z4NEQpyr?= =?us-ascii?Q?rwldzeeQXWO8xloxed+lfJVjBtvyAMxdkXtOJcCgY0tszrHOZLbjYeeJK+yb?= =?us-ascii?Q?SML3NTX/m+R8N9M6UfypfL+BqhAY3tNeDLDev58CWSNXdxOMd1yFedhnY7Wu?= =?us-ascii?Q?aCEfDDEsbIZ5A9Dv0K/gXkabtRlpmC+5TXUwkibSzDMJ0K3N5a8X/dCdWN8p?= =?us-ascii?Q?uakDf8o4/epnNG8YC7FDPe0oFSaWRyTt+AiU/oB+n8Z8DHc9JlME1k53DJbe?= =?us-ascii?Q?XH4Xc2hsYylgVH9kE0J2SUkJP1miwJ7DUZ+wet6oc1BzKRZ+1c0lCLh4c3Ir?= =?us-ascii?Q?wlpHOoux1waFsPthTNbRQnpYWzX/mKvrlSqK3sV4Qq+2dN0LJg75Ww2FZ90+?= =?us-ascii?Q?3yaFWVZw3qQeTM9+6EIJJBJ89iVmRuv6zrPccjHwjGM2yvBl5vNwJ3r9Ern7?= =?us-ascii?Q?TFuQ5SbzU9fveRKFBny6mrKPB6JZdObrlDhz5LIx9YmZy/GT6pKl0+DGOi2L?= =?us-ascii?Q?qTV8xZV9cX4miT+fVtmlJVsioOhhhVtNufYeglJCLGmX1YG3b0TZCtUNhDQQ?= =?us-ascii?Q?MQnLZt4wYRWCQOHEce+KRsbno4GiXrK3GTCA9m3dKAUC3xLZSuNZytBrE8/8?= =?us-ascii?Q?gkVu5H6GRBnNvY4Niq9jNvupUbvb0D0wxNjXYQI1o2OkefK74BlSTpGC4IUA?= =?us-ascii?Q?aqJ0n/X82B3EOYcJBOpOE0Dwx1MJEazmb545JPVZwmrEOvUaJtJvp34G/H7h?= =?us-ascii?Q?QC2WieDIUVgTX5+F1lO2gbofhDRyxnV3YpoJs8mAtSmubGG83gJzNXEb47iT?= =?us-ascii?Q?OHmhY3z7/rCqc3idl6w=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:03.6644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39e3450c-8f4c-45ca-d14a-08de222a8a4a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003442.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8141 Content-Type: text/plain; charset="utf-8" A region is always bound to a root decoder. The region's associated root decoder is often needed. Add it to struct cxl_region. This simplifies the code by removing dynamic lookups and the root decoder argument from the function argument list where possible. Patch is a prerequisite to implement address translation which uses struct cxl_region to store all relevant region and interleaving parameters. It changes the argument list of __construct_region() in preparation of adding a context argument. Additionally the arg list of cxl_region_attach_position() is simplified and the use of to_cxl_root_decoder() removed, which always reconstructs and checks the pointer. The pointer never changes and is frequently used. Code becomes more readable as this amphazises the binding between both objects. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 37 +++++++++++++++++++------------------ drivers/cxl/cxl.h | 2 ++ 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 500aacf66d36..a7786d768699 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -480,9 +480,9 @@ static ssize_t interleave_ways_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(dev->parent); - struct cxl_decoder *cxld =3D &cxlrd->cxlsd.cxld; struct cxl_region *cxlr =3D to_cxl_region(dev); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; + struct cxl_decoder *cxld =3D &cxlrd->cxlsd.cxld; struct cxl_region_params *p =3D &cxlr->params; unsigned int val, save; int rc; @@ -543,9 +543,9 @@ static ssize_t interleave_granularity_store(struct devi= ce *dev, struct device_attribute *attr, const char *buf, size_t len) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(dev->parent); - struct cxl_decoder *cxld =3D &cxlrd->cxlsd.cxld; struct cxl_region *cxlr =3D to_cxl_region(dev); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; + struct cxl_decoder *cxld =3D &cxlrd->cxlsd.cxld; struct cxl_region_params *p =3D &cxlr->params; int rc, val; u16 ig; @@ -619,7 +619,7 @@ static DEVICE_ATTR_RO(mode); =20 static int alloc_hpa(struct cxl_region *cxlr, resource_size_t size) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_region_params *p =3D &cxlr->params; struct resource *res; u64 remainder =3D 0; @@ -1352,7 +1352,7 @@ static int cxl_port_setup_targets(struct cxl_port *po= rt, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; int parent_iw, parent_ig, ig, iw, rc, inc =3D 0, pos =3D cxled->pos; struct cxl_port *parent_port =3D to_cxl_port(port->dev.parent); struct cxl_region_ref *cxl_rr =3D cxl_rr_load(port, cxlr); @@ -1711,10 +1711,10 @@ static int cxl_region_validate_position(struct cxl_= region *cxlr, } =20 static int cxl_region_attach_position(struct cxl_region *cxlr, - struct cxl_root_decoder *cxlrd, struct cxl_endpoint_decoder *cxled, const struct cxl_dport *dport, int pos) { + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct cxl_switch_decoder *cxlsd =3D &cxlrd->cxlsd; struct cxl_decoder *cxld =3D &cxlsd->cxld; @@ -1951,7 +1951,7 @@ static int cxl_region_sort_targets(struct cxl_region = *cxlr) static int cxl_region_attach(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct cxl_dev_state *cxlds =3D cxlmd->cxlds; struct cxl_region_params *p =3D &cxlr->params; @@ -2056,8 +2056,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, ep_port =3D cxled_to_port(cxled); dport =3D cxl_find_dport_by_dev(root_port, ep_port->host_bridge); - rc =3D cxl_region_attach_position(cxlr, cxlrd, cxled, - dport, i); + rc =3D cxl_region_attach_position(cxlr, cxled, dport, i); if (rc) return rc; } @@ -2080,7 +2079,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, if (rc) return rc; =20 - rc =3D cxl_region_attach_position(cxlr, cxlrd, cxled, dport, pos); + rc =3D cxl_region_attach_position(cxlr, cxled, dport, pos); if (rc) return rc; =20 @@ -2376,8 +2375,8 @@ static const struct attribute_group *region_groups[] = =3D { =20 static void cxl_region_release(struct device *dev) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(dev->parent); struct cxl_region *cxlr =3D to_cxl_region(dev); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; int id =3D atomic_read(&cxlrd->region_id); =20 /* @@ -2460,10 +2459,12 @@ static struct cxl_region *cxl_region_alloc(struct c= xl_root_decoder *cxlrd, int i * region id allocations */ get_device(dev->parent); + cxlr->cxlrd =3D cxlrd; + cxlr->id =3D id; + device_set_pm_not_required(dev); dev->bus =3D &cxl_bus_type; dev->type =3D &cxl_region_type; - cxlr->id =3D id; =20 return cxlr; } @@ -3104,7 +3105,7 @@ EXPORT_SYMBOL_FOR_MODULES(cxl_calculate_hpa_offset, "= cxl_translate"); u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, u64 dpa) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_region_params *p =3D &cxlr->params; struct cxl_endpoint_decoder *cxled =3D NULL; u64 dpa_offset, hpa_offset, hpa; @@ -3157,7 +3158,7 @@ static int region_offset_to_dpa_result(struct cxl_reg= ion *cxlr, u64 offset, struct dpa_result *result) { struct cxl_region_params *p =3D &cxlr->params; - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_endpoint_decoder *cxled; u64 hpa, hpa_offset, dpa_offset; u16 eig =3D 0; @@ -3511,7 +3512,7 @@ static int match_region_by_range(struct device *dev, = const void *data) static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr, struct resource *res) { - struct cxl_root_decoder *cxlrd =3D to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_region_params *p =3D &cxlr->params; resource_size_t size =3D resource_size(res); resource_size_t cache_size, start; @@ -3547,9 +3548,9 @@ static int cxl_extended_linear_cache_resize(struct cx= l_region *cxlr, } =20 static int __construct_region(struct cxl_region *cxlr, - struct cxl_root_decoder *cxlrd, struct cxl_endpoint_decoder *cxled) { + struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct range *hpa_range =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; @@ -3645,7 +3646,7 @@ static struct cxl_region *construct_region(struct cxl= _root_decoder *cxlrd, return cxlr; } =20 - rc =3D __construct_region(cxlr, cxlrd, cxled); + rc =3D __construct_region(cxlr, cxled); if (rc) { devm_release_action(port->uport_dev, unregister_region, cxlr); return ERR_PTR(rc); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index e8931b626fc6..99e3a1a6587b 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -521,6 +521,7 @@ enum cxl_partition_mode { * struct cxl_region - CXL region * @dev: This region's device * @id: This region's id. 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Endpoint decoders assigned to a region share the same HPA range. The region's address range is the system's physical address (SPA) range. Endpoint decoders in systems that need address translation use HPAs which are not SPAs. To make the SPA range accessible to the endpoint decoders, store and track the region's SPA range in struct cxl_region. Introduce the @hpa_range member to the struct. Now, the SPA range of an endpoint decoder can be determined based on its assigned region. Patch is a prerequisite to implement address translation which uses struct cxl_region to store all relevant region and interleaving parameters. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 7 +++++++ drivers/cxl/cxl.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index a7786d768699..5b9d096a73fe 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -655,6 +655,8 @@ static int alloc_hpa(struct cxl_region *cxlr, resource_= size_t size) return PTR_ERR(res); } =20 + cxlr->hpa_range =3D DEFINE_RANGE(res->start, res->end); + p->res =3D res; p->state =3D CXL_CONFIG_INTERLEAVE_ACTIVE; =20 @@ -691,6 +693,8 @@ static int free_hpa(struct cxl_region *cxlr) if (p->state >=3D CXL_CONFIG_ACTIVE) return -EBUSY; =20 + cxlr->hpa_range =3D DEFINE_RANGE(0, -1); + cxl_region_iomem_release(cxlr); p->state =3D CXL_CONFIG_IDLE; return 0; @@ -2433,6 +2437,8 @@ static void unregister_region(void *_cxlr) for (i =3D 0; i < p->interleave_ways; i++) detach_target(cxlr, i); =20 + cxlr->hpa_range =3D DEFINE_RANGE(0, -1); + cxl_region_iomem_release(cxlr); put_device(&cxlr->dev); } @@ -3568,6 +3574,7 @@ static int __construct_region(struct cxl_region *cxlr, } =20 set_bit(CXL_REGION_F_AUTO, &cxlr->flags); + cxlr->hpa_range =3D *hpa_range; =20 res =3D kmalloc(sizeof(*res), GFP_KERNEL); if (!res) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 99e3a1a6587b..4cb7f66b9483 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -522,6 +522,7 @@ enum cxl_partition_mode { * @dev: This region's device * @id: This region's id. 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The structure is dynamically allocated, though it contains only a single pointer in it. This also requires to check two pointers to check for the existance of a callback. Simplify the allocation, release and handler check by embedding the ops statically in struct cxl_root. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Robert Richter --- drivers/cxl/acpi.c | 7 ++----- drivers/cxl/core/cdat.c | 8 ++++---- drivers/cxl/core/port.c | 9 ++------- drivers/cxl/cxl.h | 19 ++++++++++--------- 4 files changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 1a64e5c71fbd..4fe489244a77 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -318,10 +318,6 @@ static int cxl_acpi_qos_class(struct cxl_root *cxl_roo= t, return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class); } =20 -static const struct cxl_root_ops acpi_root_ops =3D { - .qos_class =3D cxl_acpi_qos_class, -}; - static void del_cxl_resource(struct resource *res) { if (!res) @@ -930,9 +926,10 @@ static int cxl_acpi_probe(struct platform_device *pdev) cxl_res->end =3D -1; cxl_res->flags =3D IORESOURCE_MEM; =20 - cxl_root =3D devm_cxl_add_root(host, &acpi_root_ops); + cxl_root =3D devm_cxl_add_root(host); if (IS_ERR(cxl_root)) return PTR_ERR(cxl_root); + cxl_root->ops.qos_class =3D cxl_acpi_qos_class; root_port =3D &cxl_root->port; =20 rc =3D bus_for_each_dev(adev->dev.bus, NULL, root_port, diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 7120b5f2e31f..18f0f2a25113 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -213,7 +213,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port= *port, if (!cxl_root) return -ENODEV; =20 - if (!cxl_root->ops || !cxl_root->ops->qos_class) + if (!cxl_root->ops.qos_class) return -EOPNOTSUPP; =20 xa_for_each(dsmas_xa, index, dent) { @@ -221,9 +221,9 @@ static int cxl_port_perf_data_calculate(struct cxl_port= *port, =20 cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c); dent->entries =3D 1; - rc =3D cxl_root->ops->qos_class(cxl_root, - &dent->coord[ACCESS_COORDINATE_CPU], - 1, &qos_class); + rc =3D cxl_root->ops.qos_class(cxl_root, + &dent->coord[ACCESS_COORDINATE_CPU], + 1, &qos_class); if (rc !=3D 1) continue; =20 diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8128fd2b5b31..2338d146577c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -459,7 +459,6 @@ static void cxl_root_decoder_release(struct device *dev) if (atomic_read(&cxlrd->region_id) >=3D 0) memregion_free(atomic_read(&cxlrd->region_id)); __cxl_decoder_release(&cxlrd->cxlsd.cxld); - kfree(cxlrd->ops); kfree(cxlrd); } =20 @@ -955,19 +954,15 @@ struct cxl_port *devm_cxl_add_port(struct device *hos= t, } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, "CXL"); =20 -struct cxl_root *devm_cxl_add_root(struct device *host, - const struct cxl_root_ops *ops) +struct cxl_root *devm_cxl_add_root(struct device *host) { - struct cxl_root *cxl_root; struct cxl_port *port; =20 port =3D devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); if (IS_ERR(port)) return ERR_CAST(port); =20 - cxl_root =3D to_cxl_root(port); - cxl_root->ops =3D ops; - return cxl_root; + return to_cxl_root(port); } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, "CXL"); =20 diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4cb7f66b9483..11709f0f91d6 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -638,6 +638,14 @@ struct cxl_port { resource_size_t component_reg_phys; }; =20 +struct cxl_root; + +struct cxl_root_ops { + int (*qos_class)(struct cxl_root *cxl_root, + struct access_coordinate *coord, int entries, + int *qos_class); +}; + /** * struct cxl_root - logical collection of root cxl_port items * @@ -646,7 +654,7 @@ struct cxl_port { */ struct cxl_root { struct cxl_port port; - const struct cxl_root_ops *ops; + struct cxl_root_ops ops; }; =20 static inline struct cxl_root * @@ -655,12 +663,6 @@ to_cxl_root(const struct cxl_port *port) return container_of(port, struct cxl_root, port); } =20 -struct cxl_root_ops { - int (*qos_class)(struct cxl_root *cxl_root, - struct access_coordinate *coord, int entries, - int *qos_class); -}; - static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_de= v) { @@ -774,8 +776,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); -struct cxl_root *devm_cxl_add_root(struct device *host, - const struct cxl_root_ops *ops); +struct cxl_root *devm_cxl_add_root(struct device *host); struct cxl_root *find_cxl_root(struct cxl_port *port); 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De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 05/11] cxl/region: Separate region parameter setup and region construction Date: Wed, 12 Nov 2025 21:31:32 +0100 Message-ID: <20251112203143.1269944-6-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|DS2PR12MB9661:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a132908-3d13-467e-3cf1-08de222a9064 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AeZ82LfOFP8e+65IiO2hCx6L/CgoTZ68P6XGjkvyBzRhy2dY5aumIX6rafBR?= =?us-ascii?Q?6EaKpBli3APW7hv5nYaOAHpKIxjLV5dW0qRT8hBQZmgG1roH+OIrWzb0J3O8?= =?us-ascii?Q?qqASx+vtfaruzG4cL4P8mjV87uh24BU8zK6njzcb0XxJBAjBZ4J9Z04ikjmI?= =?us-ascii?Q?lzXcw71GCeO9W8jqJMsZLp/e+sxL+hLKQEsfoUrdXVzv5bhiWm/3tXZ7RpwT?= =?us-ascii?Q?8td2ewXWZlQEOjv3OKlBtrGeOlQeoqaK4Q6c0ExWBbA4ZBjKmTjL7lxSg54a?= =?us-ascii?Q?ejMtm4wfOeHHTiKFldHGOwIBodZXMbWSzZkWIRhUrlXXBg3pkIZjyqYXNNZB?= =?us-ascii?Q?54CI5Os9GuOwBFJRXeTWgBS9rVVsQaJe0DwdxuguZjv0FmbieOS9oCcpeXxf?= =?us-ascii?Q?MTbV28BsPq0p4+eSBzO6xiwYOrgl2QivdvyV0pFHXU8rFkPRh9wFzbw1mqH5?= =?us-ascii?Q?cghEWwPcMtbd0y4aRmW8br8GXGZ0OvUXzCdNQ/Gnft2/FBRhaGvlKAdXkerU?= =?us-ascii?Q?uoNMZMeSzgo7N4b7xqsyeRb/BY5ElttZs5ualosuQaNiWsncwIbEP4N9uZnT?= =?us-ascii?Q?1QlcO5NOlBvTlo1w8aAd43mT+wArqd6SJ4rB67Mwe/6Ix80fgZbPJzKnyNbx?= =?us-ascii?Q?nf5mIZud4PlV4Pyo0Qxp3/U1M2B/g3DE4ivYT30DCou9QTZ6TY4/LZfS49bw?= =?us-ascii?Q?J9ujmsT7rMkDGweI6w/0Mky/zLAfmRwA5rLkTAC5xbt3Hyp6i7gedYXo8FSB?= =?us-ascii?Q?fEi6KAN80aojKq5nj5okjHXWKWQKNytVk1gGrb7HgFrzLfadnoCKJPe+FwTc?= =?us-ascii?Q?afLL9IpsxdB/vMoeOr5LouD1enx8UuJ/j5MsIv9b0nCMM8vUHRQeGg5EYr0d?= =?us-ascii?Q?sctLjkWjMM2c7k6hRHPJ1WXedK5wof/HOvx3fmm2NiktoSyrxm1098epQaj3?= =?us-ascii?Q?WxU4QMGBQKoNTuPHiruGCTRUprkvs8OkjWykOXsrtL798u01qZ7NmQsBGZN0?= =?us-ascii?Q?H2UP9DVGHRgP2+KdikqROF8ekmIEyHRwSAsNxRT/IsJO4PXScsXNtoSQgK8C?= =?us-ascii?Q?1lEyucyaxrHOlbbqCsErJYxTaGr+Ue0Iu9MOZLaIWlBFvOSf+bP5gA/3Nt05?= =?us-ascii?Q?e2AAp9vTAKE1dEZZ+qdsVKjLASv9cTXvj/+QhlCpwLEmx1juFHfUr+eWpRSZ?= =?us-ascii?Q?PxHW8n18DO4l1OhIgGLDKbDluA56bvtUBzDT4RLfBK3uMxhVAy0XWFRlmJum?= =?us-ascii?Q?suLteLfYeQLNRcfCTwGlIVbyPhgkn1FaHvLIksSdTVxB9NulCELb0EPYsXX4?= =?us-ascii?Q?7V9FAL2AgTw4SInxB6e/5FXMRubRW/YxmjuUiD/I+qtyr4HGqdH39/UtlgLW?= =?us-ascii?Q?wxDR4ANNYaVQ23JU85wkzczC3qQKgqy2b+11me/sMZCwlbh8RGsm9g8Rr8MF?= =?us-ascii?Q?sjF+x73br2glcp7D5Gu66R/xzaJ50WBkHWl3f/Zp0qRaYBLXXtQRXsVmuA4v?= =?us-ascii?Q?J4xIF2dQayW3Ka+OJfmGD/wiGuurBddGXVEpHRjt1N719bWicx+4c2ToVbKS?= =?us-ascii?Q?iKyX3Q/oy98b2FCrv/w=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:13.8868 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a132908-3d13-467e-3cf1-08de222a9064 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003448.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9661 Content-Type: text/plain; charset="utf-8" To construct a region, the region parameters such as address range and interleaving config need to be determined. This is done while constructing the region by inspecting the endpoint decoder configuration. The endpoint decoder is passed as a function argument. With address translation the endpoint decoder data is no longer sufficient to extract the region parameters as some of the information is obtained using other methods such as using firmware calls. In a first step, separate code to determine the region parameters from the region construction. Temporarily store all the data to create the region in the new struct cxl_region_context. Once the region data is determined and struct cxl_region_context is filled, construct the region. Patch is a prerequisite to implement address translation. The code separation helps to later extend it to determine region parameters using other methods as needed, esp. to support address translation. Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/core.h | 8 ++++++++ drivers/cxl/core/region.c | 27 ++++++++++++++++++--------- 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 1fb66132b777..ae9e1bb51562 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -19,6 +19,14 @@ enum cxl_detach_mode { }; =20 #ifdef CONFIG_CXL_REGION + +struct cxl_region_context { + struct cxl_endpoint_decoder *cxled; + struct range hpa_range; + int interleave_ways; + int interleave_granularity; +}; + extern struct device_attribute dev_attr_create_pmem_region; extern struct device_attribute dev_attr_create_ram_region; extern struct device_attribute dev_attr_delete_region; diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 5b9d096a73fe..07adc2075103 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3554,11 +3554,12 @@ static int cxl_extended_linear_cache_resize(struct = cxl_region *cxlr, } =20 static int __construct_region(struct cxl_region *cxlr, - struct cxl_endpoint_decoder *cxled) + struct cxl_region_context *ctx) { + struct cxl_endpoint_decoder *cxled =3D ctx->cxled; struct cxl_root_decoder *cxlrd =3D cxlr->cxlrd; struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); - struct range *hpa_range =3D &cxled->cxld.hpa_range; + struct range *hpa_range =3D &ctx->hpa_range; struct cxl_region_params *p; struct resource *res; int rc; @@ -3611,8 +3612,8 @@ static int __construct_region(struct cxl_region *cxlr, } =20 p->res =3D res; - p->interleave_ways =3D cxled->cxld.interleave_ways; - p->interleave_granularity =3D cxled->cxld.interleave_granularity; + p->interleave_ways =3D ctx->interleave_ways; + p->interleave_granularity =3D ctx->interleave_granularity; p->state =3D CXL_CONFIG_INTERLEAVE_ACTIVE; =20 rc =3D sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group()); @@ -3632,8 +3633,9 @@ static int __construct_region(struct cxl_region *cxlr, =20 /* Establish an empty region covering the given HPA range */ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, - struct cxl_endpoint_decoder *cxled) + struct cxl_region_context *ctx) { + struct cxl_endpoint_decoder *cxled =3D ctx->cxled; struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct cxl_port *port =3D cxlrd_to_port(cxlrd); struct cxl_dev_state *cxlds =3D cxlmd->cxlds; @@ -3653,7 +3655,7 @@ static struct cxl_region *construct_region(struct cxl= _root_decoder *cxlrd, return cxlr; } =20 - rc =3D __construct_region(cxlr, cxled); + rc =3D __construct_region(cxlr, ctx); if (rc) { devm_release_action(port->uport_dev, unregister_region, cxlr); return ERR_PTR(rc); @@ -3678,11 +3680,18 @@ cxl_find_region_by_range(struct cxl_root_decoder *c= xlrd, =20 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) { - struct range *hpa_range =3D &cxled->cxld.hpa_range; + struct cxl_region_context ctx; struct cxl_region_params *p; bool attach =3D false; int rc; =20 + ctx =3D (struct cxl_region_context) { + .cxled =3D cxled, + .hpa_range =3D cxled->cxld.hpa_range, + .interleave_ways =3D cxled->cxld.interleave_ways, + .interleave_granularity =3D cxled->cxld.interleave_granularity, + }; + struct cxl_root_decoder *cxlrd __free(put_cxl_root_decoder) =3D cxl_find_root_decoder(cxled); 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This requires the endpoint decoders to be an SPA, which is not the case for systems that need address translation. Add a separate @hpa_range argument to function cxl_calc_interleave_pos() to specify the address range. Now it is possible to pass the SPA translated address range of an endpoint decoder to function cxl_calc_interleave_pos(). Refactor only, no functional changes. Patch is a prerequisite to implement address translation. Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 07adc2075103..0fb11017f16d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1858,6 +1858,7 @@ static int find_pos_and_ways(struct cxl_port *port, s= truct range *range, /** * cxl_calc_interleave_pos() - calculate an endpoint position in a region * @cxled: endpoint decoder member of given region + * @hpa_range: translated HPA range of the endpoint * * The endpoint position is calculated by traversing the topology from * the endpoint to the root decoder and iteratively applying this @@ -1870,11 +1871,11 @@ static int find_pos_and_ways(struct cxl_port *port,= struct range *range, * Return: position >=3D 0 on success * -ENXIO on failure */ -static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled) +static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled, + struct range *hpa_range) { struct cxl_port *iter, *port =3D cxled_to_port(cxled); struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); - struct range *range =3D &cxled->cxld.hpa_range; int parent_ways =3D 0, parent_pos =3D 0, pos =3D 0; int rc; =20 @@ -1912,7 +1913,8 @@ static int cxl_calc_interleave_pos(struct cxl_endpoin= t_decoder *cxled) if (is_cxl_root(iter)) break; =20 - rc =3D find_pos_and_ways(iter, range, &parent_pos, &parent_ways); + rc =3D find_pos_and_ways(iter, hpa_range, &parent_pos, + &parent_ways); if (rc) return rc; =20 @@ -1922,7 +1924,7 @@ static int cxl_calc_interleave_pos(struct cxl_endpoin= t_decoder *cxled) dev_dbg(&cxlmd->dev, "decoder:%s parent:%s port:%s range:%#llx-%#llx pos:%d\n", dev_name(&cxled->cxld.dev), dev_name(cxlmd->dev.parent), - dev_name(&port->dev), range->start, range->end, pos); + dev_name(&port->dev), hpa_range->start, hpa_range->end, pos); =20 return pos; } @@ -1935,7 +1937,7 @@ static int cxl_region_sort_targets(struct cxl_region = *cxlr) for (i =3D 0; i < p->nr_targets; i++) { struct cxl_endpoint_decoder *cxled =3D p->targets[i]; =20 - cxled->pos =3D cxl_calc_interleave_pos(cxled); + cxled->pos =3D cxl_calc_interleave_pos(cxled, &cxlr->hpa_range); /* * Record that sorting failed, but still continue to calc * cxled->pos so that follow-on code paths can reliably @@ -2119,7 +2121,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled =3D p->targets[i]; int test_pos; =20 - test_pos =3D cxl_calc_interleave_pos(cxled); + test_pos =3D cxl_calc_interleave_pos(cxled, &cxlr->hpa_range); dev_dbg(&cxled->cxld.dev, "Test cxl_calc_interleave_pos(): %s test_pos:%d cxled->pos:%d\n", (test_pos =3D=3D cxled->pos) ? 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De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 07/11] cxl/region: Use region data to get the root decoder Date: Wed, 12 Nov 2025 21:31:34 +0100 Message-ID: <20251112203143.1269944-8-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|DS0PR12MB9727:EE_ X-MS-Office365-Filtering-Correlation-Id: d2f22042-a538-4edb-c67f-08de222a9443 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?a+l8aq/Lk6UyWQKAe2k9W6F1tbDDs9uqTKocQAp8deUhF+7UkyE5sc3lJzfg?= =?us-ascii?Q?rKaAQzowYLqZzikg4OOe7rUIHp6fplrHRhY6LXNmHsuQ7i4GVak7XUrH+1EF?= =?us-ascii?Q?Lh/HJe0HDsyxzsZ4eHx1RIs0GjEU8N7Lny8NgQaiXpnC5vqdCUSOb1955yEZ?= =?us-ascii?Q?DDsRovwOaezVpKxU2gD9k48KCDDaOjeo3G1bHyDONecCKjvMZXp2WN0Bpewq?= =?us-ascii?Q?EVmgIHG4oUWKwOxRUtt6j1XneHMgAVK9VTNwOoZi5mlBCdGC2cbiZ9NRxWVD?= =?us-ascii?Q?YbHntY3MeMlfQRWRB8AWnBmX11nL9cqcFVOn/IwLFcomxWMKBlci6RZ0CwSp?= =?us-ascii?Q?F1SGa5op1a9E6KSNDwr7vJAj9sUHVK1D6Muigwn47N1DJjGEx/yOqBsmlUGr?= =?us-ascii?Q?eM+Nq+TnDlaqrtcHPjGzw7ZtvVzfqQgH5fekFg/aolhSJ1qiUHqa9wDF7cKL?= =?us-ascii?Q?reptvMIknM9nJmhRQO7FLV+szkbZ3Bq0NewM/seODfpeT5mvJyaEU0TavxCr?= =?us-ascii?Q?jqKB9HpV99IBtR3EQQYpze8TuJq3+f5xN7/gqxWrG6JcA3Ho/wJH278FIRU2?= =?us-ascii?Q?Z7VRSpHAahNfEDmZ/W/2Vr4aIbQcfTViu06GOqzAtZxKEDcPaIz+4i9MHY1n?= =?us-ascii?Q?Jj1vmJPhoxJ3ykapqYflu5W9H907R7B/48OyFaO5oL0B9sw2/Y983A4arEHu?= =?us-ascii?Q?asGLwEJYbsFYLP10mzJlB8oZ8KAW7A1uMMKJIIXKnY6/3wcE2cY80sbabwmB?= =?us-ascii?Q?BKc3wSTntEGwmpNQURYFKZ2m6SJSoVgo80ORooOWi/AFR45w4nnbFm/9NnDc?= =?us-ascii?Q?g+nUEBKdKWKa3vUFsYVHHbid6TcibGb3ORZ+fn1DGEkQmPtJs+yWM+xhngLm?= =?us-ascii?Q?9We96keyo6vg9p8DrLjFle/QpGN6BXuDHFJ02yT6OlamFuNmunZz4WesTNvO?= =?us-ascii?Q?JtOO/KVFyQJqbwJMmjDSgYvtagIHBuPI98xEkW1jMeu7OxvyllF10rZ8Ub3Y?= =?us-ascii?Q?16luYfx74LxD+9Fc06puo7kAImuDQOdOUjC63EQS6eMkSxolHCI+WVLd/Uq2?= =?us-ascii?Q?cYdsKrXCnewd0E5kliTBW7cQKRGNPpNIuyU5ax07BzCJWmr32CRhNSwt7ZK+?= =?us-ascii?Q?d3wHqIZTMc6WSU5Q8TYoO2zvghuk+qORql8+a+Nsy0d+tX33sM0rr7Xj+K4t?= =?us-ascii?Q?SSdokcaWGCif5ldZg7HWnZxRNoFz9/3+b2HXKIbBHPeUePkm2QvCgPAX5k4U?= =?us-ascii?Q?Y89PB5jN0EFJs4R6CdhJH5PeTGBJtKptKlB05LdjD9l0CvdRHPwSVKfHruyg?= =?us-ascii?Q?kLcGsntLvia6umAV7ykX1zqpy9dxLD/cwwkDY3TG/iIptH6Hx3ANHgEL5IMK?= =?us-ascii?Q?UjoUNfZGsyYJD4EWR0ZKEvNRMl01BMocXWliB+SpGNCRzK+Prmr9sOgUz0Hy?= =?us-ascii?Q?QjHLZk9uK0n1iaFR2+OPSMV31evC1zTm0fjjyy/KZKZPhhHOXFPRKkn0qgKl?= =?us-ascii?Q?koYsUK/nrnNfH/Y9bm28UvVcKST1cs+7+jL4Qgo/D2AByOgNrgyklC2ZRlKY?= =?us-ascii?Q?A7gTt8g58EK9+CZBLEk=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:20.3839 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2f22042-a538-4edb-c67f-08de222a9443 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9727 Content-Type: text/plain; charset="utf-8" To find a region's root decoder, the endpoint's HPA range is used to search the matching decoder by its range. With address translation the endpoint decoder's range is in a different address space and thus cannot be used to determine the root decoder. The region parameters are encapsulated within struc cxl_region_context and may include the translated Host Physical Address (HPA) range. Use this context to identify the root decoder rather than relying on the endpoint. Modify cxl_find_root_decoder() and add the region context as parameter. Rename this function to get_cxl_root_decoder() as a counterpart to put_cxl_root_decoder(). Simplify the implementation by removing function cxl_port_find_switch_decode(). The function is unnecessary because it is not referenced or utilized elsewhere in the code. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 50 +++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 0fb11017f16d..bdd44096ea02 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3458,47 +3458,44 @@ static int devm_cxl_add_dax_region(struct cxl_regio= n *cxlr) return rc; } =20 -static int match_decoder_by_range(struct device *dev, const void *data) +static int match_root_decoder(struct device *dev, const void *data) { const struct range *r1, *r2 =3D data; - struct cxl_decoder *cxld; + struct cxl_root_decoder *cxlrd; =20 - if (!is_switch_decoder(dev)) + if (!is_root_decoder(dev)) return 0; =20 - cxld =3D to_cxl_decoder(dev); - r1 =3D &cxld->hpa_range; - return range_contains(r1, r2); -} - -static struct cxl_decoder * -cxl_port_find_switch_decoder(struct cxl_port *port, struct range *hpa_rang= e) -{ - struct device *cxld_dev =3D device_find_child(&port->dev, hpa_range, - match_decoder_by_range); + cxlrd =3D to_cxl_root_decoder(dev); + r1 =3D &cxlrd->cxlsd.cxld.hpa_range; =20 - return cxld_dev ? to_cxl_decoder(cxld_dev) : NULL; + return range_contains(r1, r2); } =20 +/* + * Note, when finished with the device, drop the reference with + * put_device() or use the put_cxl_root_decoder helper. + */ static struct cxl_root_decoder * -cxl_find_root_decoder(struct cxl_endpoint_decoder *cxled) +get_cxl_root_decoder(struct cxl_endpoint_decoder *cxled, + struct cxl_region_context *ctx) { struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct cxl_port *port =3D cxled_to_port(cxled); struct cxl_root *cxl_root __free(put_cxl_root) =3D find_cxl_root(port); - struct cxl_decoder *root, *cxld =3D &cxled->cxld; - struct range *hpa_range =3D &cxld->hpa_range; + struct device *cxlrd_dev; =20 - root =3D cxl_port_find_switch_decoder(&cxl_root->port, hpa_range); - if (!root) { + cxlrd_dev =3D device_find_child(&cxl_root->port.dev, &ctx->hpa_range, + match_root_decoder); + if (!cxlrd_dev) { dev_err(cxlmd->dev.parent, "%s:%s no CXL window for range %#llx:%#llx\n", - dev_name(&cxlmd->dev), dev_name(&cxld->dev), - hpa_range->start, hpa_range->end); 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Wed, 12 Nov 2025 12:32:20 -0800 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 08/11] cxl: Introduce callback for HPA address ranges translation Date: Wed, 12 Nov 2025 21:31:35 +0100 Message-ID: <20251112203143.1269944-9-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|IA1PR12MB6236:EE_ X-MS-Office365-Filtering-Correlation-Id: 545736ff-3340-41f2-7827-08de222a9637 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6Ung4yST46ZRyn9zP0x7Tn7XrvoosZXzyK7HNpos8gjOORBO/BICVaU2t0RR?= =?us-ascii?Q?bvarlEJ9v179V3IxN7mWU0MHJdqu+DHktjDNmzOD91hvzbGvsrLAI3RVqFKB?= =?us-ascii?Q?iMnXG6XneSgSCA0phneZtJywb2VBTXXoevOSSGJVcDWwaQK4S/0aJu2CsL1m?= =?us-ascii?Q?/WQqIg+fRuvGSEd7SeNRgUZ18WK8rxXWeJSCnVxsdhpnecPL6vatL7WQ8Rmi?= =?us-ascii?Q?K4Ff2eqvs4mzS6bMsAgpRa0vNQ+pX0KjyEOtpq2MfB6+cBdi0bnnOMTuztsR?= =?us-ascii?Q?Va3+5Pn1KjOYOxuEcLAxIvA6TaLKKqGqiIk8FWq6hbZqJteUTVLsyCVgkKbf?= =?us-ascii?Q?eo0aU4Loe+ewbqbnCMeou5N+7ApQBrruJq79ORjAsryZEhTEmJn1hLG90ZZL?= =?us-ascii?Q?klQVlqdpIGBM1WzSC/uMfVSHA3QXGU3ltdq/ootg7eZCGaiZFCjg0g+YdGN1?= =?us-ascii?Q?sNqjx+3uDrcIvLDsweP4qwIl2t6bziW4iUhxRYod1BCQpwUlHi61rcz6egkY?= =?us-ascii?Q?b9N0JqQ2YPS0o61vsMdfaeKXOfwDelWBfvD0WkWhAaf1N5PwSRDZrAhLTtUW?= =?us-ascii?Q?1e7affbL+MGxScmBnLxdzSjohBh5D0UiSMMEMsW8UQuRaiKTAV6ebWqvpbdb?= =?us-ascii?Q?lTw9izivW2a1H/dJb9aGhX5XX8o5ZFOFWQ06kjy6p9r80s6JonW0ISVKD2AH?= =?us-ascii?Q?6AJBboyemO7wZdR3Vqs9qZ9U4dHlWSvhqzTdYhe9Cv0IikbQRW6ZJq9EX16C?= =?us-ascii?Q?D3atDuncxQmCb0rDk6+ZHdH5x8/TFz3HXCtzpSX4FIApKwQ4oKBNVgKtOchL?= =?us-ascii?Q?6KJlzttGQ1R/fgGNOYi650ta7rXImt9XiHE4YGcpU/Aicb9anxViugVzdmcd?= =?us-ascii?Q?fdEir0gKDE7EGLEtFJ8i6fD+6V8DsG4wQjiFUEVjXzEYIK/GFVeTY6/mEnGg?= =?us-ascii?Q?/LFhPpYrUZlLkC4IuQh8CxzaWRfTm5fNjt33Wp8Fyd+U/uFW/73aI5K6gWoT?= =?us-ascii?Q?fHYBH4tAV42EPERjzA30WE0vrdYMn0r+8SExJ2TEp9zWyiijctKC9vnS9Nv0?= =?us-ascii?Q?8bgT9Uj2XWIWhVgvsx+MC55wLrYw72VdOMuxfUdpOky0EAKztVe2FvcayFWk?= =?us-ascii?Q?rgcJVxvkAaWaji2NsLo7Z86kETkraodSddtasZfEz8hldfT0mL4R39sr1+dx?= =?us-ascii?Q?x84TzGwuVDSdfBsYP5bNvLVXETkAsPCUDcOnZkndRVkW5WZWvLMTwDcbxftM?= =?us-ascii?Q?1nczcH3SrNegUI1OPIT48uqCmslttDqdgXCgoa4yOp3dD0QBHIaZ7X7/vCb2?= =?us-ascii?Q?8qn8rnQG3JSUZ3P3jZXgJ6zI0sM262HJdYbeTneQPLGqXRCCaP0xS/Nhlew4?= =?us-ascii?Q?m72WzbGxvy2tAT6KfiJU7E9wPVymDOE2YqmL86GK2nQvrT+b1bnMnfpc+b2t?= =?us-ascii?Q?SSj2qFh+SRtAUrwSO1rCXdufklGSjEtn0OUcwr/1u9fCCwpvyJh28Q7brm6Y?= =?us-ascii?Q?8EIiWqyrjVCU5aa25V1IcC2Ube9yf/I33Nm8MTz3bamkeGpqzavjMQ49olvr?= =?us-ascii?Q?nwG9jR2pSlG6gC+5ksw=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:23.6704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 545736ff-3340-41f2-7827-08de222a9637 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003448.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6236 Content-Type: text/plain; charset="utf-8" Introduce a callback to translate an endpoint's HPA range to the address range of the root port which is the System Physical Address (SPA) range used by a region. The callback can be set if a platform needs to handle address translation. The callback is attached to the root port. An endpoint's root port can easily be determined in the PCI hierarchy without any CXL specific knowledge. This allows the early use of address translation for CXL enumeration. Address translation is esp. needed for the detection of the root decoders. Thus, the callback is embedded in struct cxl_root_ops instead of struct cxl_rd_ops. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 19 +++++++++++++++++++ drivers/cxl/cxl.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index bdd44096ea02..451e5492911c 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3472,6 +3472,15 @@ static int match_root_decoder(struct device *dev, co= nst void *data) return range_contains(r1, r2); } =20 +static int translate_hpa_range(struct cxl_root *cxl_root, + struct cxl_region_context *ctx) +{ + if (!cxl_root->ops.translate_hpa_range) + return 0; + + return cxl_root->ops.translate_hpa_range(cxl_root, ctx); +} + /* * Note, when finished with the device, drop the reference with * put_device() or use the put_cxl_root_decoder helper. @@ -3484,6 +3493,16 @@ get_cxl_root_decoder(struct cxl_endpoint_decoder *cx= led, struct cxl_port *port =3D cxled_to_port(cxled); struct cxl_root *cxl_root __free(put_cxl_root) =3D find_cxl_root(port); struct device *cxlrd_dev; + int rc; + + rc =3D translate_hpa_range(cxl_root, ctx); + if (rc) { + dev_err(cxlmd->dev.parent, + "%s:%s Failed to translate address range %#llx:%#llx\n", + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), + ctx->hpa_range.start, ctx->hpa_range.end); + return ERR_PTR(rc); + } =20 cxlrd_dev =3D device_find_child(&cxl_root->port.dev, &ctx->hpa_range, match_root_decoder); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 11709f0f91d6..8d056095402a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -644,6 +644,7 @@ struct cxl_root_ops { int (*qos_class)(struct cxl_root *cxl_root, struct access_coordinate *coord, int entries, int *qos_class); + int (*translate_hpa_range)(struct cxl_root *cxl_root, void *data); }; =20 /** --=20 2.47.3 From nobody Sun Feb 8 06:04:32 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011064.outbound.protection.outlook.com [40.107.208.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A692D131D; 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Wed, 12 Nov 2025 12:32:23 -0800 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 09/11] cxl/acpi: Prepare use of EFI runtime services Date: Wed, 12 Nov 2025 21:31:36 +0100 Message-ID: <20251112203143.1269944-10-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|SA3PR12MB9159:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e3da646-4278-4ef0-2ebf-08de222a9819 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?x7hpUOiATvD9mIJ8u9WJf9Jup3dFj6YC3hG2WNw0nMJSmKNlI8cPy4ldPD2M?= =?us-ascii?Q?jKy9Jxm7ENYvQZ6+SpmBhuhDn5Rk13VGIFJFgKrWhrI6k8ioC+ViYIag4iXu?= =?us-ascii?Q?SuO1/KutaHnVzNZCpUPV6rtzfvhY02CpXbNNRiKb2/9aLITqWKdfxpfCQzS1?= =?us-ascii?Q?78p8y0UPl300hxDvkfz61QeUyYA3Wem1ZEBX8piRtBAS4aZx4c+1/QNMiZHt?= =?us-ascii?Q?jjGHvKBLa2HrssOTZ/G0tDsTJzb7mO5HJgsYSgSzSCD1uEbTl6HBRHRbNT6P?= =?us-ascii?Q?Ssi27IfonAvlFqw+eR1OEYEO6wdIS02l8xMQaDd8IruryPwx8e7Kr0CJJOxf?= =?us-ascii?Q?kCK3mU9hnJec7PW378p+625xPMHeUJk28CzF751f80d/PUC4kpBDdas4B1sS?= =?us-ascii?Q?R4O5eIZikEE3dKkyQiuqk021kI/Jz8rekJliVotBZMuvOmKF7ZYmP5JuD0IJ?= =?us-ascii?Q?ynApljqA/y+53QHgtw/BEInGxT3SuBanuy1hkzckntMoAHb3iKQddMO74M27?= =?us-ascii?Q?pIOzLolinsrc8ef8M4ESwA4UVu+Sbu6b43VbIWKo/XPi23reQinIpr1lc0Dv?= =?us-ascii?Q?FnEIWG4sUu26wOVknwvBVfnLsL2e6qPl6vHZpS2pd9WnW11wUdIWSVTexuRe?= =?us-ascii?Q?RNjms6GtwuV9kNUzwmql1eMBddJh8ZKf0NMYlB5O9wsIQIgz4skKhDFfE+uU?= =?us-ascii?Q?YPKoEfCb0+OKV4Aj+FhAgxLnQEBRZvOggE43y2a7yQxebetOqEq3mfuRyu0o?= =?us-ascii?Q?UnEnozkDPgPST84wgO5gNLZ4NGoC/vgdXIXndW1ssTGxs0DTqw3iNfdG3Kub?= =?us-ascii?Q?ORIrrbcGgkgDR8UEWIRd+jryocaofUrmxSM7EO+pYn2l+ZThXAnU5V/2jcTh?= =?us-ascii?Q?Z4rE1oUZKJwRMYvPzNMCzJ6IlnJk/tJTK5x1yF+7UB8+xQbo/iNq/tg0KOOB?= =?us-ascii?Q?CXOXeF8TMnBfkL6YJMQU0bYFeVD/oL2jk+An9/1cnBp+s96uoHjANzgMkWeA?= =?us-ascii?Q?e3fgFUFvx4PWtz79sgoi70iu43vctsu6KyOHsEXZm2b7mmgOQS2WOBGzNwrQ?= =?us-ascii?Q?II7Oj6iPNlXZQCS6KL/eCMl2Ng5/QTNa1xDzd6fzuRLLhxDZJMfdr6V4iU5D?= =?us-ascii?Q?3eldBUIhN3UNyZxaKmrGsMLqdDq/ZMivSlxIjuJP/v0zsmJer1BlE+o06Aw1?= =?us-ascii?Q?TN9j+VVly2fZ2589tKnVePKp0hT8tvG7qo3QDa9fi9k6nUD4GTmuvxwpmFCn?= =?us-ascii?Q?pU6n4ht2gCXXGm/cgZkLVepIL9bhQC3OMkMrQhDjw5aW/f5JhRYDUJqG61g2?= =?us-ascii?Q?Vg68cF3yelw8evmBM3/axEBJCq5ikc8zH120wRm9T6qMTfOGimYfk3WpDUCH?= =?us-ascii?Q?twrIrE3nfh1AL2BhLvJbFKZdZxUIgJSwgbiiyUEjuyPiqJr06aKgax4Ts1J5?= =?us-ascii?Q?fbNePuhZYik6K4xXs55G3WnA5WAv/vGwcYy3mH2VRie8XRxhkYwObR6DsKo9?= =?us-ascii?Q?E6lE57ZX3zr5rqiwRxupxxgHrzhUfLl3xLOTK98w1dFuaXNGrr+UaZLcvEog?= =?us-ascii?Q?jyuKFXkG6IBQAxovh1c=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:26.8146 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e3da646-4278-4ef0-2ebf-08de222a9819 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9159 Content-Type: text/plain; charset="utf-8" In order to use EFI runtime services, esp. ACPI PRM which uses the efi_rts_wq workqueue, initialize EFI before CXL ACPI. There is a subsys_initcall order dependency if driver is builtin: subsys_initcall(cxl_acpi_init); subsys_initcall(efisubsys_init); Prevent the efi_rts_wq workqueue being used by cxl_acpi_init() before its allocation. Use subsys_initcall_sync(cxl_acpi_init) to always run efisubsys_init() first. Reported-by: Gregory Price Tested-by: Joshua Hahn Reviewed-by: Joshua Hahn Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/acpi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 4fe489244a77..52b3c162a564 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -1012,8 +1012,12 @@ static void __exit cxl_acpi_exit(void) cxl_bus_drain(); } =20 -/* load before dax_hmem sees 'Soft Reserved' CXL ranges */ -subsys_initcall(cxl_acpi_init); +/* + * Load before dax_hmem sees 'Soft Reserved' CXL ranges. Use + * subsys_initcall_sync() since there is an order dependency with + * subsys_initcall(efisubsys_init), which must run first. + */ +subsys_initcall_sync(cxl_acpi_init); =20 /* * Arrange for host-bridge ports to be active synchronous with --=20 2.47.3 From nobody Sun Feb 8 06:04:32 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010064.outbound.protection.outlook.com [52.101.61.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 044D72D12F1; Wed, 12 Nov 2025 20:32:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.64 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762979560; cv=fail; b=oZ3zUWGVX7T8Vn+dqXITD6ZDKYFsZVrj0tnd2zjQo6hTirD0zSgS2dwcvqH/OeI05ypSXBRmRm7jd4+F2rzjTHdPDB1PGoajsGXRwyXyi7y1RkJsMEDZrqrhe95h+T3+QyxxWKDkF2KZ6xxicHEBfmDfaRhQiQS3DqkQUrdsvtY= ARC-Message-Signature: i=2; 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De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 10/11] cxl: Enable AMD Zen5 address translation using ACPI PRMT Date: Wed, 12 Nov 2025 21:31:37 +0100 Message-ID: <20251112203143.1269944-11-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|PH8PR12MB6675:EE_ X-MS-Office365-Filtering-Correlation-Id: ff723e9a-666a-4e18-e24a-08de222a9a61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?bTBMaXM4aXJlYzBPTjVxZlBVWTFtRERzT0pNU0pUZVdzTkNZd3ZLVklmd0xU?= =?utf-8?B?YzFXWCtqQUVJUStmajZZcFNVL1lZMm5OZC9IaEFhLzBTYjI0TFFjcVBSY3pK?= =?utf-8?B?UG41d2x1TGorZXlBZS9jbVZCenM1RmM1bGpVTWM0d0lEbzQ0TTRUQmhZem9y?= =?utf-8?B?aDl3eVNPQTlvWTVjQkkrUU1CbzdvcTdsckZ4d0hzYTVGUisrdEtWTHY5bjJR?= =?utf-8?B?eEo3MzVtQWhRakx0aGZVazIxTDVhL1RMbGlRK2Z6UjlMZ0Zub2cwSXFNWWtX?= =?utf-8?B?bHByallSMVFrT3BSM3VTL2ZPeVFzVWkrRVBNbFpHVVo0N3lFUHhjVW9qNTBR?= =?utf-8?B?RytRZks2SnJKSHEwR2ZVcHBPVUc5OGVpbHdiYS9UZ1NmcEh3NW5vUUt4ZXNh?= =?utf-8?B?YzN5cS8rSk9kOGhtMDNFVnR5UkxNdzBvUXVXcGNpaXZldElnQkt2RDF1QnF1?= =?utf-8?B?UlJuSC92dkkzeitZdUtUWmtVck5YaGlWMFozdTA0OXQ4TUhlVUovL2h3YnNH?= =?utf-8?B?UlhNL3c1OVg5bDIzN2EzZUpWdk5DNmwvK0FqcFFqNGFvV1Boa1RGMUFQWDZW?= =?utf-8?B?VldFMmhGMW1UOTlDb3J2NUsyY2FuM1UreTZ3alVGN1JZUlpuKzAvOTVEVi92?= =?utf-8?B?Q2tLbVE3QmlaMVZhQ1F4bm1oVFFka0QxMktSdE1NU0Y5ZFI5VjdlcUx2UEE1?= =?utf-8?B?YnUyZGRMSlZ3ZG9JT0NuTGNVREpuNlA1Y3VSdnp6eVd0WVZyNUo3c3YzZEVV?= =?utf-8?B?U3NIeThNV2tpSUwrVm9JQitTZUlxMFl3NTRwbE11NXRBV2Vjd1ltNTdGZUpn?= =?utf-8?B?aWtIdXRuTHRac1JWMVRZNWxBQ21zN2IrWkhpNXYzeXBlTGlxRjNXM1htNzhE?= =?utf-8?B?VTNjdjBoR1NhL1pvdElJZWpIeFhqTXhBY01uMXBJVGdXMklzRnhSZHJrUkdO?= =?utf-8?B?bVhxd3RCalVjZ1NnTkQvSlpFQ0MvSEtvaElBaXd1a0dkeVVuT3Z3M1o2aXFp?= =?utf-8?B?cnphL0lyM2pQOWkyYWNMU2F5dDgrRjc4NzhiTWQ5VEFKaWROVUQzRnl2ZzFr?= =?utf-8?B?VGRkRFoyT2RISjFkYmk2VzdVZFYyOGVSc0xFYm01WjNsMktCcFZram4rVDRR?= =?utf-8?B?WFI2dWNBN0pSbGVUVlhhVTBhOWw3YnA1VXllc05yMG14SzNDb2h2UGN1TEFL?= =?utf-8?B?MkhqZm5kZlA0ZGMxUFMrZGlNb3JLcHR0VjEzem1veDd5Y1hxYk5YTnBlRDJS?= =?utf-8?B?UGlFRFlTNUlkbk54YlVDcWtuQ2g3MDkrcHA4MjdKQS9IaVNQWWg5WUNXZWtR?= =?utf-8?B?cStLMzdtYnNVQ1poYURSdTBlZkxyYitjbHRLZGk5WVZpQU1YN251dENEL1FH?= =?utf-8?B?RkhhbWt5bUloUmUzalk4cy8yMllxa0dRejA0c0hyQnVlTURoMmlDamJlR0oy?= =?utf-8?B?bTZpRTBZaWhZVzBFOTB5azIrdk5TdkZpaDdrb1o4S1RtK1RTMnhBVHE2ODM4?= =?utf-8?B?T29GcGZzcTlybytoMTJKdHlLNXJOdTZTSDlXMmw1S1BDcFlib3EwTkVxM0xK?= =?utf-8?B?YXNwOHdIWkFMMXFNMEFCSmptS01XbHhzdG1pOTRzLzV4eW1SbHNlMkh5bGVB?= =?utf-8?B?d2szT0NDR05xc2dkblloYUM0VElUV1YzMWptQjViZUU2ci9ZWWFhcU9zNzBP?= =?utf-8?B?eWdrUGRLeE5BVkJvUGZERjdySE4vVUNoVlZCcEpURmpqWXVTdUtBNWpsZ1N1?= =?utf-8?B?WmU2eDFTM3dOODc0aTV0ajE4eWlaUEFpZU03NFpNejA3bzVrQWVVNzBkUkJZ?= =?utf-8?B?N2sycHpLbnVBZG5nMTNpb01heTlwenRNZXRRcktlSmRpWkl1ZnpGRTlWSEh1?= =?utf-8?B?b2FRcHVLaXVrYzBqQ1ZkRDJXTENQOGtvR3JsSXd0VDJrOWhlL2pPblk5VXpY?= =?utf-8?B?ZlVXV0lnb25vSVNvaWQ4WVlwR3FrM2lCOU5ueldDc29lK2x1NzQrYUhnaDJF?= =?utf-8?B?cFBKVkxCWDlBbEV5eHRSQmplSUswVWlwWUdWNUxLdWlXeEdQZm9iOVlibm1t?= =?utf-8?B?VW45cGY5VXZ1TFlzQU5DalNLU05WSzFiQmozNXc3ODB0MENSeU4vakU5Y0pQ?= =?utf-8?Q?czaM=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:30.6531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff723e9a-666a-4e18-e24a-08de222a9a61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003448.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6675 Add AMD Zen5 support for address translation. Zen5 systems may be configured to use 'Normalized addresses'. Then, host physical addresses (HPA) are different from their system physical addresses (SPA). The endpoint has its own physical address space and an incoming HPA is already converted to the device's physical address (DPA). Thus it has interleaving disabled and CXL endpoints are programmed passthrough (DPA =3D=3D HPA). Host Physical Addresses (HPAs) need to be translated from the endpoint to its CXL host bridge, esp. to identify the endpoint's root decoder and region's address range. ACPI Platform Runtime Mechanism (PRM) provides a handler to translate the DPA to its SPA. This is documented in: AMD Family 1Ah Models 00h=E2=80=930Fh and Models 10h=E2=80=931Fh ACPI v6.5 Porting Guide, Publication # 58088 https://www.amd.com/en/search/documentation/hub.html With Normalized Addressing this PRM handler must be used to translate an HPA of an endpoint to its SPA. Do the following to implement AMD Zen5 address translation: Introduce a new file core/atl.c to handle ACPI PRM specific address translation code. Naming is loosely related to the kernel's AMD Address Translation Library (CONFIG_AMD_ATL) but implementation does not depend on it, nor it is vendor specific. Use Kbuild and Kconfig options respectively to enable the code depending on architecture and platform options. AMD Zen5 systems support the ACPI PRM CXL Address Translation firmware call (see ACPI v6.5 Porting Guide, Address Translation - CXL DPA to System Physical Address). Firmware enables the PRM handler if the platform has address translation implemented. Check firmware and kernel support of ACPI PRM using the specific GUID. On success enable address translation by setting up the earlier introduced root port callback, see function cxl_prm_translate_hpa_range(). Setup is done in cxl_setup_prm_address_translation(), it is the only function that needs to be exported. For low level PRM firmware calls, use the ACPI framework. Identify the region's interleaving ways by inspecting the address ranges. Also determine the interleaving granularity using the address translation callback. Note that the position of the chunk from one interleaving block to the next may vary and thus cannot be considered constant. Address offsets larger than the interleaving block size cannot be used to calculate the granularity. Thus, probe the granularity using address translation for various HPAs in the same interleaving block. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/Kconfig | 5 + drivers/cxl/acpi.c | 2 + drivers/cxl/core/Makefile | 1 + drivers/cxl/core/atl.c | 197 ++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 7 ++ 5 files changed, 212 insertions(+) create mode 100644 drivers/cxl/core/atl.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..103950a9b73e 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -233,4 +233,9 @@ config CXL_MCE def_bool y depends on X86_MCE && MEMORY_FAILURE =20 +config CXL_ATL + def_bool y + depends on CXL_REGION + depends on ACPI_PRMT && AMD_NB + endif diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 52b3c162a564..d5119de7f5a9 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -932,6 +932,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) cxl_root->ops.qos_class =3D cxl_acpi_qos_class; root_port =3D &cxl_root->port; =20 + cxl_setup_prm_address_translation(cxl_root); + rc =3D bus_for_each_dev(adev->dev.bus, NULL, root_port, add_host_bridge_dport); if (rc < 0) diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..11fe272a6e29 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -20,3 +20,4 @@ cxl_core-$(CONFIG_CXL_REGION) +=3D region.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o +cxl_core-$(CONFIG_CXL_ATL) +=3D atl.o diff --git a/drivers/cxl/core/atl.c b/drivers/cxl/core/atl.c new file mode 100644 index 000000000000..3b02999d3c59 --- /dev/null +++ b/drivers/cxl/core/atl.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include + +#include +#include "core.h" + +/* + * PRM Address Translation - CXL DPA to System Physical Address + * + * Reference: + * + * AMD Family 1Ah Models 00h=E2=80=930Fh and Models 10h=E2=80=931Fh + * ACPI v6.5 Porting Guide, Publication # 58088 + */ + +static const guid_t prm_cxl_dpa_spa_guid =3D + GUID_INIT(0xee41b397, 0x25d4, 0x452c, 0xad, 0x54, 0x48, 0xc6, 0xe3, + 0x48, 0x0b, 0x94); + +struct prm_cxl_dpa_spa_data { + u64 dpa; + u8 reserved; + u8 devfn; + u8 bus; + u8 segment; + u64 *spa; +} __packed; + +static u64 prm_cxl_dpa_spa(struct pci_dev *pci_dev, u64 dpa) +{ + struct prm_cxl_dpa_spa_data data; + u64 spa; + int rc; + + data =3D (struct prm_cxl_dpa_spa_data) { + .dpa =3D dpa, + .devfn =3D pci_dev->devfn, + .bus =3D pci_dev->bus->number, + .segment =3D pci_domain_nr(pci_dev->bus), + .spa =3D &spa, + }; + + rc =3D acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data); + if (rc) { + pci_dbg(pci_dev, "failed to get SPA for %#llx: %d\n", dpa, rc); + return ULLONG_MAX; + } + + pci_dbg(pci_dev, "PRM address translation: DPA -> SPA: %#llx -> %#llx\n",= dpa, spa); + + return spa; +} + +static int cxl_prm_translate_hpa_range(struct cxl_root *cxl_root, void *da= ta) +{ + struct cxl_region_context *ctx =3D data; + struct cxl_endpoint_decoder *cxled =3D ctx->cxled; + struct cxl_decoder *cxld =3D &cxled->cxld; + struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); + struct range hpa_range =3D ctx->hpa_range; + struct pci_dev *pci_dev; + u64 spa_len, len =3D range_len(&hpa_range); + u64 addr, base_spa, base; + int ways, gran; + + /* + * When Normalized Addressing is enabled, the endpoint maintains a 1:1 + * mapping between HPA and DPA. If disabled, skip address translation + * and perform only a range check. + */ + if (hpa_range.start !=3D cxled->dpa_res->start) + return 0; + + if (!IS_ALIGNED(hpa_range.start, SZ_256M) || + !IS_ALIGNED(hpa_range.end + 1, SZ_256M)) { + dev_dbg(cxld->dev.parent, + "CXL address translation: Unaligned decoder HPA range: %#llx-%#llx(%s)\= n", + hpa_range.start, hpa_range.end, dev_name(&cxld->dev)); + return -ENXIO; + } + + /* + * Endpoints are programmed passthrough in Normalized Addressing mode. + */ + if (ctx->interleave_ways !=3D 1) { + dev_dbg(&cxld->dev, "unexpected interleaving config: ways: %d granularit= y: %d\n", + ctx->interleave_ways, ctx->interleave_granularity); + return -ENXIO; + } + + if (!cxlmd || !dev_is_pci(cxlmd->dev.parent)) { + dev_dbg(&cxld->dev, "No endpoint found: %s, range %#llx-%#llx\n", + dev_name(cxld->dev.parent), hpa_range.start, + hpa_range.end); + return -ENXIO; + } + + pci_dev =3D to_pci_dev(cxlmd->dev.parent); + + /* Translate HPA range to SPA. */ + base =3D hpa_range.start; + hpa_range.start =3D prm_cxl_dpa_spa(pci_dev, hpa_range.start); + hpa_range.end =3D prm_cxl_dpa_spa(pci_dev, hpa_range.end); + base_spa =3D hpa_range.start; + + if (hpa_range.start =3D=3D ULLONG_MAX || hpa_range.end =3D=3D ULLONG_MAX)= { + dev_dbg(cxld->dev.parent, + "CXL address translation: Failed to translate HPA range: %#llx-%#llx:%#= llx-%#llx(%s)\n", + hpa_range.start, hpa_range.end, ctx->hpa_range.start, + ctx->hpa_range.end, dev_name(&cxld->dev)); + return -ENXIO; + } + + /* + * Since translated addresses include the interleaving offsets, align + * the range to 256 MB. + */ + hpa_range.start =3D ALIGN_DOWN(hpa_range.start, SZ_256M); + hpa_range.end =3D ALIGN(hpa_range.end, SZ_256M) - 1; + + spa_len =3D range_len(&hpa_range); + if (!len || !spa_len || spa_len % len) { + dev_dbg(cxld->dev.parent, + "CXL address translation: HPA range not contiguous: %#llx-%#llx:%#llx-%= #llx(%s)\n", + hpa_range.start, hpa_range.end, ctx->hpa_range.start, + ctx->hpa_range.end, dev_name(&cxld->dev)); + return -ENXIO; + } + + ways =3D spa_len / len; + gran =3D SZ_256; + + /* + * Determine interleave granularity + * + * Note: The position of the chunk from one interleaving block to the + * next may vary and thus cannot be considered constant. Address offsets + * larger than the interleaving block size cannot be used to calculate + * the granularity. + */ + if (ways > 1) { + while (gran <=3D SZ_16M) { + addr =3D prm_cxl_dpa_spa(pci_dev, base + gran); + if (addr !=3D base_spa + gran) + break; + gran <<=3D 1; + } + } + + if (gran > SZ_16M) { + dev_dbg(cxld->dev.parent, + "CXL address translation: Cannot determine granularity: %#llx-%#llx:%#l= lx-%#llx(%s)\n", + hpa_range.start, hpa_range.end, ctx->hpa_range.start, + ctx->hpa_range.end, dev_name(&cxld->dev)); + return -ENXIO; + } + + ctx->hpa_range =3D hpa_range; + ctx->interleave_ways =3D ways; + ctx->interleave_granularity =3D gran; + + dev_dbg(&cxld->dev, + "address mapping found for %s (hpa -> spa): %#llx+%#llx -> %#llx+%#llx w= ays:%d granularity:%d\n", + dev_name(cxlmd->dev.parent), base, len, hpa_range.start, + spa_len, ways, gran); + + return 0; +} + +void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) +{ + struct device *host =3D cxl_root->port.uport_dev; + u64 spa; + struct prm_cxl_dpa_spa_data data =3D { .spa =3D &spa }; + int rc; + + /* + * Applies only to PCIe Host Bridges which are children of the CXL Root + * Device (HID=3D=E2=80=9CACPI0017=E2=80=9D). Check this and drop cxl_tes= t instances. + */ + if (!acpi_match_device(host->driver->acpi_match_table, host)) + return; + + /* Check kernel (-EOPNOTSUPP) and firmware support (-ENODEV) */ + rc =3D acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data); + if (rc =3D=3D -EOPNOTSUPP || rc =3D=3D -ENODEV) + return; + + cxl_root->ops.translate_hpa_range =3D cxl_prm_translate_hpa_range; +} +EXPORT_SYMBOL_NS_GPL(cxl_setup_prm_address_translation, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 8d056095402a..0481679eb109 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -809,6 +809,13 @@ static inline void cxl_dport_init_ras_reporting(struct= cxl_dport *dport, struct device *host) { } #endif =20 +#ifdef CONFIG_CXL_ATL +void cxl_setup_prm_address_translation(struct cxl_root *cxl_root); +#else +static inline +void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {} +#endif + struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 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De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v5 11/11] cxl/atl: Lock decoders that need address translation Date: Wed, 12 Nov 2025 21:31:38 +0100 Message-ID: <20251112203143.1269944-12-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251112203143.1269944-1-rrichter@amd.com> References: <20251112203143.1269944-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|PH7PR12MB5830:EE_ X-MS-Office365-Filtering-Correlation-Id: f692d31c-8cc9-4e99-12c1-08de222a9c3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?5owwamdWue1/Ah7V5EmL1dGSWstC2i4xcVkLcKkboP7IbgGHcgYW8SM14ruY?= =?us-ascii?Q?ljrS/FdnfEGcFVGhgCSJzcDUoVRa2PR8CWOjFmESb9IZsloLzAZvMQpXhKCf?= =?us-ascii?Q?2zsWG1OtGmn0DwYpBkQT2w0fxtJLoL3x53dQjsuDxEMc0v67RbAXNcHLBE65?= =?us-ascii?Q?+U5B4LDPUm9V+WvlSR26SIS/kgQgpOIkacuYbNNV9OXHjPhpiDP9ZdJCpsVs?= =?us-ascii?Q?bGia3vkYLY/t/RMvL/rPGqoR1ggM3oC2BZ/842gyRU81i2yboZJRCQFnt6J+?= =?us-ascii?Q?pPBbKmhSGw5npTF5zQqXmBB2+77Mx0cE2NFau+xCW1V3vUa+wW2jvnZfXNX8?= =?us-ascii?Q?wAEVKreaN6uU5Dfwmzn/4fyFxSJ4VEUjmi1ctj4qaR7ymOj/suCJBLgMSmKu?= =?us-ascii?Q?aiVzqTQni/5TmQXCeNQA+6++TKnbNVoR78JALHuaxtfIbJfkAo2lXefqGc/3?= =?us-ascii?Q?hOlQBL/k6WcOt6EluGhrB2VIf9TTXwYwy0mEShM241DgKE8syO3o2TTBpuPE?= =?us-ascii?Q?V2AtN06px9wtFC/8EKPGqu9D09wvZIWlTkTrTt/cj20SpW5QuKEfVkyRkOOw?= =?us-ascii?Q?cIhLdnI4xMJujqwheAaHUJAdEJRroDg1GSYbKQDXj/WVifqt11XYVB2iwanX?= =?us-ascii?Q?j4godB+CTEPqOdogsYabmG5o/bGf0JpZvkmGjnHkJPsGLuaw32i6x0PQodUn?= =?us-ascii?Q?+iBjwOoFImpzp2YPMLWC+tZR9XAV6IWzS7t1J28wTMkGCuJuzmTeTr+3RrZs?= =?us-ascii?Q?HcGcjpzurmVejNhwttcc5UBmo+LX66D9B+IG4YWOAhzHG4Vq46lfw9rbCKMs?= =?us-ascii?Q?cQlhd9936J0Iw5Ig81arrCd1y0SB+tMkNDuDtucnFSHWu7pyodAa2d+9kGYt?= =?us-ascii?Q?JeGMs5eNu77md0HAmxcOslzzEPaoMXsH/2sDlROBa7bmsftzgD0U+Roid0ql?= =?us-ascii?Q?o6UKB4jgNMp/wgdnIrgxl4MFFJ6JNwIUmfG4wXnMYLXYfo/kRvgSmD+3XzQp?= =?us-ascii?Q?oCxg78LBHi7t5PZzPM6rOrIAjf4bVv2zqeBJQ+Hz5nSi4Kym33x1g5BTkZVk?= =?us-ascii?Q?dflRf+rDhuZpJv+IkrM30deQXJkWQF4eqzRNIf6mMMqbPEZmqHXfCo1svm3K?= =?us-ascii?Q?iPWPuTbwO5QRTYOPFSv6nphpWgYBu6wttyZzuAoDFj/eOhQhQjhVA0/fg7u6?= =?us-ascii?Q?Wnnrl6ss2sl50hOFXeWbfxI9Q+39vbs8kplnWCByiaLWMVbXSyD3e4Hbx1NB?= =?us-ascii?Q?AiFn4shJGuyZiUhu0ZWXDyO9oAKoqHwyqIEOGM1xQeu8W7V5pmwfZo+J2LpN?= =?us-ascii?Q?8LKaMO1M4JBHO2oxhw7ZMGXswLlXo5wZ7iy4cMn9bxGGBESontvurOJBbBsq?= =?us-ascii?Q?nPWg2gz2dbeJzh/cfHXYyQ7ROprMbzZlZzV/q3/7dw3nxyugAopk32lXU05+?= =?us-ascii?Q?rXJl6JwFSB/2Yn211Fj3NlyOuqkeb/HAnFtcpzq1mSUgrllUsLZb+h1f2t9M?= =?us-ascii?Q?I8LHxL55ojICvhUq1cAS9uPL6uczMSxU4YlrWugC2rp+te5x+M3FuVX4iosW?= =?us-ascii?Q?JFkr4qnnCB3Bcw8RXnk=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 20:32:33.7477 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f692d31c-8cc9-4e99-12c1-08de222a9c3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5830 Content-Type: text/plain; charset="utf-8" There is only support to translate addresses from an endpoint to its CXL host bridge, but not in the opposite direction from the bridge to the endpoint. Thus, the endpoint address range cannot be determined and setup manually for a given SPA range of a region. If the endpoint has address translation enabled, lock it to prevent the kernel from reconfiguring it. This is more a limitation of the kernel implementation rather than the BIOS. The BIOS provides enought information by CFMWS, PRM, HDM and PCI topology. In theory and if there is demand for it, support could be added for driver region setup. For that reason the lock bit should be set by the kernel instead of the BIOS. Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter --- drivers/cxl/core/atl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/cxl/core/atl.c b/drivers/cxl/core/atl.c index 3b02999d3c59..4f645f71b397 100644 --- a/drivers/cxl/core/atl.c +++ b/drivers/cxl/core/atl.c @@ -161,6 +161,16 @@ static int cxl_prm_translate_hpa_range(struct cxl_root= *cxl_root, void *data) return -ENXIO; } =20 + /* + * There is only support to translate from the endpoint to its + * parent port, but not in the opposite direction from the + * parent to the endpoint. Thus, the endpoint address range + * cannot be determined and setup manually. If the address range + * was translated and modified, forbid reprogramming of the + * decoders and lock them. + */ + cxld->flags |=3D CXL_DECODER_F_LOCK; + ctx->hpa_range =3D hpa_range; ctx->interleave_ways =3D ways; ctx->interleave_granularity =3D gran; --=20 2.47.3