From nobody Mon Feb 9 13:17:21 2026 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E84572C0F6F for ; Wed, 12 Nov 2025 20:20:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762978806; cv=none; b=B1qQeXkCGF+ABUhhZnLwY+0CWC0M3DP1S81IxUca3hJFMbj7oZYh011TWCCkr5Q/tIy0sqIDkqWPkdSuf+xzaQV7vW6wg6FVbnXcCfUaMqxcwoCq+pGsg59595hnFNFfFuXgnGPR/J0k7vnE+Q3fWWhKKBqi8n+Q83zvdU2TYWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762978806; c=relaxed/simple; bh=/plj9fh/IZTy6oZAC8Dfhmcc4NUzFHy253uswukPQ7Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dVaAW4l2Jt1RA3sFaQsqc5dmXuXXuWslWASFDRTub3w0oSJSQMyUnOuke+qD+OcjqztgyOrPKfhs3w+CCzywnKlH6Y8wetwT68I4n8Lrt9J/1u3D3mNv548D7/QtvXm2/ZnYgXkRYKuy+oP04SF04U+XfApQA+FJAJqDPGwNayY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kspnNGkv; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kspnNGkv" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-29568d93e87so228645ad.2 for ; Wed, 12 Nov 2025 12:20:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762978804; x=1763583604; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I/vBXqyh3UPyAQ3zsAxz2ig4U3J84dfQKbNA3jaUdzo=; b=kspnNGkvldDFU3englaHpott0zd5VPTj0s3hWJTLiLDhemBvyJPerksTmCMwBwjbKG 019SusppVMeq1Xh3ndVvsOtTaPsS/eYggoRrueYikBPcjjfOaJTv+pNX0wu31zNa6WyT O53J/Ds676Nsdm1N7bfoSOaFMEbCu6P7bqVo6ppNKqjYGpH65bC58M+BJZSEtTlZigSH KOg7RgLtEAfhTmUujMqOstB0+UmTZouZUi1NtGWsCpbUnaaFOoiZEqUq7Cs5oLYu/mo4 w20a9v7SvRa6yU9Hse4rgBfYtRtQgbLm6SQFa54l0l/9BSUZmJuvkptD5v0aoc+FUe8Y JWXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762978804; x=1763583604; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=I/vBXqyh3UPyAQ3zsAxz2ig4U3J84dfQKbNA3jaUdzo=; b=Lsx7gEFYql4DrwJ0tsMoMPBdAqOpjoglkHS+6leBEDXBN1r8oPQhChEMUKWuL3ZnHn 5gtDDCd78cNU198GXgNxNZO0uriSvxjBGCoRLrdcgW53qWjNwLYLKGyn2xrdHdgaj9N0 CqWMm7S3Pj9i4tgyds9PqhzuZpFui7ClcZ9T7VVAnnD+ddWr8KTcYHOOGQFgy1Rlp7gc lB7hAYgqi25oooZOqQDeH1cEqaECUvTQUloSSfR4DkCkX8dqC6X2+r7GmPrgIYKP3lLN 7EXAVCWIj5bBUm9vMeQ0JwFPf4JGeSipJyo5XRCJloOqtRuxNynda3RpE+V1mq1dcd5D rLCg== X-Forwarded-Encrypted: i=1; AJvYcCVxLdEPjf13WtYi2Giy5Qavk7sJKo2V1jb0cceOx63aemGEnqpcbtyDbEi2vEKF1LfRonmTA20DvydILp0=@vger.kernel.org X-Gm-Message-State: AOJu0YwmOCDHYcPsvys7wpXLVC9GZVg4yAAyUGDdr07GoNGOeKoS/Bqn Zex4vpZ4f2nAfDuGL/6AQIPmxLuLzYfreD7XpClKJPfPvk5tHXrwy8J6 X-Gm-Gg: ASbGncv3/JblQSItWohP8PFVwWt+FN2oeKvliuCorhnvc4qG9pkvMsntNTvoiut7Bsd YTezyPGUmwj8R8omq/smu2I1CUPSGKuOkudpU4nEMm8+m4LLVoe6W1GNM1ddv5d8pY4dir6Hn89 e3Y1aSUF0wjRDAuQa2ouLsinVWlfKyNYQgidFv9ZcpZOB+9VbTt9/0SfR7Z1ICDZ6NICiGJWKnL 0wFC3/lAfqdFg5IRwTqDd/HPmVdMkQ/E9wlAjn3g8hf8M3YAmHhDyA2DeDAsP3W91RjZtAZ82Ae hfn0VUkEUtKSRT8FVPk+cqc69tlaXi3569t3xWaazinxLRWDyN8m4+jcsGJmmInE9LNBjb6jkD4 WQqp2dBhL490Tb03ej8ETN8Lv2T7mnSl1ONoiTLozrprc1mif9YHzvV3T8iHPwuFXMf/KMJgfrI Nufzarq7LfnLhjd5IoUlcvWQ== X-Google-Smtp-Source: AGHT+IHD3owK8YXgdkefa4KWcxQZCFPmAJLbR/Dh5Q2mfLUiYfFz0jmPuayumGBai8cChDj7akOlAw== X-Received: by 2002:a17:903:244a:b0:295:54cb:a8df with SMTP id d9443c01a7336-2984edec25cmr53252665ad.36.1762978804106; Wed, 12 Nov 2025 12:20:04 -0800 (PST) Received: from iku.. ([2401:4900:1c07:5748:721b:a500:103e:1bad]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c2377e0sm261015ad.23.2025.11.12.12.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Nov 2025 12:20:03 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property Date: Wed, 12 Nov 2025 20:19:36 +0000 Message-ID: <20251112201937.1336854-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251112201937.1336854-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251112201937.1336854-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1 MIIC binding schema. This property allows configuring the active level of the PHY-link signals used by the Switch, EtherCAT, and SERCOS III interfaces. The signal polarity is controlled by fields in the MIIC_PHYLINK register: - SWLNK[3:0]: configures the Switch interface link signal level 0 - Active High 1 - Active Low - CATLNK[6:4]: configures the EtherCAT interface link signal level 0 - Active Low 1 - Active High - S3LNK[9:8]: configures the SERCOS III interface link signal level 0 - Active Low 1 - Active High When the `renesas,miic-phylink-active-low` property is present, the PHY-link signal is configured as active-low. When omitted, the signal defaults to active-high. Signed-off-by: Lad Prabhakar --- .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.ya= ml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 3adbcf56d2be..825ae8a91e8b 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -86,6 +86,13 @@ patternProperties: and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/= N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 =20 + renesas,miic-phylink-active-low: + type: boolean + description: Indicates that the PHY-link signal provided by the Et= hernet switch, + EtherCAT, or SERCOS3 interface is active low. When present, this= property + sets the corresponding signal polarity to active low. When omitt= ed, the signal + defaults to active high. + required: - reg - renesas,miic-input --=20 2.43.0 From nobody Mon Feb 9 13:17:21 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E55FE28313D for ; Wed, 12 Nov 2025 20:20:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762978815; cv=none; b=Frfkmw6nDOdCkF7rwE0RXGAabTWAKzkzVxSsJg5v6fymWYimo4pIEMK4AfR0PDFR4kJMmD4hOQs9eKnu8Cod+lQB7yHTSUkfd5Sjh1PLlFqMOcxwu9sz9ksTxcD8o8qXlgiQmidVff6VgIl0mVwSVH3wWGYuhzIZW0v2XVnBPbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762978815; c=relaxed/simple; bh=FyeNLHzx9wEN/qXKtjmM5rgKnxBy7kQtIf7OGGTpnZ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KNRJ3pS0Frxs4oq7Xe7Cd0RLW4M7zZL+p1C+dJvrCQ/LI6a+nmKignQLuiNw6KvNPpiwcoRYC9kIQLZpEF4/QzSFDv3ZZpf9rGdbWKO3bE9SNVfRla0LcnG1xKmXx9X9Kb5fTPdVi4V6M8CVt4GKCrfoa/VqM0fIwvAqFPxETuE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NL1G+iXM; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NL1G+iXM" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-2958db8ae4fso272285ad.2 for ; Wed, 12 Nov 2025 12:20:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762978813; x=1763583613; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mdhW6tk5d4e4tP2yeRNaTsh6HeUSuYd0/9wpH/jkddA=; b=NL1G+iXMw8XH9QrGdPtugZCuB86/Fy7BuH/6WDDeJOMaNxyIyvgXqME1E5RH8v0yZx tkP34H69aX0PaCvr90rg++1x/TPU0PY6pzt/PQ78nBDqkunURPaRz5R0RRs7Co7eUQv3 vk4UARshpoKm27fCQKZ8okzTC5nDnHIY3SNck++s6o22dvxCcDKs+ZDr0OmVgrcgvzhd eqmev7nLFiDYMZxaFbK24wGG7oRf+ey3KxISZyP2+M9wChuzOeEwANjFjvkrFb9q7/2+ h8+8Y/voOtyGslXCRd7HxpcfDmzdv1fJ4VP6AAHtXb5CyfZ1PXwvqWM1IVjQdxoSJ0Ax aeFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762978813; x=1763583613; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=mdhW6tk5d4e4tP2yeRNaTsh6HeUSuYd0/9wpH/jkddA=; b=bzuuWNbT2qbqqADqLQ74xOwhgcHD5+ocD+RoBO7sdTUv8u1gKBaTfkb4XUP00M5i/U B0bzHEQQwnr1u3YRYkRicujFY/+Y8BbE8en4rgCiDik/UWMiqG9AuRVMpeJyeNN1lQxg n61vlUBfPdwcDf/reUtxuz9BQxDXulrKRwD5NXYOO3oizIIv/Ok0kHyt/mmV4m8SpZxj 0aHjbWwJbJAEefL3MmayksY023zRJjGUOcEIFpF+qBc7wDpjngKS8aL9SotTl9wcLABv PW8ccP+Z/8YtVimSUtZYW4idlJ8FJSWVsVJLBHWcMc8WljSTutCqNyUFs4pXTUN6y/gX 2nlg== X-Forwarded-Encrypted: i=1; AJvYcCWKlX9oCMKfRXcWLKLYHTnZ18KJLHOD9AO9H6eVAI+M97jDvBRIkUygcxa/nZfr6A2v5GKoAeXRi2MVEyM=@vger.kernel.org X-Gm-Message-State: AOJu0YxsQW2t2A6NnJO08iI8qwK/pINEwyXxhocNAOLBqKL2Tpy/DpN0 iP02qXBz/o4hYUMPu6+dAnMOrk+qs05lEFU6ZpN+klGPPu+w8X53kx5x X-Gm-Gg: ASbGncsJuxqKrbqu8PabHJn7b0XIUIzskSE3LMbUBLnh9XagdZUyZd7kqkLrSjahbjo no/fUBB22rHX/lUrzyrQfNpbi2w1y577+vCpqIQAFxXYShDqgyNL24DKt6F4XKG3NlPnvqVzpVN CM7LN0XgZlGxj15i71OzWTW8bot2srBuxJmHxu9vP8NpwYrrNk6aDx5600PZZ6wZXPR5oC73USK BRPG/lZgb2wTDidgspUuTelmhvKd0pwMNauR1fChC9Fl2ValIDgrtMvh4O86JJwUmjpUiSrmxan 3zduqpcakWqm0AOYxUUQIdXQYFcBKfddiUrrAM6FwTbpy4VPwFCJGj3+fDXh5gHo2mTKp5OVGiq ydjY259MmcNBVdQB0rlgabtYjgIfsXHOYRIcuDkr+DDR/Se9T18z5CU+s3BxXwvm8cRNKVPbL3V WmEVIKSIudt3xzbDxXPA1FvQ== X-Google-Smtp-Source: AGHT+IGuZmaA8bZsrtSJ31Pxg9MAJXLF6MUuXUKDHpV8hW9nvrdGY7K9Hzkg2UNWKBb1fiHttuFL/Q== X-Received: by 2002:a17:903:3d07:b0:298:8a9:766a with SMTP id d9443c01a7336-2984eddeab4mr49609515ad.53.1762978813003; Wed, 12 Nov 2025 12:20:13 -0800 (PST) Received: from iku.. ([2401:4900:1c07:5748:721b:a500:103e:1bad]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c2377e0sm261015ad.23.2025.11.12.12.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Nov 2025 12:20:12 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration Date: Wed, 12 Nov 2025 20:19:37 +0000 Message-ID: <20251112201937.1336854-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251112201937.1336854-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251112201937.1336854-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support to configure the PHY link signal active level per converter using the DT property "renesas,miic-phylink-active-low". Introduce the MIIC_PHYLINK register definition and extend the MIIC driver with a new `phylink` structure to store the mask and value for PHY link configuration. Implement `miic_configure_phylink()` to determine the bit position and polarity for each port based on the SoC type, such as RZ/N1 or RZ/T2H/N2H. The accumulated configuration is stored during Device Tree parsing and applied later in `miic_probe()` after hardware initialization, since the MIIC registers can only be modified safely once the hardware setup is complete. Signed-off-by: Lad Prabhakar --- drivers/net/pcs/pcs-rzn1-miic.c | 108 +++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 885f17c32643..333467cf91a7 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -28,6 +28,8 @@ =20 #define MIIC_MODCTRL 0x8 =20 +#define MIIC_PHYLINK 0x14 + #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) =20 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) @@ -177,6 +179,16 @@ static const char * const rzt2h_reset_ids[] =3D { "crst", }; =20 +/** + * struct phylink - Phylink configuration + * @mask: Mask of phylink bits + * @val: Value of phylink bits + */ +struct phylink { + u32 mask; + u32 val; +}; + /** * struct miic - MII converter structure * @base: base address of the MII converter @@ -184,6 +196,7 @@ static const char * const rzt2h_reset_ids[] =3D { * @lock: Lock used for read-modify-write access * @rsts: Reset controls for the MII converter * @of_data: Pointer to OF data + * @phylink: Phylink configuration */ struct miic { void __iomem *base; @@ -191,6 +204,12 @@ struct miic { spinlock_t lock; struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; const struct miic_of_data *of_data; + struct phylink phylink; +}; + +enum miic_type { + MIIC_TYPE_RZN1, + MIIC_TYPE_RZT2H, }; =20 /** @@ -210,6 +229,7 @@ struct miic { * @init_unlock_lock_regs: Flag to indicate if registers need to be unlock= ed * before access. * @miic_write: Function pointer to write a value to a MIIC register + * @type: Type of MIIC */ struct miic_of_data { struct modctrl_match *match_table; @@ -226,6 +246,7 @@ struct miic_of_data { u8 reset_count; bool init_unlock_lock_regs; void (*miic_write)(struct miic *miic, int offset, u32 value); + enum miic_type type; }; =20 /** @@ -581,10 +602,82 @@ static int miic_match_dt_conf(struct miic *miic, s8 *= dt_val, u32 *mode_cfg) return -EINVAL; } =20 +static void miic_configure_phylink(struct miic *miic, u32 conf, + u32 port, bool active_low) +{ + bool polarity_active_high; + u32 mask, val; + int shift; + + /* determine shift and polarity for this conf */ + if (miic->of_data->type =3D=3D MIIC_TYPE_RZN1) { + switch (conf) { + /* switch ports =3D> bits [3:0] (shift 0), active when low */ + case MIIC_SWITCH_PORTA: + case MIIC_SWITCH_PORTB: + case MIIC_SWITCH_PORTC: + case MIIC_SWITCH_PORTD: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* EtherCAT ports =3D> bits [7:4] (shift 4), active when high */ + case MIIC_ETHERCAT_PORTA: + case MIIC_ETHERCAT_PORTB: + case MIIC_ETHERCAT_PORTC: + shift =3D 4; + polarity_active_high =3D true; + break; + + /* Sercos ports =3D> bits [11:8] (shift 8), active when high */ + case MIIC_SERCOS_PORTA: + case MIIC_SERCOS_PORTB: + shift =3D 8; + polarity_active_high =3D true; + break; + + default: + return; + } + } else { + switch (conf) { + /* ETHSW ports =3D> bits [3:0] (shift 0), active when low */ + case ETHSS_ETHSW_PORT0: + case ETHSS_ETHSW_PORT1: + case ETHSS_ETHSW_PORT2: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* ESC ports =3D> bits [7:4] (shift 4), active when high */ + case ETHSS_ESC_PORT0: + case ETHSS_ESC_PORT1: + case ETHSS_ESC_PORT2: + shift =3D 4; + polarity_active_high =3D true; + break; + + default: + return; + } + } + + mask =3D BIT(port) << shift; + + if (polarity_active_high) + val =3D (active_low ? 0 : BIT(port)) << shift; + else + val =3D (active_low ? BIT(port) : 0) << shift; + + miic->phylink.mask |=3D mask; + miic->phylink.val =3D (miic->phylink.val & ~mask) | (val & mask); +} + static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) { struct device_node *np =3D miic->dev->of_node; struct device_node *conv; + bool active_low; int port, ret; s8 *dt_val; u32 conf; @@ -605,8 +698,15 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_= cfg) =20 /* Adjust for 0 based index */ port +=3D !miic->of_data->miic_port_start; - if (of_property_read_u32(conv, "renesas,miic-input", &conf) =3D=3D 0) - dt_val[port] =3D conf; + if (of_property_read_u32(conv, "renesas,miic-input", &conf)) + continue; + + dt_val[port] =3D conf; + + active_low =3D of_property_read_bool(conv, "renesas,miic-phylink-active-= low"); + + miic_configure_phylink(miic, conf, port - !miic->of_data->miic_port_star= t, + active_low); } =20 ret =3D miic_match_dt_conf(miic, dt_val, mode_cfg); @@ -696,6 +796,8 @@ static int miic_probe(struct platform_device *pdev) if (ret) goto disable_runtime_pm; =20 + miic_reg_rmw(miic, MIIC_PHYLINK, miic->phylink.mask, miic->phylink.val); + /* miic_create() relies on that fact that data are attached to the * platform device to determine if the driver is ready so this needs to * be the last thing to be done after everything is initialized @@ -729,6 +831,7 @@ static struct miic_of_data rzn1_miic_of_data =3D { .sw_mode_mask =3D GENMASK(4, 0), .init_unlock_lock_regs =3D true, .miic_write =3D miic_reg_writel_unlocked, + .type =3D MIIC_TYPE_RZN1, }; =20 static struct miic_of_data rzt2h_miic_of_data =3D { @@ -745,6 +848,7 @@ static struct miic_of_data rzt2h_miic_of_data =3D { .reset_ids =3D rzt2h_reset_ids, .reset_count =3D ARRAY_SIZE(rzt2h_reset_ids), .miic_write =3D miic_reg_writel_locked, + .type =3D MIIC_TYPE_RZT2H, }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.43.0