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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 18:26:39.7370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c5bafc5-3767-4fc8-9085-08de221905ae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7127 Content-Type: text/plain; charset="utf-8" Introduce the amd_iommu_set_dte_v1() helper function to configure IOMMU host (v1) page table into DTE. Suggested-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jason Gunthorpe --- drivers/iommu/amd/amd_iommu.h | 5 ++ drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/iommu.c | 94 ++++++++++++++++------------- 3 files changed, 59 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index ebedb49c28cf..df167ae9e4aa 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -187,6 +187,11 @@ void amd_iommu_domain_set_pgtable(struct protection_do= main *domain, struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid); =20 +void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_data, + struct protection_domain *domain, + u16 domid, struct pt_iommu_amdv1_hw_info *pt_info, + struct dev_table_entry *new); + void amd_iommu_update_dte(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, struct dev_table_entry *new); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 734f6a753b3a..19a98c6490cb 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -352,6 +352,7 @@ #define DTE_FLAG_HAD (3ULL << 7) #define DTE_MODE_MASK GENMASK_ULL(11, 9) #define DTE_HOST_TRP GENMASK_ULL(51, 12) +#define DTE_FLAG_PPR BIT_ULL(52) #define DTE_FLAG_GIOV BIT_ULL(54) #define DTE_FLAG_GV BIT_ULL(55) #define DTE_GLX GENMASK_ULL(57, 56) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 24bab275e8c0..d392b6757f2a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2030,36 +2030,56 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev= _data, ioasid_t pasid) * Note: * The old value for GCR3 table and GPT have been cleared from caller. */ -static void set_dte_gcr3_table(struct amd_iommu *iommu, - struct iommu_dev_data *dev_data, - struct dev_table_entry *target) +static void set_dte_gcr3_table(struct iommu_dev_data *dev_data, + struct dev_table_entry *new) { struct gcr3_tbl_info *gcr3_info =3D &dev_data->gcr3_info; - u64 gcr3; + u64 gcr3 =3D iommu_virt_to_phys(gcr3_info->gcr3_tbl); =20 - if (!gcr3_info->gcr3_tbl) - return; - - pr_debug("%s: devid=3D%#x, glx=3D%#x, gcr3_tbl=3D%#llx\n", - __func__, dev_data->devid, gcr3_info->glx, - (unsigned long long)gcr3_info->gcr3_tbl); - - gcr3 =3D iommu_virt_to_phys(gcr3_info->gcr3_tbl); + new->data[0] |=3D DTE_FLAG_TV | + (dev_data->ppr ? DTE_FLAG_PPR : 0) | + (pdom_is_v2_pgtbl_mode(dev_data->domain) ? DTE_FLAG_GIOV : 0) | + DTE_FLAG_GV | + FIELD_PREP(DTE_GLX, gcr3_info->glx) | + FIELD_PREP(DTE_GCR3_14_12, gcr3 >> 12) | + DTE_FLAG_IR | DTE_FLAG_IW; =20 - target->data[0] |=3D DTE_FLAG_GV | - FIELD_PREP(DTE_GLX, gcr3_info->glx) | - FIELD_PREP(DTE_GCR3_14_12, gcr3 >> 12); - if (pdom_is_v2_pgtbl_mode(dev_data->domain)) - target->data[0] |=3D DTE_FLAG_GIOV; - - target->data[1] |=3D FIELD_PREP(DTE_GCR3_30_15, gcr3 >> 15) | - FIELD_PREP(DTE_GCR3_51_31, gcr3 >> 31); + new->data[1] |=3D FIELD_PREP(DTE_DOMID_MASK, dev_data->gcr3_info.domid) | + FIELD_PREP(DTE_GCR3_30_15, gcr3 >> 15) | + (dev_data->ats_enabled ? DTE_FLAG_IOTLB : 0) | + FIELD_PREP(DTE_GCR3_51_31, gcr3 >> 31); =20 /* Guest page table can only support 4 and 5 levels */ if (amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) - target->data[2] |=3D FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_5_LEVE= L); + new->data[2] |=3D FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_5_LEVEL); else - target->data[2] |=3D FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_4_LEVE= L); + new->data[2] |=3D FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_4_LEVEL); +} + +void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_data, + struct protection_domain *domain, + u16 domid, struct pt_iommu_amdv1_hw_info *pt_info, + struct dev_table_entry *new) +{ + /* Note Dirty tracking is used for v1 table only for now */ + new->data[0] |=3D DTE_FLAG_TV | + FIELD_PREP(DTE_MODE_MASK, pt_info->mode) | + (domain->dirty_tracking ? DTE_FLAG_HAD : 0) | + FIELD_PREP(DTE_HOST_TRP, pt_info->host_pt_root >> 12) | + DTE_FLAG_IR | DTE_FLAG_IW; + + new->data[1] |=3D FIELD_PREP(DTE_DOMID_MASK, domid) | + (dev_data->ats_enabled ? DTE_FLAG_IOTLB : 0); +} + +static void set_dte_passthrough(struct iommu_dev_data *dev_data, + struct protection_domain *domain, + struct dev_table_entry *new) +{ + new->data[0] |=3D DTE_FLAG_TV | DTE_FLAG_IR | DTE_FLAG_IW; + + new->data[1] |=3D FIELD_PREP(DTE_DOMID_MASK, domain->id) | + (dev_data->ats_enabled) ? DTE_FLAG_IOTLB : 0; } =20 static void set_dte_entry(struct amd_iommu *iommu, @@ -2074,8 +2094,6 @@ static void set_dte_entry(struct amd_iommu *iommu, struct dev_table_entry *dte =3D &get_dev_table(iommu)[dev_data->devid]; struct pt_iommu_amdv1_hw_info pt_info; =20 - amd_iommu_make_clear_dte(dev_data, &new); - if (gcr3_info && gcr3_info->gcr3_tbl) domid =3D dev_data->gcr3_info.domid; else { @@ -2097,35 +2115,29 @@ static void set_dte_entry(struct amd_iommu *iommu, &pt_info); } =20 - new.data[0] |=3D __sme_set(pt_info.host_pt_root) | - (pt_info.mode & DEV_ENTRY_MODE_MASK) - << DEV_ENTRY_MODE_SHIFT; + pt_info.host_pt_root =3D __sme_set(pt_info.host_pt_root); } } =20 - new.data[0] |=3D DTE_FLAG_IR | DTE_FLAG_IW; - /* * When SNP is enabled, we can only support TV=3D1 with non-zero domain I= D. * This is prevented by the SNP-enable and IOMMU_DOMAIN_IDENTITY check in * do_iommu_domain_alloc(). */ WARN_ON(amd_iommu_snp_en && (domid =3D=3D 0)); - new.data[0] |=3D DTE_FLAG_TV; - - if (dev_data->ppr) - new.data[0] |=3D 1ULL << DEV_ENTRY_PPR; - - if (domain->dirty_tracking) - new.data[0] |=3D DTE_FLAG_HAD; =20 - if (dev_data->ats_enabled) - new.data[1] |=3D DTE_FLAG_IOTLB; + amd_iommu_make_clear_dte(dev_data, &new); =20 old_domid =3D READ_ONCE(dte->data[1]) & DTE_DOMID_MASK; - new.data[1] |=3D domid; - - set_dte_gcr3_table(iommu, dev_data, &new); + if (gcr3_info && gcr3_info->gcr3_tbl) + set_dte_gcr3_table(dev_data, &new); + else if (domain->domain.type =3D=3D IOMMU_DOMAIN_IDENTITY) + set_dte_passthrough(dev_data, domain, &new); + else if (domain->domain.type & __IOMMU_DOMAIN_PAGING && + domain->pd_mode =3D=3D PD_MODE_V1) + amd_iommu_set_dte_v1(dev_data, domain, domid, &pt_info, &new); + else + WARN_ON(true); =20 amd_iommu_update_dte(iommu, dev_data, &new); =20 --=20 2.34.1