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Wed, 12 Nov 2025 07:09:55 -0800 (PST) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42abe62bf40sm33272447f8f.9.2025.11.12.07.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Nov 2025 07:09:54 -0800 (PST) From: Tomer Maimon To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com, andrew@codeconstruct.com.au Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH v2] spi: dt-bindings: nuvoton,npcm-pspi: Convert to DT schema Date: Wed, 12 Nov 2025 17:09:50 +0200 Message-Id: <20251112150950.1680154-1-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Nuvoton NPCM PSPI binding to DT schema format. Also update the binding to fix shortcoming: * Drop clock-frequency property: it is never read in the NPCM PSPI driver and has no effect. Signed-off-by: Tomer Maimon Reviewed-by: Krzysztof Kozlowski --- Addressed comments from: - Krzysztof Kozlowski: https://patchwork.ozlabs.org/project/openbmc/patch/= 20251110081457.1008316-1-tmaimon77@gmail.com/ Changes since version 1: - Fix commit subject and message. - Drop unnecessary description. - Use GPIO defines. - Add clock-names property. .../bindings/spi/nuvoton,npcm-pspi.txt | 36 ---------- .../bindings/spi/nuvoton,npcm-pspi.yaml | 72 +++++++++++++++++++ 2 files changed, 72 insertions(+), 36 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi= .txt create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi= .yaml diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/= Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt deleted file mode 100644 index a4e72e52af59..000000000000 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt +++ /dev/null @@ -1,36 +0,0 @@ -Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver - -Nuvoton NPCM7xx SOC support two PSPI channels. - -Required properties: - - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX. - "nuvoton,npcm845-pspi" for Arbel NPCM8XX. - - #address-cells : should be 1. see spi-bus.txt - - #size-cells : should be 0. see spi-bus.txt - - specifies physical base address and size of the register. - - interrupts : contain PSPI interrupt. - - clocks : phandle of PSPI reference clock. - - clock-names: Should be "clk_apb5". - - pinctrl-names : a pinctrl state named "default" must be defined. - - pinctrl-0 : phandle referencing pin configuration of the device. - - resets : phandle to the reset control for this device. - - cs-gpios: Specifies the gpio pins to be used for chipselects. - See: Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -- clock-frequency : Input clock frequency to the PSPI block in Hz. - Default is 25000000 Hz. - -spi0: spi@f0200000 { - compatible =3D "nuvoton,npcm750-pspi"; - reg =3D <0xf0200000 0x1000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pspi1_pins>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - clocks =3D <&clk NPCM7XX_CLK_APB5>; - clock-names =3D "clk_apb5"; - resets =3D <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1> - cs-gpios =3D <&gpio6 11 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.yaml b= /Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.yaml new file mode 100644 index 000000000000..db0fb872020a --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,npcm-pspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Peripheral SPI (PSPI) Controller + +maintainers: + - Tomer Maimon + +allOf: + - $ref: spi-controller.yaml# + +description: + Nuvoton NPCM Peripheral Serial Peripheral Interface (PSPI) controller. + Nuvoton NPCM7xx SOC supports two PSPI channels. + Nuvoton NPCM8xx SOC support one PSPI channel. + +properties: + compatible: + enum: + - nuvoton,npcm750-pspi # Poleg NPCM7XX + - nuvoton,npcm845-pspi # Arbel NPCM8XX + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: PSPI reference clock. + + clock-names: + items: + - const: clk_apb5 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include "dt-bindings/gpio/gpio.h" + spi0: spi@f0200000 { + compatible =3D "nuvoton,npcm750-pspi"; + reg =3D <0xf0200000 0x1000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pspi1_pins>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&clk NPCM7XX_CLK_APB5>; + clock-names =3D "clk_apb5"; + resets =3D <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + cs-gpios =3D <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + --=20 2.34.1