From nobody Sun Feb 8 07:07:09 2026 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48126335078 for ; Wed, 12 Nov 2025 12:33:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762950823; cv=none; b=jADsT21d/3aS2AduE1uR1GWEoHxI/m+TW+VTLIO9lGMvBbu0xX4rGc3pFp3sFa7nXIkRRyzY3ExYWajTiexrIoxX6U5lBxgYR8ckjlXd/3n9uFi5HnOJkWb21kesBDPA9Lm8lJngPsoyZtoN0IGP1aTGfZHI0RPoHi4C5d3Onyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762950823; c=relaxed/simple; bh=d9cHU13fFbCVRuXvMiXwPmUVkpMZfy3GZGlcMRZ6zyM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Jkv+1rfmTsVsCPxb2m3PZgnMTVXyPSSPfxTOowmmDl9ZfEnwtotmuu6HAsSetwiDduyD8r51zHc5zCgZ+cmMweNIzt7oufbRi/sXF/7uaEAPOMesHxIeYakJOjC5WAra5JZndb1LjoiTXlM7FMCGr9c92VoCZ5rbD34qwydoB4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=vI2Iau4l; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="vI2Iau4l" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-bb1875e1416so694788a12.0 for ; Wed, 12 Nov 2025 04:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1762950819; x=1763555619; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=DL8GJ0K0iNwYW+A1OoM+d4qx21RJUKEPvPuxNBd2KIY=; b=vI2Iau4lgxZ6XGBrCi6YefUIbqfmEHW5hJl1TCrzr5Zsm1YBkG3MzIfaOjVEpXg34S ISiXUMhoB/1328PEMxRu2TStIRwpiXDK4s8eDuA9CMPLa37vbkNNnMqXvG6G180AqYMI 9g4/dDjxrNNaiheYgck9upBL8VZbEHV7GFISSn3Zlb69c70a3vMLn3GOBWCifV04TAZ4 VSVA+GRs/8/mqMzq0uR5VgRZipj7Ap7SluZ5Jqxz5fcS3eK5lVMrVp6hPf6UdoAZRo7m iGOdbr86y0PrcegfPNxtNiy3bRWBUyg1sT53h4Pq/Qzw6s3qInYeCXJNzdz8sfVad4Ok g8fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762950819; x=1763555619; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DL8GJ0K0iNwYW+A1OoM+d4qx21RJUKEPvPuxNBd2KIY=; b=Q3HCfUEXHBmKQLLo8F9IgGJ5xQa+BrMytrYFTTabkOMIEd/aUCox9bwT/dEMQ5ufez ZaQGzSvOhQZJfcaJ3jUtFkPS9zS6CMa7TDR4sEvnKg/9uoM3FX2J/hI0wiNE8GOCCMMg o+KgxZfghMrQHGzgNufKfqLWbE0ie+KjOeuI9Jdq8oRsIh5IZcd02wc3Wuu86g79PGzb OzG4MXPmKe74c5HTbE5CfIZynvQRDAgb6u9pOvcXaOCA2+SDDgqulIwg/d+1QR+U+dm3 sQXXVQlRXah01sKyT6xmcFsj1/+qtkBrekgg/i4B+hEpKkmquVIMMuxwZLWzVkBpVZk5 FiRQ== X-Forwarded-Encrypted: i=1; AJvYcCVaf3IQ4q+gEe5TUOnpqcYshE1zg2bbN+v+27/hAGrFaS/UZXF3Si+ZcxzET96l1JPo6yoLAznOc48EJ9c=@vger.kernel.org X-Gm-Message-State: AOJu0YxoVDV53WUICX1UGTZD6PiwJ2108RZNuBlwx//3AvLB/46Tieqo J5xVb5n+l9GhdVWKxSPcxZG2n4j2zL86AXei1ZUpFqHeAYDOGaHZUEJJV/2AWmNp0+lEzRpuz5/ +8uQO9Q== X-Google-Smtp-Source: AGHT+IHW6MkJJN6CNX2hfnUNdBNBx+IM3THZOwO6ahE5BTDHOZbstitebr0A6VvJc7/SjssqfaCawsE5+Tw= X-Received: from dlaj13.prod.google.com ([2002:a05:701b:280d:b0:119:b185:ea6a]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:19c8:b0:295:613f:3d6a with SMTP id d9443c01a7336-2984edacc5fmr40942345ad.29.1762950819047; Wed, 12 Nov 2025 04:33:39 -0800 (PST) Date: Wed, 12 Nov 2025 12:32:56 +0000 In-Reply-To: <20251112123257.3755489-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251112123257.3755489-1-royluo@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251112123257.3755489-2-royluo@google.com> Subject: [PATCH v6 1/2] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 From: Roy Luo To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , Doug Anderson , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the DWC3 USB controller found in Google Tensor SoCs, starting with the G5 generation (codename: laguna). The Tensor G5 silicon represents a complete architectural departure from previous generations (like gs101), including entirely new clock/reset schemes, top-level wrapper and register interface. Consequently, existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating this new device tree binding. The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features Dual-Role Device single port with hibernation support. Signed-off-by: Roy Luo Reviewed-by: Krzysztof Kozlowski --- .../bindings/usb/google,lga-dwc3.yaml | 140 ++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/google,lga-dwc3.y= aml diff --git a/Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml b/D= ocumentation/devicetree/bindings/usb/google,lga-dwc3.yaml new file mode 100644 index 000000000000..95be84c843f5 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/google,lga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series G5 (Laguna) DWC3 USB SoC Controller + +maintainers: + - Roy Luo + +description: + Describes the DWC3 USB controller block implemented on Google Tensor SoC= s, + starting with the G5 generation (laguna). Based on Synopsys DWC3 IP, the + controller features Dual-Role Device single port with hibernation add-on. + +properties: + compatible: + const: google,lga-dwc3 + + reg: + items: + - description: Core DWC3 IP registers. + + interrupts: + items: + - description: Core DWC3 interrupt. + - description: High speed power management event for remote wakeup. + - description: Super speed power management event for remote wakeup. + + interrupt-names: + items: + - const: core + - const: hs_pme + - const: ss_pme + + clocks: + items: + - description: Non-sticky module clock. + - description: Sticky module clock. + + clock-names: + items: + - const: non_sticky + - const: sticky + + resets: + items: + - description: Non-sticky module reset. + - description: Sticky module reset. + - description: DRD bus reset. + - description: Top-level reset. + + reset-names: + items: + - const: non_sticky + - const: sticky + - const: drd_bus + - const: top + + power-domains: + items: + - description: Power switchable domain, the child of top domain. + Turning it on puts the controller into full power state, + turning it off puts the controller into power gated state. + - description: Top domain, the parent of power switchable domain. + Turning it on puts the controller into power gated state, + turning it off completely shuts off the controller. + + power-domain-names: + items: + - const: psw + - const: top + + iommus: + maxItems: 1 + + google,usb-cfg-csr: + description: + A phandle to a syscon node used to access the USB configuration + registers. These registers are the top-level wrapper of the USB + subsystem and provide control and status for the integrated USB + controller and USB PHY. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the syscon node. + - description: USB host controller configuration register offset. + - description: USB custom interrrupts control register offset. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - power-domain-names + - google,usb-cfg-csr + +allOf: + - $ref: snps,dwc3-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb@c400000 { + compatible =3D "google,lga-dwc3"; + reg =3D <0 0x0c400000 0 0xd060>; + interrupts =3D , + , + ; + interrupt-names =3D "core", "hs_pme", "ss_pme"; + clocks =3D <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_= clk>; + clock-names =3D "non_sticky", "sticky"; + resets =3D <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usb= c_sticky>, + <&hsion_resets_usb_drd_bus>, <&hsion_resets_usb_top>; + reset-names =3D "non_sticky", "sticky", "drd_bus", "top"; + power-domains =3D <&hsio_n_usb_psw>, <&hsio_n_usb>; + power-domain-names =3D "psw", "top"; + phys =3D <&usb_phy 0>; + phy-names =3D "usb2-phy"; + snps,quirk-frame-length-adjustment =3D <0x20>; + snps,gfladj-refclk-lpm-sel-quirk; + snps,incr-burst-type-adjustment =3D <4>; + google,usb-cfg-csr =3D <&usb_cfg_csr 0x0 0x20>; + }; + }; +... --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 07:07:09 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27B57335071 for ; Wed, 12 Nov 2025 12:33:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; 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Wed, 12 Nov 2025 04:33:41 -0800 (PST) Date: Wed, 12 Nov 2025 12:32:57 +0000 In-Reply-To: <20251112123257.3755489-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251112123257.3755489-1-royluo@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251112123257.3755489-3-royluo@google.com> Subject: [PATCH v6 2/2] usb: dwc3: Add Google Tensor SoC DWC3 glue driver From: Roy Luo To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , Doug Anderson , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the DWC3 USB controller found on Google Tensor G5 (codename: laguna). The controller features dual-role functionality and hibernation. The primary focus is implementing hibernation support in host mode, enabling the controller to enter a low-power state (D3). This is particularly relevant during system power state transition and runtime power management for power efficiency. Highlights: - Align suspend callback with dwc3_suspend_common() for deciding between a full teardown and hibernation in host mode. - Integration with `psw` (power switchable) and `top` power domains, managing their states and device links to support hibernation. - A notifier callback dwc3_google_usb_psw_pd_notifier() for `psw` power domain events to manage controller state transitions to/from D3. - Coordination of the `non_sticky` reset during power state transitions, asserting it on D3 entry and deasserting on D0 entry in hibernation scenario. - Handling of high-speed and super-speed PME interrupts that are generated by remote wakeup during hibernation. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo Acked-by: Thinh Nguyen --- drivers/usb/dwc3/Kconfig | 10 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-google.c | 628 +++++++++++++++++++++++++++++++++ 3 files changed, 639 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-google.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 4925d15084f8..bb0e4dc97da3 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -200,4 +200,14 @@ config USB_DWC3_GENERIC_PLAT the dwc3 child node in the device tree. Say 'Y' or 'M' here if your platform integrates DWC3 in a similar way. =20 +config USB_DWC3_GOOGLE + tristate "Google Platform" + depends on OF && COMMON_CLK && RESET_CONTROLLER + default n + help + Support the DesignWare Core USB3 IP found on Google Tensor + SoCs, starting with the G5 generation. This driver includes + support for hibernation in host mode. + Say 'Y' or 'M' if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 96469e48ff9d..cf1cd408d938 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -58,3 +58,4 @@ obj-$(CONFIG_USB_DWC3_XILINX) +=3D dwc3-xilinx.o obj-$(CONFIG_USB_DWC3_OCTEON) +=3D dwc3-octeon.o obj-$(CONFIG_USB_DWC3_RTK) +=3D dwc3-rtk.o obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) +=3D dwc3-generic-plat.o +obj-$(CONFIG_USB_DWC3_GOOGLE) +=3D dwc3-google.o diff --git a/drivers/usb/dwc3/dwc3-google.c b/drivers/usb/dwc3/dwc3-google.c new file mode 100644 index 000000000000..428adf7d6049 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-google.c @@ -0,0 +1,628 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwc3-google.c - Google DWC3 Specific Glue Layer + * + * Copyright (c) 2025, Google LLC + * Author: Roy Luo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "glue.h" + +/* HOST CFG registers */ +#define HC_STATUS_OFFSET 0x0 +#define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0) +#define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3) + +#define HOST_CFG1_OFFSET 0x4 +#define HOST_CFG1_PME_EN BIT(3) +#define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4) +#define HOST_CFG1_PM_POWER_STATE_D0 0x0 +#define HOST_CFG1_PM_POWER_STATE_D3 0x3 + +/* USBINT registers */ +#define USBINT_CFG1_OFFSET 0x0 +#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK BIT(2) +#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK BIT(3) +#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN BIT(8) +#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN BIT(9) +#define USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR BIT(14) +#define USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR BIT(15) + +#define USBINT_STATUS_OFFSET 0x4 +#define USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW BIT(2) +#define USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW BIT(3) + +#define USBCS_TOP_CTRL_CFG1_OFFSET 0xc +#define USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE BIT(5) + +#define DWC3_GOOGLE_MAX_RESETS 4 + +struct dwc3_google { + struct device *dev; + struct dwc3 dwc; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control_bulk_data rsts[DWC3_GOOGLE_MAX_RESETS]; + int num_rsts; + struct reset_control *non_sticky_rst; + struct device *usb_psw_pd; + struct device_link *usb_psw_pd_dl; + struct notifier_block usb_psw_pd_nb; + struct device *usb_top_pd; + struct device_link *usb_top_pd_dl; + struct regmap *usb_cfg_regmap; + unsigned int host_cfg_offset; + unsigned int usbint_cfg_offset; + int hs_pme_irq; + int ss_pme_irq; + bool is_usb2only; + bool is_hibernation; +}; + +#define to_dwc3_google(d) container_of((d), struct dwc3_google, dwc) + +static int dwc3_google_rst_init(struct dwc3_google *google) +{ + int ret; + + google->num_rsts =3D 4; + google->rsts[0].id =3D "non_sticky"; + google->rsts[1].id =3D "sticky"; + google->rsts[2].id =3D "drd_bus"; + google->rsts[3].id =3D "top"; + + ret =3D devm_reset_control_bulk_get_exclusive(google->dev, + google->num_rsts, + google->rsts); + + if (ret < 0) + return ret; + + google->non_sticky_rst =3D google->rsts[0].rstc; + + return 0; +} + +static int dwc3_google_set_pmu_state(struct dwc3_google *google, int state) +{ + u32 reg; + int ret; + + regmap_read(google->usb_cfg_regmap, + google->host_cfg_offset + HOST_CFG1_OFFSET, ®); + + reg &=3D ~HOST_CFG1_PM_POWER_STATE_REQUEST; + reg |=3D (FIELD_PREP(HOST_CFG1_PM_POWER_STATE_REQUEST, state) | + HOST_CFG1_PME_EN); + regmap_write(google->usb_cfg_regmap, + google->host_cfg_offset + HOST_CFG1_OFFSET, reg); + + ret =3D regmap_read_poll_timeout(google->usb_cfg_regmap, + google->host_cfg_offset + HC_STATUS_OFFSET, reg, + (FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U2PMU, + reg) =3D=3D state && + FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U3PMU, + reg) =3D=3D state), + 10, 10000); + + if (ret) + dev_err(google->dev, "failed to set PMU state %d\n", state); + + return ret; +} + +/* + * Clear pme interrupts and report their status. + * The hardware requires write-1 then write-0 sequence to clear the interr= upt bits. + */ +static u32 dwc3_google_clear_pme_irqs(struct dwc3_google *google) +{ + u32 irq_status, reg_set, reg_clear; + + regmap_read(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_STATUS_OFFSET, &irq_status); + + irq_status &=3D (USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW | + USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW); + if (!irq_status) + return irq_status; + + regmap_read(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®_set); + + reg_clear =3D reg_set; + if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW) { + reg_set |=3D USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; + reg_clear &=3D ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; + } + if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW) { + reg_set |=3D USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; + reg_clear &=3D ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; + } + + regmap_write(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_set); + regmap_write(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_clear); + + return irq_status; +} + +static void dwc3_google_enable_pme_irq(struct dwc3_google *google) +{ + u32 reg; + + regmap_read(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®); + reg &=3D ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); + reg |=3D (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); + regmap_write(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg); + + enable_irq(google->hs_pme_irq); + enable_irq(google->ss_pme_irq); + enable_irq_wake(google->hs_pme_irq); + enable_irq_wake(google->ss_pme_irq); +} + +static void dwc3_google_disable_pme_irq(struct dwc3_google *google) +{ + u32 reg; + + regmap_read(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®); + reg &=3D ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); + reg |=3D (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); + regmap_write(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg); + + disable_irq_wake(google->hs_pme_irq); + disable_irq_wake(google->ss_pme_irq); + disable_irq_nosync(google->hs_pme_irq); + disable_irq_nosync(google->ss_pme_irq); +} + +static irqreturn_t dwc3_google_resume_irq(int irq, void *data) +{ + struct dwc3_google *google =3D data; + struct dwc3 *dwc =3D &google->dwc; + u32 irq_status, dr_role; + + irq_status =3D dwc3_google_clear_pme_irqs(google); + dr_role =3D dwc->current_dr_role; + + if (!irq_status || !google->is_hibernation || + dr_role !=3D DWC3_GCTL_PRTCAP_HOST) { + dev_dbg(google->dev, "spurious pme irq %d, hibernation %d, dr_role %u\n", + irq, google->is_hibernation, dr_role); + return IRQ_HANDLED; + } + + if (dwc->xhci) + pm_runtime_resume(&dwc->xhci->dev); + + return IRQ_HANDLED; +} + +static int dwc3_google_request_irq(struct dwc3_google *google, struct plat= form_device *pdev, + const char *irq_name, const char *req_name) +{ + int ret; + int irq; + + irq =3D platform_get_irq_byname(pdev, irq_name); + if (irq < 0) { + dev_err(google->dev, "invalid irq name %s\n", irq_name); + return irq; + } + + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret =3D devm_request_threaded_irq(google->dev, irq, NULL, + dwc3_google_resume_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + req_name, google); + if (ret < 0) { + dev_err(google->dev, "failed to request irq %s\n", req_name); + return ret; + } + + return irq; +} + +static int dwc3_google_usb_psw_pd_notifier(struct notifier_block *nb, unsi= gned long action, void *d) +{ + struct dwc3_google *google =3D container_of(nb, struct dwc3_google, usb_p= sw_pd_nb); + int ret; + + if (!google->is_hibernation) + return NOTIFY_OK; + + if (action =3D=3D GENPD_NOTIFY_OFF) { + dev_dbg(google->dev, "enter D3 power state\n"); + dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D3); + ret =3D reset_control_assert(google->non_sticky_rst); + if (ret) + dev_err(google->dev, "non sticky reset assert failed: %d\n", ret); + } else if (action =3D=3D GENPD_NOTIFY_ON) { + dev_dbg(google->dev, "enter D0 power state\n"); + dwc3_google_clear_pme_irqs(google); + ret =3D reset_control_deassert(google->non_sticky_rst); + if (ret) + dev_err(google->dev, "non sticky reset deassert failed: %d\n", ret); + dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D0); + } + + return NOTIFY_OK; +} + +static void dwc3_google_pm_domain_deinit(struct dwc3_google *google) +{ + if (google->usb_top_pd_dl) + device_link_del(google->usb_top_pd_dl); + + if (!IS_ERR_OR_NULL(google->usb_top_pd)) { + device_set_wakeup_capable(google->usb_top_pd, false); + dev_pm_domain_detach(google->usb_top_pd, true); + } + + if (google->usb_psw_pd_dl) + device_link_del(google->usb_psw_pd_dl); + + if (!IS_ERR_OR_NULL(google->usb_psw_pd)) { + dev_pm_genpd_remove_notifier(google->usb_psw_pd); + dev_pm_domain_detach(google->usb_psw_pd, true); + } +} + +static int dwc3_google_pm_domain_init(struct dwc3_google *google) +{ + int ret; + + /* + * Establish PM RUNTIME link between dwc dev and its power domain usb_psw= _pd, + * register notifier block to handle hibernation. + */ + google->usb_psw_pd =3D dev_pm_domain_attach_by_name(google->dev, "psw"); + if (IS_ERR_OR_NULL(google->usb_psw_pd)) { + dev_err(google->dev, "failed to get psw pd"); + ret =3D google->usb_psw_pd ? PTR_ERR(google->usb_psw_pd) : -ENODATA; + return ret; + } + + google->usb_psw_pd_nb.notifier_call =3D dwc3_google_usb_psw_pd_notifier; + ret =3D dev_pm_genpd_add_notifier(google->usb_psw_pd, &google->usb_psw_pd= _nb); + if (ret) { + dev_err(google->dev, "failed to add psw pd notifier"); + goto err; + } + + google->usb_psw_pd_dl =3D device_link_add(google->dev, google->usb_psw_pd, + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (!google->usb_psw_pd_dl) { + dev_err(google->usb_psw_pd, "failed to add device link"); + ret =3D -ENODEV; + goto err; + } + + /* + * usb_top_pd is the parent power domain of usb_psw_pd. Keeping usb_top_p= d on + * while usb_psw_pd is off places the controller in a power-gated state, + * essential for hibernation. Acquire a handle to usb_top_pd and sets it = as + * wakeup-capable to allow the domain to be left on during system suspend. + */ + google->usb_top_pd =3D dev_pm_domain_attach_by_name(google->dev, "top"); + if (IS_ERR_OR_NULL(google->usb_top_pd)) { + dev_err(google->dev, "failed to get top pd"); + ret =3D google->usb_top_pd ? PTR_ERR(google->usb_top_pd) : -ENODATA; + goto err; + } + device_set_wakeup_capable(google->usb_top_pd, true); + + google->usb_top_pd_dl =3D device_link_add(google->dev, google->usb_top_pd, + DL_FLAG_STATELESS); + if (!google->usb_top_pd_dl) { + dev_err(google->usb_top_pd, "failed to add device link"); + ret =3D -ENODEV; + goto err; + } + + return 0; + +err: + dwc3_google_pm_domain_deinit(google); + + return ret; +} + +static void dwc3_google_program_usb2only(struct dwc3_google *google) +{ + u32 reg; + + regmap_read(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, ®); + reg |=3D USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE; + regmap_write(google->usb_cfg_regmap, + google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, reg); +} + +static int dwc3_google_probe(struct platform_device *pdev) +{ + struct dwc3_probe_data probe_data =3D {}; + struct device *dev =3D &pdev->dev; + struct dwc3_google *google; + struct resource *res; + int ret; + u32 args[2]; + + google =3D devm_kzalloc(&pdev->dev, sizeof(*google), GFP_KERNEL); + if (!google) + return -ENOMEM; + + google->dev =3D &pdev->dev; + + ret =3D dwc3_google_pm_domain_init(google); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to init pdom\n"); + + google->usb_cfg_regmap =3D + syscon_regmap_lookup_by_phandle_args(dev->of_node, + "google,usb-cfg-csr", + ARRAY_SIZE(args), args); + if (IS_ERR(google->usb_cfg_regmap)) { + return dev_err_probe(dev, PTR_ERR(google->usb_cfg_regmap), + "invalid usb cfg csr\n"); + } + + google->host_cfg_offset =3D args[0]; + google->usbint_cfg_offset =3D args[1]; + + if (device_property_match_string(dev, "phy-names", "usb3-phy") < 0) { + google->is_usb2only =3D true; + dwc3_google_program_usb2only(google); + } + + ret =3D devm_clk_bulk_get_all_enabled(dev, &google->clks); + if (ret < 0) { + ret =3D dev_err_probe(dev, ret, "failed to get and enable clks\n"); + goto err_deinit_pdom; + } + google->num_clks =3D ret; + + ret =3D dwc3_google_rst_init(google); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to get resets\n"); + goto err_deinit_pdom; + } + + ret =3D reset_control_bulk_deassert(google->num_rsts, google->rsts); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to deassert rsts\n"); + goto err_deinit_pdom; + } + + ret =3D dwc3_google_request_irq(google, pdev, "hs_pme", "USB HS wakeup"); + if (ret < 0) { + ret =3D dev_err_probe(dev, ret, "failed to request hs pme irq"); + goto err_reset_assert; + } + google->hs_pme_irq =3D ret; + + ret =3D dwc3_google_request_irq(google, pdev, "ss_pme", "USB SS wakeup"); + if (ret < 0) { + ret =3D dev_err_probe(dev, ret, "failed to request ss pme irq"); + goto err_reset_assert; + } + google->ss_pme_irq =3D ret; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret =3D dev_err_probe(dev, -ENODEV, "invalid memory\n"); + goto err_reset_assert; + } + + device_init_wakeup(dev, true); + + google->dwc.dev =3D dev; + probe_data.dwc =3D &google->dwc; + probe_data.res =3D res; + probe_data.ignore_clocks_and_resets =3D true; + ret =3D dwc3_core_probe(&probe_data); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); + goto err_reset_assert; + } + + return 0; + +err_reset_assert: + reset_control_bulk_assert(google->num_rsts, google->rsts); + +err_deinit_pdom: + dwc3_google_pm_domain_deinit(google); + + return ret; +} + +static void dwc3_google_remove(struct platform_device *pdev) +{ + struct dwc3 *dwc =3D platform_get_drvdata(pdev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + + dwc3_core_remove(&google->dwc); + + reset_control_bulk_assert(google->num_rsts, google->rsts); + + dwc3_google_pm_domain_deinit(google); +} + +static int dwc3_google_suspend(struct dwc3_google *google, pm_message_t ms= g) +{ + if (pm_runtime_suspended(google->dev)) + return 0; + + if (google->dwc.current_dr_role =3D=3D DWC3_GCTL_PRTCAP_HOST) { + /* + * Follow dwc3_suspend_common() guidelines for deciding between + * a full teardown and hibernation. + */ + if (PMSG_IS_AUTO(msg) || device_may_wakeup(google->dev)) { + dev_dbg(google->dev, "enter hibernation"); + pm_runtime_get_sync(google->usb_top_pd); + device_wakeup_enable(google->usb_top_pd); + dwc3_google_enable_pme_irq(google); + google->is_hibernation =3D true; + return 0; + } + } + + reset_control_bulk_assert(google->num_rsts, google->rsts); + clk_bulk_disable_unprepare(google->num_clks, google->clks); + + return 0; +} + +static int dwc3_google_resume(struct dwc3_google *google, pm_message_t msg) +{ + int ret; + + if (google->is_hibernation) { + dev_dbg(google->dev, "exit hibernation"); + dwc3_google_disable_pme_irq(google); + device_wakeup_disable(google->usb_top_pd); + pm_runtime_put_sync(google->usb_top_pd); + google->is_hibernation =3D false; + return 0; + } + + if (google->is_usb2only) + dwc3_google_program_usb2only(google); + + ret =3D clk_bulk_prepare_enable(google->num_clks, google->clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(google->num_rsts, google->rsts); + if (ret) { + clk_bulk_disable_unprepare(google->num_clks, google->clks); + return ret; + } + + return 0; +} + +static int dwc3_google_pm_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_pm_suspend(&google->dwc); + if (ret) + return ret; + + return dwc3_google_suspend(google, PMSG_SUSPEND); +} + +static int dwc3_google_pm_resume(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_google_resume(google, PMSG_RESUME); + if (ret) + return ret; + + return dwc3_pm_resume(&google->dwc); +} + +static void dwc3_google_complete(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + dwc3_pm_complete(dwc); +} + +static int dwc3_google_prepare(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + return dwc3_pm_prepare(dwc); +} + +static int dwc3_google_runtime_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_runtime_suspend(&google->dwc); + if (ret) + return ret; + + return dwc3_google_suspend(google, PMSG_AUTO_SUSPEND); +} + +static int dwc3_google_runtime_resume(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_google_resume(google, PMSG_AUTO_RESUME); + if (ret) + return ret; + + return dwc3_runtime_resume(&google->dwc); +} + +static int dwc3_google_runtime_idle(struct device *dev) +{ + return dwc3_runtime_idle(dev_get_drvdata(dev)); +} + +static const struct dev_pm_ops dwc3_google_dev_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(dwc3_google_pm_suspend, dwc3_google_pm_resume) + RUNTIME_PM_OPS(dwc3_google_runtime_suspend, dwc3_google_runtime_resume, + dwc3_google_runtime_idle) + .complete =3D pm_sleep_ptr(dwc3_google_complete), + .prepare =3D pm_sleep_ptr(dwc3_google_prepare), +}; + +static const struct of_device_id dwc3_google_of_match[] =3D { + { .compatible =3D "google,lga-dwc3" }, + { } +}; +MODULE_DEVICE_TABLE(of, dwc3_google_of_match); + +static struct platform_driver dwc3_google_driver =3D { + .probe =3D dwc3_google_probe, + .remove =3D dwc3_google_remove, + .driver =3D { + .name =3D "google-dwc3", + .pm =3D pm_ptr(&dwc3_google_dev_pm_ops), + .of_match_table =3D dwc3_google_of_match, + }, +}; + +module_platform_driver(dwc3_google_driver); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DesignWare DWC3 Google Glue Driver"); --=20 2.51.2.1041.gc1ab5b90ca-goog