From nobody Fri Dec 19 19:17:21 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3AAE3002A3; Wed, 12 Nov 2025 10:12:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942323; cv=none; b=ZJeyh9wqoiWOc/9hMZu+kMI1p7LZCmzQNkfB9kU3Jn3FIf/u5wXHmb0hC+jOn9znq0HoMJhm3XbeehHzG0MwrS09BmstyO95IWky/zY2zrFgk2JOrOigbyxTC9bsPM8r1E7LR8BZs5NRdturvszB5O5by+/nkrbQ6eFdTJSMgr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942323; c=relaxed/simple; bh=Obpd//VpUN2twV+EMu4LchAWePJkY0WgL7SJD42yqv8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WJwGP4iDYI+UVMZVkAM7u25B++NdfK55QtDvcCmpeE5m51chZWgTli2M1QvNvmxrvBE/grLljQNncUGNLkOCgrMiQOGTkW1fITNQGWqqS4J22y6sgpd1hblJpsNGXSgJMzeuC5rQnz+/Qu8NxWC50ldJajy6FUoufmT2iszjNYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 12 Nov 2025 18:11:57 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 12 Nov 2025 18:11:57 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , CC: Conor Dooley Subject: [PATCH v8 1/4] dt-bindings: arm: aspeed: Add AST2700 board compatible Date: Wed, 12 Nov 2025 18:11:54 +0800 Message-ID: <20251112101157.2149169-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> References: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree compatible string for AST2700 based boards ("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC board bindings. This allows proper schema validation and enables support for AST2700 platforms. Signed-off-by: Ryan Chen Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index aedefca7cf4a..1c1a12fc3a91 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -109,4 +109,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 =20 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true --=20 2.34.1 From nobody Fri Dec 19 19:17:21 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1888301495; Wed, 12 Nov 2025 10:12:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942325; cv=none; b=WHvVkLUYs9a8PT/rpXg8mtJnZmgOkl8VFPFUqplFqf/nJYq4wEn1nAkMIcALZP7Qf9Xw1+2G8reSrC+sth9KFg+vSRHlUxsuAekwSC4/f/2gHV8teb5KUrIruG48nAiRgiEoiy/+9DuzDPdSyiy5HMbEpQp5FjzyQuAA/JppUks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942325; c=relaxed/simple; bh=BAYMByeTWbf6H+zSOF0w2OtICBfA8D+kxFgeDUaNptY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pmJmigsGEFtYYBTdAc1P7gK6nwmkgYb0hIBLxuMduLP16Fn349IgHFgoFZurwm/4RNyQEXZX0vL88jfsEvuoiCxVGYV6uZ5ftt5GlLO+6RyNQxUyNksu7hpX5mEr8728s+IYcnoGLjHVvVhWfOJ4l+F1P7k461ue0Nq1N2lvMAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 12 Nov 2025 18:11:57 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 12 Nov 2025 18:11:57 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , Subject: [PATCH v8 2/4] arm64: Kconfig: Add ASPEED SoC family Kconfig support Date: Wed, 12 Nov 2025 18:11:55 +0800 Message-ID: <20251112101157.2149169-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> References: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for ASPEED SoC family like ast27XX 8th generation ASPEED BMCs. Signed-off-by: Ryan Chen --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 13173795c43d..ac304048a84e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -47,6 +47,12 @@ config ARCH_ARTPEC help This enables support for the ARMv8 based ARTPEC SoC Family. =20 +config ARCH_ASPEED + bool "Aspeed SoC family" + help + This enables support for ASPEED SoC family like ast27XX 8th + generation Aspeed BMCs. + config ARCH_AXIADO bool "Axiado SoC Family" select GPIOLIB --=20 2.34.1 From nobody Fri Dec 19 19:17:21 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D31883016FE; Wed, 12 Nov 2025 10:12:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942328; cv=none; b=jA99yu+/f2UCmIKT6L6eIEzok5vbFBNpMebOvYU9p44kqdxkSEG8kO8ePLhTW/7aSPDCLKbLRqYVAw1k9pyN5noPJJ/Xcosf92L4LOzO3RJP2hOPyNzrbr0hWK2dX4e084mvrdTxQdjVcv6rQ4+emn1QPvm48uDZAoUzsEnl4uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942328; c=relaxed/simple; bh=QTXeJF1dbVUewGCEY5qenkMe+R29cbeWNAs2lslXmRo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s9Y0S0Th/Lv0e3Vx9kZPnlyZq9z5Aiy/FdKd3M5h6jhWe+Ljv02/1jYat9zsL60EnxGvrckeBL+A3RWlHKzVi5C9E7lxT/WgpXtnuc5Wkl8N08uN7kvL5lbYJLKQITbUhA8FLHiQ2WM1KJXHDOoF9pgPxX46stj99rBNtq2/Iis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 12 Nov 2025 18:11:57 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 12 Nov 2025 18:11:57 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , Subject: [PATCH v8 3/4] arm64: dts: aspeed: Add initial AST27xx SoC device tree Date: Wed, 12 Nov 2025 18:11:56 +0800 Message-ID: <20251112101157.2149169-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> References: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial device tree support for the ASPEED AST27xx family, the 8th-generation Baseboard Management Controller (BMC) SoCs. AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ The AST27xx features a dual-SoC architecture consisting of two ties, referred to as SoC0 and SoC1 - interconnected through an internal property bus. Both SoCs share the same address decoding scheme, while each maintains independent clock and reset domains. - SoC0 (CPU die): contains a dual-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals. - SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals. The device tree describes the SoC0 and SoC1 domains and their peripheral layouts. Signed-off-by: Ryan Chen --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/Makefile | 4 + arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi | 154 ++++++++ .../boot/dts/aspeed/aspeed-g7-common.dtsi | 351 ++++++++++++++++++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 31 ++ 5 files changed, 541 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-common.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index b0844404eda1..5b8fbf5b1061 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D amlogic subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm +subdir-y +=3D aspeed subdir-y +=3D axiado subdir-y +=3D bitmain subdir-y +=3D blaize diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspe= ed/Makefile new file mode 100644 index 000000000000..ffe7e15017cc --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ASPEED) +=3D \ + ast2700-evb.dtb diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi b/arch/arm64/boo= t/dts/aspeed/aspeed-g7-a35.dtsi new file mode 100644 index 000000000000..da8869a74b35 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AST27xx SoC Family + * + * Copyright (C) ASPEED Technology Inc. + */ + +#include + +/ { + compatible =3D "aspeed,ast2700"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x3>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + }; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + atf: trusted-firmware-a@430000000 { + reg =3D <0x4 0x30000000 0x0 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg =3D <0x4 0x30080000 0x0 0x1000000>; + no-map; + }; + }; + + arm-pmu { + compatible =3D "arm,cortex-a35-pmu"; + interrupts =3D ; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + gic: interrupt-controller@12200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + + soc0: bus@10000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>; + }; + + soc1: bus@14000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x14000000 0x0 0x14000000 0x0 0xD00000>; + }; +}; + +#include "aspeed-g7-common.dtsi" diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-common.dtsi b/arch/arm64/= boot/dts/aspeed/aspeed-g7-common.dtsi new file mode 100644 index 000000000000..95c548465d0a --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-common.dtsi @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AST27xx SoC Family Main Domain peripherals + * + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include + +&soc0 { + sram0: sram@10000000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x10000000 0x0 0x20000>; + ranges =3D <0x0 0x0 0x10000000 0x20000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + soc0-sram@0 { + reg =3D <0x0 0x20000>; + export; + }; + }; + + intc0_11: interrupt-controller@12101b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x12101b00 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + }; + + syscon0: syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg =3D <0x0 0x12c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x12c02000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + silicon-id@0 { + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg =3D <0x0 0x4>; + }; + + scu_ic0: interrupt-controller@1d0 { + compatible =3D "aspeed,ast2700-scu-ic0"; + reg =3D <0x1d0 0xc>; + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@1e0 { + compatible =3D "aspeed,ast2700-scu-ic1"; + reg =3D <0x1e0 0xc>; + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-controller; + }; + }; + + gpio0: gpio@12c11000 { + #gpio-cells =3D <2>; + gpio-controller; + compatible =3D "aspeed,ast2700-gpio"; + reg =3D <0x0 0x12c11000 0x0 0x1000>; + interrupts =3D ; + ngpios =3D <12>; + clocks =3D <&syscon0 SCU0_CLK_APB>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + uart4: serial@12c1a000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x12c1a000 0x0 0x1000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon0 SCU0_CLK_GATE_UART4CLK>; + interrupts =3D ; + no-loopback-test; + status =3D "disabled"; + }; +}; + +&soc1 { + sram1: sram@14b80000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x14b80000 0x0 0x40000>; + ranges =3D <0x0 0x0 0x14b80000 0x40000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + soc1-sram@0 { + reg =3D <0x0 0x40000>; + export; + }; + }; + + syscon1: syscon@14c02000 { + compatible =3D "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg =3D <0x0 0x14c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x14c02000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + scu_ic2: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-scu-ic2"; + reg =3D <0x100 0x8>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc1_5 0>; + interrupt-controller; + }; + + scu_ic3: interrupt-controller@108 { + compatible =3D "aspeed,ast2700-scu-ic3"; + reg =3D <0x108 0x8>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc1_5 26>; + interrupt-controller; + }; + }; + + gpio1: gpio@14c0b000 { + #gpio-cells =3D <2>; + gpio-controller; + compatible =3D "aspeed,ast2700-gpio"; + reg =3D <0x0 0x14c0b000 0x0 0x1000>; + interrupts-extended =3D <&intc1_2 18>; + ngpios =3D <216>; + clocks =3D <&syscon1 SCU1_CLK_AHB>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + intc1_0: interrupt-controller@14c18100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18100 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0>; + }; + + intc1_1: interrupt-controller@14c18110 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18110 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 1>; + }; + + intc1_2: interrupt-controller@14c18120 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18120 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 2>; + }; + + intc1_3: interrupt-controller@14c18130 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18130 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 3>; + }; + + intc1_4: interrupt-controller@14c18140 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18140 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 4>; + }; + + intc1_5: interrupt-controller@14c18150 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18150 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 5>; + }; + + uart0: serial@14c33000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART0CLK>; + interrupts-extended =3D <&intc1_4 7>; + no-loopback-test; + status =3D "disabled"; + }; + + uart1: serial@14c33100 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33100 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART1CLK>; + interrupts-extended =3D <&intc1_4 8>; + no-loopback-test; + status =3D "disabled"; + }; + + uart2: serial@14c33200 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33200 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART2CLK>; + interrupts-extended =3D <&intc1_4 9>; + no-loopback-test; + status =3D "disabled"; + }; + + uart3: serial@14c33300 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33300 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART3CLK>; + interrupts-extended =3D <&intc1_4 10>; + no-loopback-test; + status =3D "disabled"; + }; + + uart5: serial@14c33400 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33400 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART5CLK>; + interrupts-extended =3D <&intc1_4 11>; + no-loopback-test; + status =3D "disabled"; + }; + + uart6: serial@14c33500 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33500 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART6CLK>; + interrupts-extended =3D <&intc1_4 12>; + no-loopback-test; + status =3D "disabled"; + }; + + uart7: serial@14c33600 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33600 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART7CLK>; + interrupts-extended =3D <&intc1_4 13>; + no-loopback-test; + status =3D "disabled"; + }; + + uart8: serial@14c33700 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33700 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART8CLK>; + interrupts-extended =3D <&intc1_4 14>; + no-loopback-test; + status =3D "disabled"; + }; + + uart9: serial@14c33800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33800 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART9CLK>; + interrupts-extended =3D <&intc1_4 15>; + no-loopback-test; + status =3D "disabled"; + }; + + uart10: serial@14c33900 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33900 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART10CLK>; + interrupts-extended =3D <&intc1_4 16>; + no-loopback-test; + status =3D "disabled"; + }; + + uart11: serial@14c33a00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33a00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART11CLK>; + interrupts-extended =3D <&intc1_4 17>; + no-loopback-test; + status =3D "disabled"; + }; + + uart12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART12CLK>; + interrupts-extended =3D <&intc1_4 18>; + no-loopback-test; + status =3D "disabled"; + }; + + uart13: serial@14c33c00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33c00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_UART13>; + interrupts-extended =3D <&intc1_0 23>; + no-loopback-test; + status =3D "disabled"; + }; + + uart14: serial@14c33d00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33d00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_UART14>; + interrupts-extended =3D <&intc1_1 23>; + no-loopback-test; + status =3D "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/d= ts/aspeed/ast2700-evb.dts new file mode 100644 index 000000000000..0ecedf11a5e6 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source AST2700 EVB + * + * Copyright (C) ASPEED Technology Inc. + */ + +/dts-v1/; +#include "aspeed-g7-a35.dtsi" + +/ { + model =3D "AST2700 EVB"; + compatible =3D "aspeed,ast2700-evb", "aspeed,ast2700"; + + aliases { + serial0 =3D &uart12; /* console port */ + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x0 0x40000000>; + }; +}; + +&uart12 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Fri Dec 19 19:17:21 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D9D7302CB1; Wed, 12 Nov 2025 10:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762942329; cv=none; b=u3lehiTCvzF83FcsjuVHwSX8YCmmJuAiidYMxmnpqPhik57U79F4o0IVkPsVjry3SPIls6sXPAbouqTKLQSN2P+Zj9/G+8iLF1+9sBbbJ0OvKMw/MgMf+Jr47D1jCDz8ck/olewOv3QyRKQ5e9N4LtwDx+H1nn6Ij1pUlKi8bc4= ARC-Message-Signature: i=1; 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Wed, 12 Nov 2025 18:11:57 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , CC: Krzysztof Kozlowski Subject: [PATCH v8 4/4] arm64: configs: Update defconfig for AST2700 platform support Date: Wed, 12 Nov 2025 18:11:57 +0800 Message-ID: <20251112101157.2149169-5-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> References: <20251112101157.2149169-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable options for ASPEED AST2700 SoC. Signed-off-by: Ryan Chen Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e3a2d37bd104..ca2978dd1ccc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy CONFIG_ARCH_ARTPEC=3Dy +CONFIG_ARCH_ASPEED=3Dy CONFIG_ARCH_AXIADO=3Dy CONFIG_ARCH_BCM=3Dy CONFIG_ARCH_BCM2835=3Dy --=20 2.34.1