From nobody Sun Feb 8 23:35:10 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A871B2FD677; Wed, 12 Nov 2025 08:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762937823; cv=none; b=EfLAPSiQekU22aq4vlJZhJ4GQ2JR1Q6Q0WAfyVT+NPnT5pETrdCN24tb97hwuLz34wAVtiwLWcx6tX6dwt09yOdHV9ls+3YX4GOSxwOXYl2Xi1n0nSOrwdUKmy/7XVBF5thGvaijL6ESZxdOvEtaxvCfo+ctJIWp8JAQfFYXPf4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762937823; c=relaxed/simple; bh=TpnqB5cVEldbbxbB1iMBExcXlvHntIUf7yAJgYYCb7c=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I1dm/854ALhk5R8oeJipHBBpb8py+FUnxeg7y/JyZStVUuZZdoyoSusNtEW9A1j5mDTmZ0aJo7oNqOY9uhjNNzOc5tUy7P4Ldgvbef340QkgU7SuYTrdrkK6FI1M2m2wYYZ3yd+vMiY53veafi1sp14jy5RujzoEZgHWsNAD92I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 12 Nov 2025 16:56:49 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 12 Nov 2025 16:56:49 +0800 From: Ryan Chen To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v22 1/4] dt-bindings: i2c: Split AST2600 binding into a new YAML Date: Wed, 12 Nov 2025 16:56:46 +0800 Message-ID: <20251112085649.1903631-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251112085649.1903631-1-ryan_chen@aspeedtech.com> References: <20251112085649.1903631-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2600 I2C controller introduces a completely new register map and Separate control/target register sets, unlike the mixed layout used in AST2400/AST2500. In addition, at new AST2600 configuration registers and transfer modes require new DT properties, which are incompatible with existing bindings. Therefore, this creates a dedicated binding file for AST2600 to properly describe these new hardware capabilities. A subsequent change will modify this new binding to properly describe the AST2600 hardware. The example section updated to reflect the actual AST2600 SoC register layout and interrupt configuration. Reference: aspeed-g6.dtsi (lines 885-897) -I2C bus and buffeset address offsets - AST2600 I2C controller register base starts from 0x80, and the buffer region is located at 0xc00, as defined in AST2600 SOC register map. -Interrupt configuration - AST2600 U2C controller are connected to ARM GIC interrupt controller rather than the legacy internal interrupt controller. Signed-off-by: Ryan Chen --- .../bindings/i2c/aspeed,ast2600-i2c.yaml | 67 +++++++++++++++++++ .../devicetree/bindings/i2c/aspeed,i2c.yaml | 3 +- 2 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2= c.yaml diff --git a/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml = b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml new file mode 100644 index 000000000000..e6ed84c53639 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/aspeed,ast2600-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED I2C on the AST26XX SoCs + +maintainers: + - Ryan Chen + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - aspeed,ast2600-i2c-bus + + reg: + minItems: 1 + maxItems: 2 + description: + The first region covers the controller registers. + The optional second region covers the controller's buffer space. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + root clock of bus, should reference the APB + clock in the second cell + + clock-frequency: + description: Desired operating frequency of the I2C bus in Hz. + minimum: 500 + maximum: 4000000 + default: 100000 + + resets: + maxItems: 1 + +required: + - reg + - compatible + - clocks + - resets + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c@80 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "aspeed,ast2600-i2c-bus"; + reg =3D <0x80 0x80>, <0xc00 0x20>; + clocks =3D <&syscon ASPEED_CLK_APB>; + resets =3D <&syscon ASPEED_RESET_I2C>; + clock-frequency =3D <100000>; + interrupts =3D ; + }; diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Docume= ntation/devicetree/bindings/i2c/aspeed,i2c.yaml index 5b9bd2feda3b..d4e4f412feba 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs +title: ASPEED I2C on the AST24XX, AST25XX SoCs =20 maintainers: - Rayn Chen @@ -17,7 +17,6 @@ properties: enum: - aspeed,ast2400-i2c-bus - aspeed,ast2500-i2c-bus - - aspeed,ast2600-i2c-bus =20 reg: minItems: 1 --=20 2.34.1