From nobody Sun Feb 8 11:21:28 2026 Received: from canpmsgout01.his.huawei.com (canpmsgout01.his.huawei.com [113.46.200.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B03992951B3; Wed, 12 Nov 2025 01:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.216 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762912736; cv=none; b=axFkhy5aByUz7iVoFIJ12uN9QWe+RX81dXqaHbcOTXUrQXYqYc97sDAS3SbtxzIa9BwJp4Dld96NsIQAxvGlT01yV4ggKAXbWgKkcPykYvkhMgYOCP6evM7Ton9HRqZt8rHA85+h8SIeiIl6rA3E1xPmJ27Jd0r/qZMMcPYMKlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762912736; c=relaxed/simple; bh=tzZa6vtYzmz6G0etazCSQ4lDn5Fz76x4TG1FiuJJ/xA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jca3A8wSsY1HVn+icILgjXW8EG0RkeO7Th4x8bEiRdUswALtQzOuDmV+jqRxn5tdeTLZWrmKKh03n8qOPasNfZFMQBJAdQuJdCYDKwxvjlzusVvrTH3KmuJCaKQf/2qKdSo8eZvT+W1m04a0Z07dqjGIcK+awMzrDX2CfEJUKCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=X6AmB1Tg; arc=none smtp.client-ip=113.46.200.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="X6AmB1Tg" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=yI+shLkJDKP9R9FfeV7amQ3F21U8McCYPl060RXsF6s=; b=X6AmB1TgFNTa6XtAjH1xMk95R+gRIPwso7WvfB00LQM7JQa+5LFCIbkXRJq9/OzVFeyfs2INg I10eYgoZNuBnxKDS+KEZC+gHaV1dyhKTI8zw9CBXFptqDB9FIeayEBY5aLLfO2NjrS4MLJYbKml riib1ZHqWsETQJUaT4rhGvI= Received: from mail.maildlp.com (unknown [172.19.163.174]) by canpmsgout01.his.huawei.com (SkyGuard) with ESMTPS id 4d5mkG4hQvz1T4Fs; Wed, 12 Nov 2025 09:57:26 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id 81DFC1400E3; Wed, 12 Nov 2025 09:58:49 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 12 Nov 2025 09:58:49 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 12 Nov 2025 09:58:48 +0800 From: Chenghai Huang To: , , , , , , , , , , , , CC: , , , Subject: [PATCH RFC 1/4] UAPI: Introduce 128-bit types and byteswap operations Date: Wed, 12 Nov 2025 09:58:43 +0800 Message-ID: <20251112015846.1842207-2-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251112015846.1842207-1-huangchenghai2@huawei.com> References: <20251112015846.1842207-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian Architectures like ARM64 support 128-bit integer types and operations. This patch adds a generic byte order conversion interface for 128-bit. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- include/uapi/linux/byteorder/big_endian.h | 6 ++++++ include/uapi/linux/byteorder/little_endian.h | 6 ++++++ include/uapi/linux/swab.h | 10 ++++++++++ include/uapi/linux/types.h | 3 +++ 4 files changed, 25 insertions(+) diff --git a/include/uapi/linux/byteorder/big_endian.h b/include/uapi/linux= /byteorder/big_endian.h index 80aa5c41a763..318d51a18f43 100644 --- a/include/uapi/linux/byteorder/big_endian.h +++ b/include/uapi/linux/byteorder/big_endian.h @@ -29,6 +29,12 @@ #define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x)) #define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x)) #define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x)) + +#ifdef __SIZEOF_INT128__ +#define __cpu_to_le128(x) ((__force __le128)__swab128((x))) +#define __le128_to_cpu(x) __swab128((__force __u128)(__le128)(x)) +#endif + #define __cpu_to_le64(x) ((__force __le64)__swab64((x))) #define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x)) #define __cpu_to_le32(x) ((__force __le32)__swab32((x))) diff --git a/include/uapi/linux/byteorder/little_endian.h b/include/uapi/li= nux/byteorder/little_endian.h index cd98982e7523..b2732452b825 100644 --- a/include/uapi/linux/byteorder/little_endian.h +++ b/include/uapi/linux/byteorder/little_endian.h @@ -29,6 +29,12 @@ #define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be3= 2)(x)) #define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x))) #define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be1= 6)(x)) + +#ifdef __SIZEOF_INT128__ +#define __cpu_to_le128(x) ((__force __le128)(__u128)(x)) +#define __le128_to_cpu(x) ((__force __u128)(__le128)(x)) +#endif + #define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) #define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) diff --git a/include/uapi/linux/swab.h b/include/uapi/linux/swab.h index 01717181339e..7381b9a785ce 100644 --- a/include/uapi/linux/swab.h +++ b/include/uapi/linux/swab.h @@ -133,6 +133,16 @@ static inline __attribute_const__ __u32 __fswahb32(__u= 32 val) __fswab64(x)) #endif =20 +#ifdef __SIZEOF_INT128__ +static inline __attribute_const__ __u128 __swab128(__u128 val) +{ + __u64 h =3D val >> 64; + __u64 l =3D val; + + return (((__u128)__swab64(l)) << 64) | ((__u128)(__swab64(h))); +} +#endif + static __always_inline unsigned long __swab(const unsigned long y) { #if __BITS_PER_LONG =3D=3D 64 diff --git a/include/uapi/linux/types.h b/include/uapi/linux/types.h index 48b933938877..9624ea43cd8a 100644 --- a/include/uapi/linux/types.h +++ b/include/uapi/linux/types.h @@ -40,6 +40,9 @@ typedef __u32 __bitwise __be32; typedef __u64 __bitwise __le64; typedef __u64 __bitwise __be64; =20 +#ifdef __SIZEOF_INT128__ +typedef __u128 __bitwise __le128; +#endif typedef __u16 __bitwise __sum16; typedef __u32 __bitwise __wsum; =20 --=20 2.33.0 From nobody Sun Feb 8 11:21:28 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A381B291C07; Wed, 12 Nov 2025 01:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 12 Nov 2025 09:58:49 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 12 Nov 2025 09:58:49 +0800 From: Chenghai Huang To: , , , , , , , , , , , , CC: , , , Subject: [PATCH RFC 2/4] asm-generic/io.h: add io{read,write}128 accessors Date: Wed, 12 Nov 2025 09:58:44 +0800 Message-ID: <20251112015846.1842207-3-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251112015846.1842207-1-huangchenghai2@huawei.com> References: <20251112015846.1842207-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian Architectures like ARM64 already support 128-bit memory access. Currently, device drivers implement atomic read and write operations for 128-bit memory using assembly. This patch adds generic io{read,write}128 access functions, which will enable device drivers to consistently use io{read,write}128 for 128-bit access. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- include/asm-generic/io.h | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index ca5a1ce6f0f8..c419021318e6 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -146,6 +146,16 @@ static inline u64 __raw_readq(const volatile void __io= mem *addr) #endif #endif /* CONFIG_64BIT */ =20 +#ifdef CONFIG_ARCH_SUPPORTS_INT128 +#ifndef __raw_read128 +#define __raw_read128 __raw_read128 +static inline u128 __raw_read128(volatile void __iomem *addr) +{ + return *(const volatile u128 __force *)addr; +} +#endif +#endif /* CONFIG_ARCH_SUPPORTS_INT128 */ + #ifndef __raw_writeb #define __raw_writeb __raw_writeb static inline void __raw_writeb(u8 value, volatile void __iomem *addr) @@ -180,6 +190,16 @@ static inline void __raw_writeq(u64 value, volatile vo= id __iomem *addr) #endif #endif /* CONFIG_64BIT */ =20 +#ifdef CONFIG_ARCH_SUPPORTS_INT128 +#ifndef __raw_write128 +#define __raw_write128 __raw_write128 +static inline void __raw_write128(u128 value, volatile void __iomem *addr) +{ + *(volatile u128 __force *)addr =3D value; +} +#endif +#endif /* CONFIG_ARCH_SUPPORTS_INT128 */ + /* * {read,write}{b,w,l,q}() access little endian memory and return result in * native endianness. @@ -917,6 +937,22 @@ static inline u64 ioread64(const volatile void __iomem= *addr) #endif #endif /* CONFIG_64BIT */ =20 +#ifdef CONFIG_ARCH_SUPPORTS_INT128 +#ifndef ioread128 +#define ioread128 ioread128 +static inline u128 ioread128(const volatile void __iomem *addr) +{ + u128 val; + + __io_br(); + val =3D __le128_to_cpu((__le128 __force)__raw_read128(addr)); + __io_ar(val); + + return val; +} +#endif +#endif /* CONFIG_ARCH_SUPPORTS_INT128 */ + #ifndef iowrite8 #define iowrite8 iowrite8 static inline void iowrite8(u8 value, volatile void __iomem *addr) @@ -951,6 +987,18 @@ static inline void iowrite64(u64 value, volatile void = __iomem *addr) #endif #endif /* CONFIG_64BIT */ =20 +#ifdef CONFIG_ARCH_SUPPORTS_INT128 +#ifndef iowrite128 +#define iowrite128 iowrite128 +static inline void iowrite128(u128 value, volatile void __iomem *addr) +{ + __io_bw(); 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Wed, 12 Nov 2025 09:58:49 +0800 From: Chenghai Huang To: , , , , , , , , , , , , CC: , , , Subject: [PATCH RFC 3/4] io-128-nonatomic: introduce io{read|write}128_{lo_hi|hi_lo} Date: Wed, 12 Nov 2025 09:58:45 +0800 Message-ID: <20251112015846.1842207-4-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251112015846.1842207-1-huangchenghai2@huawei.com> References: <20251112015846.1842207-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian In order to provide non-atomic functions for io{read|write}128. We define a number of variants of these functions in the generic iomap that will do non-atomic operations. These functions are only defined if io{read|write}128 are defined. If they are not, then the wrappers that always use non-atomic operations from include/linux/io-128-nonatomic*.h will be used. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- include/linux/io-128-nonatomic-hi-lo.h | 35 ++++++++++++++++++++++++++ include/linux/io-128-nonatomic-lo-hi.h | 34 +++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 include/linux/io-128-nonatomic-hi-lo.h create mode 100644 include/linux/io-128-nonatomic-lo-hi.h diff --git a/include/linux/io-128-nonatomic-hi-lo.h b/include/linux/io-128-= nonatomic-hi-lo.h new file mode 100644 index 000000000000..b5b083a9e81b --- /dev/null +++ b/include/linux/io-128-nonatomic-hi-lo.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_IO_128_NONATOMIC_HI_LO_H_ +#define _LINUX_IO_128_NONATOMIC_HI_LO_H_ + +#include +#include + +static inline u128 ioread128_hi_lo(const void __iomem *addr) +{ + u32 low, high; + + high =3D ioread64(addr + sizeof(u64)); + low =3D ioread64(addr); + + return low + ((u128)high << 64); +} + +static inline void iowrite128_hi_lo(u128 val, void __iomem *addr) +{ + iowrite64(val >> 64, addr + sizeof(u64)); + iowrite64(val, addr); +} + +#ifndef ioread128 +#define ioread128_is_nonatomic +#define ioread128 ioread128_hi_lo +#endif + +#ifndef iowrite128 +#define iowrite128_is_nonatomic +#define iowrite128 iowrite128_hi_lo +#endif + +#endif /* _LINUX_IO_128_NONATOMIC_HI_LO_H_ */ + diff --git a/include/linux/io-128-nonatomic-lo-hi.h b/include/linux/io-128-= nonatomic-lo-hi.h new file mode 100644 index 000000000000..0448ee5a13de --- /dev/null +++ b/include/linux/io-128-nonatomic-lo-hi.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_IO_128_NONATOMIC_LO_HI_H_ +#define _LINUX_IO_128_NONATOMIC_LO_HI_H_ + +#include +#include + +static inline u128 ioread128_lo_hi(const void __iomem *addr) +{ + u64 low, high; + + low =3D ioread64(addr); + high =3D ioread64(addr + sizeof(u64)); + + return low + ((u128)high << 64); +} + +static inline void iowrite128_lo_hi(u128 val, void __iomem *addr) +{ + iowrite64(val, addr); + iowrite64(val >> 64, addr + sizeof(u64)); +} + +#ifndef ioread128 +#define ioread128_is_nonatomic +#define ioread128 ioread128_lo_hi +#endif + +#ifndef iowrite128 +#define iowrite128_is_nonatomic +#define iowrite128 iowrite128_lo_hi +#endif + +#endif /* _LINUX_IO_128_NONATOMIC_LO_HI_H_ */ --=20 2.33.0 From nobody Sun Feb 8 11:21:28 2026 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB66E21ADCB; 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Wed, 12 Nov 2025 09:58:50 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 12 Nov 2025 09:58:50 +0800 From: Chenghai Huang To: , , , , , , , , , , , , CC: , , , Subject: [PATCH RFC 4/4] arm64/io: Add {__raw_read|__raw_write}128 support Date: Wed, 12 Nov 2025 09:58:46 +0800 Message-ID: <20251112015846.1842207-5-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251112015846.1842207-1-huangchenghai2@huawei.com> References: <20251112015846.1842207-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian Starting from ARMv8.4, stp and ldp instructions become atomic. Currently, device drivers depend on 128-bit atomic memory IO access, but these are implemented within the drivers. Therefore, this introduces generic {__raw_read|__raw_write}128 function for 128-bit memory access. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- arch/arm64/include/asm/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 83e03abbb2ca..80430750a28c 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -50,6 +50,17 @@ static __always_inline void __raw_writeq(u64 val, volati= le void __iomem *addr) asm volatile("str %x0, %1" : : "rZ" (val), "Qo" (*ptr)); } =20 +#define __raw_write128 __raw_write128 +static __always_inline void __raw_write128(u128 val, volatile void __iomem= *addr) +{ + u64 low, high; + + low =3D val; + high =3D (u64)(val >> 64); + + asm volatile ("stp %x0, %x1, [%2]\n" :: "rZ"(low), "rZ"(high), "r"(addr)); +} + #define __raw_readb __raw_readb static __always_inline u8 __raw_readb(const volatile void __iomem *addr) { @@ -95,6 +106,16 @@ static __always_inline u64 __raw_readq(const volatile v= oid __iomem *addr) return val; } =20 +#define __raw_read128 __raw_read128 +static __always_inline u128 __raw_read128(const volatile void __iomem *add= r) +{ + u64 high, low; + + asm volatile("ldp %0, %1, [%2]" : "=3Dr" (low), "=3Dr" (high) : "r" (addr= )); + + return (((u128)high << 64) | (u128)low); +} + /* IO barriers */ #define __io_ar(v) \ ({ \ --=20 2.33.0