From nobody Wed Dec 10 20:13:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CA80212B31; Thu, 13 Nov 2025 00:43:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762994622; cv=none; b=IYkRVEozwHmpW/U7BjBBjL4VWDOt4T/2Sg/PkbAJo2fZbDdhhLv5jc/9zXH6O8u70YsJcwbufppBoqOkTqxTO0izTqayihfFZvUEFQ21/AwxTV25QgcVF9V56wYspc/Bp5ZarQDLs+btTvN95TbwbtemLQwvDOFbap9F4wrP9Cw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762994622; c=relaxed/simple; bh=CqInFrBaKchBNEHG/Ro0YLP1E73335mzqEPzKeUi6b4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JBl9BaaguL8nLp/naajoy68XU+tbt3Df+/7pG3f9zYF+R9VVQZ279STeWBc1bqKJtZ+6kKXN4AfmqWqO5Zd2/hl6z84PeLnLrhDVBiT4+wv06WYUKDkLlFSiu2bfh7xUUL/umjCIapq7w3/RT42uvn50rQn/E72fDtI8QVYcdjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JlO/r7Cx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JlO/r7Cx" Received: by smtp.kernel.org (Postfix) with ESMTPS id E0E5CC2BCB7; Thu, 13 Nov 2025 00:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762994622; bh=CqInFrBaKchBNEHG/Ro0YLP1E73335mzqEPzKeUi6b4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JlO/r7Cx1UBHu/+nCR5M6M99Z/CIXyva3iUie+1Fe78Po5XBJ2qZLXXg18Id+TO+J 4EYx+uCUhStqOMgzFVjAb/7geAExX20WE75AXElMxTbYcu/BR1INmP5xBZQSfbOE0J bbJTaNnOT8BRTsUgcAEobNMQZYQ6KHuA9Wxn/y3WDOhYUAmZ9DRZmsRAvf3F+TcbIq KWjZVBQJI9IOBhs6viOM7ggoI18Dypt2Y78CALny/PxTEZZKEpMzzSIvZP+3AZvo0T yEY9ZfNVFWwlLydFCef8Ql+DKR5FYp7o13XrshXbtRwJlPL4aXiyUHY+Tnt0Fza4eZ lLL8uRBQPQDTQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7DE0CD4F2D; Thu, 13 Nov 2025 00:43:41 +0000 (UTC) From: Deepak Gupta via B4 Relay Date: Wed, 12 Nov 2025 16:43:01 -0800 Subject: [PATCH v23 03/28] riscv: zicfiss / zicfilp enumeration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251112-v5_user_cfi_series-v23-3-b55691eacf4f@rivosinc.com> References: <20251112-v5_user_cfi_series-v23-0-b55691eacf4f@rivosinc.com> In-Reply-To: <20251112-v5_user_cfi_series-v23-0-b55691eacf4f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762994618; l=3576; i=debug@rivosinc.com; s=20251023; h=from:subject:message-id; bh=taPijq5zqeNuOB2Z6LTam5E9/MI20PvhyLXut1PkwcM=; b=Z4eC5Y3hzcpETeoJH9MnYdZa3a1VYcQrqMeJHdm7BsJdI8PpiUTqKiCbevMD2eWdxODTQN/lA vl1G3BtQa8ZCqCMVzgPxCz0RNDiqmWJD6/SO9jwjUlVoI80mB++H8xc X-Developer-Key: i=debug@rivosinc.com; a=ed25519; pk=O37GQv1thBhZToXyQKdecPDhtWVbEDRQ0RIndijvpjk= X-Endpoint-Received: by B4 Relay for debug@rivosinc.com/20251023 with auth_id=553 X-Original-From: Deepak Gupta Reply-To: debug@rivosinc.com From: Deepak Gupta This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature bitmap. Furthermore this patch adds detection utility functions to return whether shadow stack or landing pads are supported by cpu. Reviewed-by: Zong Li Reviewed-by: Alexandre Ghiti Signed-off-by: Deepak Gupta Tested-by: Andreas Korb --- arch/riscv/include/asm/cpufeature.h | 12 ++++++++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 22 ++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index fbd0e4306c93..481f483ebf15 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -150,4 +150,16 @@ static __always_inline bool riscv_cpu_has_extension_un= likely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } =20 +static inline bool cpu_supports_shadow_stack(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFISS)); +} + +static inline bool cpu_supports_indirect_br_lp_instr(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFILP)); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index affd63e11b0a..7c4619a6d70d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -106,6 +106,8 @@ #define RISCV_ISA_EXT_ZAAMO 97 #define RISCV_ISA_EXT_ZALRSC 98 #define RISCV_ISA_EXT_ZICBOP 99 +#define RISCV_ISA_EXT_ZICFILP 100 +#define RISCV_ISA_EXT_ZICFISS 101 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 67b59699357d..17b9e77bafc3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -274,6 +274,24 @@ static int riscv_ext_svadu_validate(const struct riscv= _isa_ext_data *data, return 0; } =20 +static int riscv_cfilp_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) + return -EINVAL; + + return 0; +} + +static int riscv_cfiss_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) + return -EINVAL; + + return 0; +} + static const unsigned int riscv_a_exts[] =3D { RISCV_ISA_EXT_ZAAMO, RISCV_ISA_EXT_ZALRSC, @@ -461,6 +479,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_x= linuxenvcfg_exts, + riscv_cfilp_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_x= linuxenvcfg_exts, + riscv_cfiss_validate), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), --=20 2.43.0