From nobody Wed Dec 10 20:12:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C2052E1C4E; Thu, 13 Nov 2025 00:43:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762994625; cv=none; b=J51IGQc4evvszhtcTd7EJcsjsok8CGH66UZIrwuLqJAyawaQJh91h3gAwmr04XwqicA7Mz8kD5uCDu7PFIGD6mH5cuvMmf6dFCj89ulGvOke31juXcpVydOoP1mqpeTD/XKWIrOHU4vzP0e6MjwNW03XytkxrfrEK8px40ZbM9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762994625; c=relaxed/simple; bh=vMyk0DvBkufLwEJ3yIeuejYgqx65+1ZyPmH4BVNHQa4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hnsZpYzm18/p1dL5Bj+R9KxmPtdZnLOYmIqhUqF9Fwt3YqfXAOK0Lqpqv3irYYTBWr7cCwDbfj5ab4UuDVc0AHQzJUphj+ND0FB5TyRd3z/0XCU52RTC3BsiIYYIXzQhGI7mir0A0O1U4Sho2nYKgkRhW5NkdbsIsEbDiVBTyPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JlVTn3n0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JlVTn3n0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 182DCC2BCF6; Thu, 13 Nov 2025 00:43:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762994624; bh=vMyk0DvBkufLwEJ3yIeuejYgqx65+1ZyPmH4BVNHQa4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JlVTn3n0T63UYSupSMoXqX5e2wH1sMYYlk+xpMFpTvZrlE6dSaRZ5Ewl0WR6jUF3b BLkiwPIuNJ8XgIaveMXNCRAMaqHmt2MXVndODJygicB/fA2vstUQIvGWFuygEQOhfi oI7jUDXBAFE9eCJlFs4YWFyADgs7G3bvyDMkBLS0KtT+1Mrc+IxPhSbmnyoceSoFZw UBIswKNZ3jeCTUzy8LOww20BYiwG++TY+QFxpfReCO3Bm2zgrcYYDct1P5HLMo1Oep jNEKXnOH2lDWx1FL1d4EnP4/ijWf/nlSxCP6sJkSw4DaNSXGhnWQPz0rf+ROPPMRix VEuuFATR3OeLw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8B6BCD342D; Thu, 13 Nov 2025 00:43:43 +0000 (UTC) From: Deepak Gupta via B4 Relay Date: Wed, 12 Nov 2025 16:43:23 -0800 Subject: [PATCH v23 25/28] riscv: create a config for shadow stack and landing pad instr support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251112-v5_user_cfi_series-v23-25-b55691eacf4f@rivosinc.com> References: <20251112-v5_user_cfi_series-v23-0-b55691eacf4f@rivosinc.com> In-Reply-To: <20251112-v5_user_cfi_series-v23-0-b55691eacf4f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762994618; l=2381; i=debug@rivosinc.com; s=20251023; h=from:subject:message-id; bh=8xXhGOHwnAnDsfTny7atQO4X4Ig8h+BkYqQGslWOtL0=; b=oVLei2Wb2IxpVhKAOsRM4E9JUd7n7tPRxHysa4C+j49eH1Nn69+BaLEL7Lr+py9efK3eWyj+U vPx2nJT9OmTBExUMIChjBE5eZB7shcypJVuT2lRx3BdyOWa4maKRdHl X-Developer-Key: i=debug@rivosinc.com; a=ed25519; pk=O37GQv1thBhZToXyQKdecPDhtWVbEDRQ0RIndijvpjk= X-Endpoint-Received: by B4 Relay for debug@rivosinc.com/20251023 with auth_id=553 X-Original-From: Deepak Gupta Reply-To: debug@rivosinc.com From: Deepak Gupta This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will support cpu assisted user mode cfi. If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`, `ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv. Reviewed-by: Zong Li Signed-off-by: Deepak Gupta Tested-by: Andreas Korb --- arch/riscv/Kconfig | 22 ++++++++++++++++++++++ arch/riscv/configs/hardening.config | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0c6038dc5dfd..f5574c6f66d8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1146,6 +1146,28 @@ config RANDOMIZE_BASE =20 If unsure, say N. =20 +config RISCV_USER_CFI + def_bool y + bool "riscv userspace control flow integrity" + depends on 64BIT && \ + $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zicfiss_zicfilp -fcf-protectio= n=3Dfull) + depends on RISCV_ALTERNATIVE + select RISCV_SBI + select ARCH_HAS_USER_SHADOW_STACK + select ARCH_USES_HIGH_VMA_FLAGS + select DYNAMIC_SIGFRAME + help + Provides CPU assisted control flow integrity to userspace tasks. + Control flow integrity is provided by implementing shadow stack for + backward edge and indirect branch tracking for forward edge in program. + Shadow stack protection is a hardware feature that detects function + return address corruption. This helps mitigate ROP attacks. + Indirect branch tracking enforces that all indirect branches must land + on a landing pad instruction else CPU will fault. This mitigates against + JOP / COP attacks. Applications must be enabled to use it, and old user- + space does not get protection "for free". + default y. + endmenu # "Kernel features" =20 menu "Boot options" diff --git a/arch/riscv/configs/hardening.config b/arch/riscv/configs/harde= ning.config new file mode 100644 index 000000000000..089f4cee82f4 --- /dev/null +++ b/arch/riscv/configs/hardening.config @@ -0,0 +1,4 @@ +# RISCV specific kernel hardening options + +# Enable control flow integrity support for usermode. +CONFIG_RISCV_USER_CFI=3Dy --=20 2.43.0