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To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 26 ++++++++++++ arch/arm/boot/dts/st/stm32mp151.dtsi | 29 +++++++++++++ arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++ arch/arm/boot/dts/st/stm32mp157a-dk1.dts | 43 +++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 43 +++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++ arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 60 +++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 31 ++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 36 ++++++++++++++++ 9 files changed, 296 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/s= t/stm32mp15-scmi.dtsi index 98552fe45d4e..c58d81f505be 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -13,6 +13,7 @@ optee: optee { method =3D "smc"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 scmi: scmi { @@ -20,6 +21,7 @@ scmi: scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-some-ram; =20 scmi_clk: protocol@14 { reg =3D <0x14>; @@ -64,6 +66,26 @@ scmi_usb33: regulator@2 { }; }; =20 +&iwdg2 { + bootph-all; +}; + +<dc { + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&rcc { + bootph-all; +}; + ®11 { status =3D "disabled"; }; @@ -72,6 +94,10 @@ ®18 { status =3D "disabled"; }; =20 +&scmi { + bootph-some-ram; +}; + &usb33 { status =3D "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index b1b568dfd126..7abee7ce0580 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -33,6 +33,7 @@ arm-pmu { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-some-ram; }; =20 intc: interrupt-controller@a0021000 { @@ -54,34 +55,41 @@ timer { }; =20 clocks { + bootph-all; + clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <24000000>; + bootph-all; }; =20 clk_hsi: clk-hsi { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <64000000>; + bootph-all; }; =20 clk_lse: clk-lse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32768>; + bootph-all; }; =20 clk_lsi: clk-lsi { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32000>; + bootph-all; }; =20 clk_csi: clk-csi { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <4000000>; + bootph-all; }; }; =20 @@ -122,6 +130,7 @@ soc { #size-cells =3D <1>; interrupt-parent =3D <&intc>; ranges; + bootph-all; =20 ipcc: mailbox@4c001000 { compatible =3D "st,stm32mp1-ipcc"; @@ -142,11 +151,13 @@ rcc: rcc@50000000 { reg =3D <0x50000000 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + bootph-all; }; =20 pwr_regulators: pwr@50001000 { compatible =3D "st,stm32mp1,pwr-reg"; reg =3D <0x50001000 0x10>; + bootph-all; =20 reg11: reg11 { regulator-name =3D "reg11"; @@ -354,6 +365,7 @@ ltdc: display-controller@5a001000 { clocks =3D <&rcc LTDC_PX>; clock-names =3D "lcd"; resets =3D <&rcc LTDC_R>; + bootph-some-ram; status =3D "disabled"; }; =20 @@ -364,6 +376,7 @@ iwdg2: watchdog@5a002000 { clock-names =3D "pclk", "lsi"; interrupts-extended =3D <&exti 46 IRQ_TYPE_LEVEL_HIGH>; wakeup-source; + bootph-all; status =3D "disabled"; }; =20 @@ -404,6 +417,8 @@ bsec: efuse@5c005000 { reg =3D <0x5c005000 0x400>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; + part_number_otp: part-number-otp@4 { reg =3D <0x4 0x1>; }; @@ -1876,6 +1891,7 @@ pinctrl: pinctrl@50002000 { ranges =3D <0 0x50002000 0xa400>; interrupt-parent =3D <&exti>; st,syscfg =3D <&exti 0x60 0xff>; + bootph-all; =20 gpioa: gpio@50002000 { gpio-controller; @@ -1885,6 +1901,7 @@ gpioa: gpio@50002000 { reg =3D <0x0 0x400>; clocks =3D <&rcc GPIOA>; st,bank-name =3D "GPIOA"; + bootph-all; status =3D "disabled"; }; =20 @@ -1896,6 +1913,7 @@ gpiob: gpio@50003000 { reg =3D <0x1000 0x400>; clocks =3D <&rcc GPIOB>; st,bank-name =3D "GPIOB"; + bootph-all; status =3D "disabled"; }; =20 @@ -1907,6 +1925,7 @@ gpioc: gpio@50004000 { reg =3D <0x2000 0x400>; clocks =3D <&rcc GPIOC>; st,bank-name =3D "GPIOC"; + bootph-all; status =3D "disabled"; }; =20 @@ -1918,6 +1937,7 @@ gpiod: gpio@50005000 { reg =3D <0x3000 0x400>; clocks =3D <&rcc GPIOD>; st,bank-name =3D "GPIOD"; + bootph-all; status =3D "disabled"; }; =20 @@ -1929,6 +1949,7 @@ gpioe: gpio@50006000 { reg =3D <0x4000 0x400>; clocks =3D <&rcc GPIOE>; st,bank-name =3D "GPIOE"; + bootph-all; status =3D "disabled"; }; =20 @@ -1940,6 +1961,7 @@ gpiof: gpio@50007000 { reg =3D <0x5000 0x400>; clocks =3D <&rcc GPIOF>; st,bank-name =3D "GPIOF"; + bootph-all; status =3D "disabled"; }; =20 @@ -1951,6 +1973,7 @@ gpiog: gpio@50008000 { reg =3D <0x6000 0x400>; clocks =3D <&rcc GPIOG>; st,bank-name =3D "GPIOG"; + bootph-all; status =3D "disabled"; }; =20 @@ -1962,6 +1985,7 @@ gpioh: gpio@50009000 { reg =3D <0x7000 0x400>; clocks =3D <&rcc GPIOH>; st,bank-name =3D "GPIOH"; + bootph-all; status =3D "disabled"; }; =20 @@ -1973,6 +1997,7 @@ gpioi: gpio@5000a000 { reg =3D <0x8000 0x400>; clocks =3D <&rcc GPIOI>; st,bank-name =3D "GPIOI"; + bootph-all; status =3D "disabled"; }; =20 @@ -1984,6 +2009,7 @@ gpioj: gpio@5000b000 { reg =3D <0x9000 0x400>; clocks =3D <&rcc GPIOJ>; st,bank-name =3D "GPIOJ"; + bootph-all; status =3D "disabled"; }; =20 @@ -1995,6 +2021,7 @@ gpiok: gpio@5000c000 { reg =3D <0xa000 0x400>; clocks =3D <&rcc GPIOK>; st,bank-name =3D "GPIOK"; + bootph-all; status =3D "disabled"; }; }; @@ -2006,6 +2033,7 @@ pinctrl_z: pinctrl@54004000 { ranges =3D <0 0x54004000 0x400>; interrupt-parent =3D <&exti>; st,syscfg =3D <&exti 0x60 0xff>; + bootph-all; =20 gpioz: gpio@54004000 { gpio-controller; @@ -2016,6 +2044,7 @@ gpioz: gpio@54004000 { clocks =3D <&rcc GPIOZ>; st,bank-name =3D "GPIOZ"; st,bank-ioport =3D <11>; + bootph-all; status =3D "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157a-dk1-scmi.dts index 847b360f02fc..f721c398e576 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -85,3 +85,17 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/s= t/stm32mp157a-dk1.dts index 0da3667ab1e0..c4581e28504a 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts @@ -23,3 +23,46 @@ chosen { stdout-path =3D "serial0:115200n8"; }; }; + +&i2c4 { + bootph-all; +}; + +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&pmic { + bootph-all; +}; + +&sdmmc1 { + bootph-pre-ram; +}; + +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157c-dk2.dts index 1ec3b8f2faa9..4fc670bb4cb0 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -79,6 +79,17 @@ touchscreen@38 { }; }; =20 +&i2c4 { + bootph-all; +}; + +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + <dc { status =3D "okay"; =20 @@ -93,6 +104,10 @@ ltdc_ep1_out: endpoint@1 { }; }; =20 +&pmic { + bootph-all; +}; + &rtc { pinctrl-names =3D "default"; pinctrl-0 =3D <&rtc_rsvd_pins_a>; @@ -103,6 +118,20 @@ rtc_lsco_pins_a: rtc-lsco-0 { }; }; =20 +&sdmmc1 { + bootph-pre-ram; +}; + +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + /* Wifi */ &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -127,6 +156,20 @@ brcmf: wifi@1 { }; }; =20 +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + /* Bluetooth */ &usart2 { pinctrl-names =3D "default", "sleep", "idle"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ed1-scmi.dts index 6f27d794d270..00d4855f9a85 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -90,3 +90,17 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ed1.dts index f6c478dbd041..f63a3d68d2b4 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -168,7 +168,9 @@ &i2c4 { i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; clock-frequency =3D <400000>; + bootph-all; status =3D "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; @@ -179,6 +181,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; status =3D "okay"; =20 regulators { @@ -314,6 +317,13 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; @@ -365,9 +375,30 @@ &sdmmc1 { sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-ddr50; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; @@ -381,9 +412,27 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &timers6 { status =3D "okay"; /* spare dmas for other usage */ @@ -399,11 +448,22 @@ &uart4 { pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { vbus-supply =3D <&vbus_otg>; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ev1-scmi.dts index 6ae391bffee5..802a492f2ed8 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -77,6 +77,37 @@ &optee { interrupts =3D ; }; =20 +&qspi { + bootph-pre-ram; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &rcc { compatible =3D "st,stm32mp1-rcc-secure", "syscon"; clock-names =3D "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ev1.dts index 8f99c30f1af1..879436cbb72d 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -262,6 +262,7 @@ &qspi_bk2_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -283,6 +284,41 @@ flash1: flash@1 { }; }; =20 +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; --=20 2.43.0