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To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32429i-eval.dts | 11 +++++++++++ arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 12 ++++++++++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 11 +++++++++++ arch/arm/boot/dts/st/stm32f429.dtsi | 9 +++++++++ arch/arm/boot/dts/st/stm32f469-disco.dts | 12 ++++++++++++ 5 files changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st= /stm32429i-eval.dts index afa417b34b25..3b6151fcb070 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -312,6 +312,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -326,6 +327,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "host"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/= st/stm32f4-pinctrl.dtsi index 3bb812d6399e..bcaed4618738 100644 --- a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi @@ -51,6 +51,7 @@ pinctrl: pinctrl@40020000 { ranges =3D <0 0x40020000 0x3000>; interrupt-parent =3D <&exti>; st,syscfg =3D <&syscfg 0x8>; + bootph-all; =20 gpioa: gpio@40020000 { gpio-controller; @@ -60,6 +61,7 @@ gpioa: gpio@40020000 { reg =3D <0x0 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; st,bank-name =3D "GPIOA"; + bootph-all; }; =20 gpiob: gpio@40020400 { @@ -70,6 +72,7 @@ gpiob: gpio@40020400 { reg =3D <0x400 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; st,bank-name =3D "GPIOB"; + bootph-all; }; =20 gpioc: gpio@40020800 { @@ -80,6 +83,7 @@ gpioc: gpio@40020800 { reg =3D <0x800 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; st,bank-name =3D "GPIOC"; + bootph-all; }; =20 gpiod: gpio@40020c00 { @@ -90,6 +94,7 @@ gpiod: gpio@40020c00 { reg =3D <0xc00 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; st,bank-name =3D "GPIOD"; + bootph-all; }; =20 gpioe: gpio@40021000 { @@ -100,6 +105,7 @@ gpioe: gpio@40021000 { reg =3D <0x1000 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; st,bank-name =3D "GPIOE"; + bootph-all; }; =20 gpiof: gpio@40021400 { @@ -110,6 +116,7 @@ gpiof: gpio@40021400 { reg =3D <0x1400 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; st,bank-name =3D "GPIOF"; + bootph-all; }; =20 gpiog: gpio@40021800 { @@ -120,6 +127,7 @@ gpiog: gpio@40021800 { reg =3D <0x1800 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; st,bank-name =3D "GPIOG"; + bootph-all; }; =20 gpioh: gpio@40021c00 { @@ -130,6 +138,7 @@ gpioh: gpio@40021c00 { reg =3D <0x1c00 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; st,bank-name =3D "GPIOH"; + bootph-all; }; =20 gpioi: gpio@40022000 { @@ -140,6 +149,7 @@ gpioi: gpio@40022000 { reg =3D <0x2000 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; st,bank-name =3D "GPIOI"; + bootph-all; }; =20 gpioj: gpio@40022400 { @@ -150,6 +160,7 @@ gpioj: gpio@40022400 { reg =3D <0x2400 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; st,bank-name =3D "GPIOJ"; + bootph-all; }; =20 gpiok: gpio@40022800 { @@ -160,6 +171,7 @@ gpiok: gpio@40022800 { reg =3D <0x2800 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; st,bank-name =3D "GPIOK"; + bootph-all; }; =20 usart1_pins_a: usart1-0 { diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/s= t/stm32f429-disco.dts index a3cb4aabdd5a..39a80a9caa5f 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -209,6 +209,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -223,6 +224,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { compatible =3D "st,stm32f4x9-fsotg"; dr_mode =3D "host"; diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm= 32f429.dtsi index ad91b74ddd0d..51c931f7b9d5 100644 --- a/arch/arm/boot/dts/st/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -54,16 +54,20 @@ / { #size-cells =3D <1>; =20 clocks { + bootph-all; + clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; =20 clk_lse: clk-lse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32768>; + bootph-all; }; =20 clk_lsi: clk-lsi { @@ -76,10 +80,12 @@ clk_i2s_ckin: i2s-ckin { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; }; =20 soc { + bootph-all; romem: efuse@1fff7800 { compatible =3D "st,stm32f4-otp"; reg =3D <0x1fff7800 0x400>; @@ -580,6 +586,7 @@ syscfg: syscon@40013800 { compatible =3D "st,stm32-syscfg", "syscon"; reg =3D <0x40013800 0x400>; clocks =3D <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>; + bootph-all; }; =20 exti: interrupt-controller@40013c00 { @@ -666,6 +673,7 @@ spi6: spi@40015400 { pwrcfg: power-config@40007000 { compatible =3D "st,stm32-power-config", "syscon"; reg =3D <0x40007000 0x400>; + bootph-all; }; =20 ltdc: display-controller@40016800 { @@ -694,6 +702,7 @@ rcc: rcc@40023800 { st,syscfg =3D <&pwrcfg>; assigned-clocks =3D <&rcc 1 CLK_HSE_RTC>; assigned-clock-rates =3D <1000000>; + bootph-all; }; =20 dma1: dma-controller@40026000 { diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/s= t/stm32f469-disco.dts index 8a4f8ddd083d..de025a385e9e 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -169,6 +169,7 @@ dsi_panel_in: endpoint { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -225,6 +226,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; 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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 10:47:07.3196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9befabfd-f8ee-43c5-012a-08de21d8d341 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009BA0.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR10MB9035 X-Proofpoint-GUID: gtf4iG0_ktEElvSfopwbgsZba1dyd9a9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA4NiBTYWx0ZWRfXxPH3Tjkdb32v ER1uEV3UEzkFkIzYrjznpfHAVbq7RFsfWF+i63COHeJYWqoTBcZJc3YMDFekqAh04Qc2hbpm4FN Csu+U5yjOc8TcGrJD2AlghgnL8gHq+u77AX24RIOjPcvNf05OfM7IbGnkBxrWIJyTrS98LYDwBh 8a10bqY1/QdK480T4kM4CBIxFhM7rCaqVxpV/Zb1ETWSmczVPHTlelIif0vp29Ha6bmRQ5DujKR 687nb/YLwDWohfNG7paYO0Y0DvbMoBNuSynBurRwPTtWWDFkQgL+cgz3H0OR7nxMUTy0Vhb5PVl VRGYX8+MqSEBIj1f+C8daqePXyAuP0AN49B6pVt+PgrpglzsNyxIBBMLyEr/gyJKA53hesjne1+ PInLkOw86BdOej155jikXr/nXfjcXQ== X-Proofpoint-ORIG-GUID: gtf4iG0_ktEElvSfopwbgsZba1dyd9a9 X-Authority-Analysis: v=2.4 cv=a849NESF c=1 sm=1 tr=0 ts=691465ae cx=c_pps a=pNXGupngiSMufF7CtLwx6w==:117 a=d6reE3nDawwanmLcZTMRXA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=XWp4PHTOCikA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=8b9GpE9nAAAA:8 a=fTQ55MeeFdhIrGqxLO4A:9 a=QEXdDO2ut3YA:10 a=T3LWEMljR5ZiDmsYVIUa:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 impostorscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120086 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 ++++++++++ arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 11 +++++++++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 12 ++++++++++++ arch/arm/boot/dts/st/stm32f746.dtsi | 5 +++++ arch/arm/boot/dts/st/stm32f769-disco.dts | 12 ++++++++++++ 5 files changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st= /stm32746g-eval.dts index e9ac37b6eca0..26c5796a81fb 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -213,6 +213,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/= st/stm32f7-pinctrl.dtsi index 97fc3fb5a9ca..6b01c3c84272 100644 --- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -24,6 +24,7 @@ gpioa: gpio@40020000 { reg =3D <0x0 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name =3D "GPIOA"; + bootph-all; }; =20 gpiob: gpio@40020400 { @@ -34,6 +35,7 @@ gpiob: gpio@40020400 { reg =3D <0x400 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name =3D "GPIOB"; + bootph-all; }; =20 gpioc: gpio@40020800 { @@ -44,6 +46,7 @@ gpioc: gpio@40020800 { reg =3D <0x800 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name =3D "GPIOC"; + bootph-all; }; =20 gpiod: gpio@40020c00 { @@ -54,6 +57,7 @@ gpiod: gpio@40020c00 { reg =3D <0xc00 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name =3D "GPIOD"; + bootph-all; }; =20 gpioe: gpio@40021000 { @@ -64,6 +68,7 @@ gpioe: gpio@40021000 { reg =3D <0x1000 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name =3D "GPIOE"; + bootph-all; }; =20 gpiof: gpio@40021400 { @@ -74,6 +79,7 @@ gpiof: gpio@40021400 { reg =3D <0x1400 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name =3D "GPIOF"; + bootph-all; }; =20 gpiog: gpio@40021800 { @@ -84,6 +90,7 @@ gpiog: gpio@40021800 { reg =3D <0x1800 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name =3D "GPIOG"; + bootph-all; }; =20 gpioh: gpio@40021c00 { @@ -94,6 +101,7 @@ gpioh: gpio@40021c00 { reg =3D <0x1c00 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name =3D "GPIOH"; + bootph-all; }; =20 gpioi: gpio@40022000 { @@ -104,6 +112,7 @@ gpioi: gpio@40022000 { reg =3D <0x2000 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name =3D "GPIOI"; + bootph-all; }; =20 gpioj: gpio@40022400 { @@ -114,6 +123,7 @@ gpioj: gpio@40022400 { reg =3D <0x2400 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name =3D "GPIOJ"; + bootph-all; }; =20 gpiok: gpio@40022800 { @@ -124,6 +134,7 @@ gpiok: gpio@40022800 { reg =3D <0x2800 0x400>; clocks =3D <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name =3D "GPIOK"; + bootph-all; }; =20 cec_pins_a: cec-0 { diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/s= t/stm32f746-disco.dts index b57dbdce2f40..9545b14d77c3 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -169,6 +169,7 @@ touchscreen@38 { <dc { pinctrl-0 =3D <<dc_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; =20 port { @@ -207,6 +208,17 @@ &usart1 { status =3D "okay"; }; =20 + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm= 32f746.dtsi index 208f8c6dfc9d..b0f012de759c 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -54,6 +54,7 @@ clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; =20 clk-lse { @@ -76,6 +77,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; =20 soc { + bootph-all; timers2: timers@40000000 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -149,6 +151,7 @@ timers5: timers@40000c00 { reg =3D <0x40000C00 0x400>; clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; clock-names =3D "int"; + bootph-all; status =3D "disabled"; =20 pwm { @@ -645,6 +648,7 @@ ltdc: display-controller@40016800 { pwrcfg: power-config@40007000 { compatible =3D "st,stm32-power-config", "syscon"; reg =3D <0x40007000 0x400>; + bootph-all; }; =20 crc: crc@40023000 { @@ -663,6 +667,7 @@ rcc: rcc@40023800 { st,syscfg =3D <&pwrcfg>; assigned-clocks =3D <&rcc 1 CLK_HSE_RTC>; assigned-clock-rates =3D <1000000>; + bootph-all; }; =20 dma1: dma-controller@40026000 { diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index 535cfdc4681c..539517c7991e 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -133,6 +133,7 @@ &clk_hse { &dsi { #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 ports { @@ -178,6 +179,7 @@ &i2c1 { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -221,6 +223,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; --=20 2.43.0 From nobody Mon Feb 9 13:05:28 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB402D8DB1; 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To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32h743.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm= 32h743.dtsi index 2f19cfbc57ad..790e4558c905 100644 --- a/arch/arm/boot/dts/st/stm32h743.dtsi +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -50,22 +50,26 @@ / { #size-cells =3D <1>; =20 clocks { + bootph-all; clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; =20 clk_lse: clk-lse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32768>; + bootph-all; }; =20 clk_i2s: i2s_ckin { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; }; =20 @@ -75,6 +79,7 @@ timer5: timer@40000c00 { reg =3D <0x40000c00 0x400>; interrupts =3D <50>; clocks =3D <&rcc TIM5_CK>; + bootph-all; }; =20 lptimer1: timer@40002400 { @@ -547,11 +552,13 @@ rcc: reset-clock-controller@58024400 { #reset-cells =3D <1>; clocks =3D <&clk_hse>, <&clk_lse>, <&clk_i2s>; st,syscfg =3D <&pwrcfg>; + bootph-all; }; =20 pwrcfg: power-config@58024800 { compatible =3D "st,stm32-power-config", "syscon"; reg =3D <0x58024800 0x400>; + bootph-all; }; =20 adc_3: adc@58026000 { @@ -596,6 +603,7 @@ pinctrl: pinctrl@58020000 { ranges =3D <0 0x58020000 0x3000>; interrupt-parent =3D <&exti>; st,syscfg =3D <&syscfg 0x8>; + bootph-all; =20 gpioa: gpio@58020000 { gpio-controller; @@ -607,6 +615,7 @@ gpioa: gpio@58020000 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 0 16>; + bootph-all; }; =20 gpiob: gpio@58020400 { @@ -619,6 +628,7 @@ gpiob: gpio@58020400 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 16 16>; + bootph-all; }; =20 gpioc: gpio@58020800 { @@ -631,6 +641,7 @@ gpioc: gpio@58020800 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 32 16>; + bootph-all; }; =20 gpiod: gpio@58020c00 { @@ -643,6 +654,7 @@ gpiod: gpio@58020c00 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 48 16>; + bootph-all; }; =20 gpioe: gpio@58021000 { @@ -655,6 +667,7 @@ gpioe: gpio@58021000 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 64 16>; + bootph-all; }; =20 gpiof: gpio@58021400 { @@ -667,6 +680,7 @@ gpiof: gpio@58021400 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 80 16>; + bootph-all; }; =20 gpiog: gpio@58021800 { @@ -679,6 +693,7 @@ gpiog: gpio@58021800 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 96 16>; + bootph-all; }; =20 gpioh: gpio@58021c00 { @@ -691,6 +706,7 @@ gpioh: gpio@58021c00 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 112 16>; + bootph-all; }; =20 gpioi: gpio@58022000 { @@ -703,6 +719,7 @@ gpioi: gpio@58022000 { #interrupt-cells =3D <2>; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 128 16>; + bootph-all; }; =20 gpioj: gpio@58022400 { @@ -715,6 +732,7 @@ gpioj: gpio@58022400 { #interrupt-cells =3D <2>; ngpios =3D <16>; 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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 10:47:07.8450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5eeaee40-68c5-4f90-b43a-08de21d8d38f X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009BA0.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR10MB5980 X-Proofpoint-GUID: hPqdmMMl_R9yKjCGOlddvq3P4p0j_6X8 X-Authority-Analysis: v=2.4 cv=LaQxKzfi c=1 sm=1 tr=0 ts=691465b3 cx=c_pps a=cyhFtQRhg4USMAHCudA+lA==:117 a=d6reE3nDawwanmLcZTMRXA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=XWp4PHTOCikA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=8b9GpE9nAAAA:8 a=Ml00H7WYq3aDj7q0dhMA:9 a=QEXdDO2ut3YA:10 a=T3LWEMljR5ZiDmsYVIUa:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-ORIG-GUID: hPqdmMMl_R9yKjCGOlddvq3P4p0j_6X8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA4NiBTYWx0ZWRfXwdpm/0wGYjU6 KlzPS+pIUkuIF8cahByGExLg3cWw2bUXfbrRSA2/a3p1Sw/uYmGjIEY/HKGmBPVUA16/ZFNbDt6 AVmuYjdR476v+X2s7iH3M2bxTv3dalZAsRgNFlItRJsj5IcuuYBRxduConJj4LUZvTqMHOv+eHS 2p4XAz8sh4A9bU2vrf5AyIUSydFO8gyfI7/zZhRbiuLBTy2gdMGaH4fBJ1vCaC6WCf6PPL6BQCr Z+0kmebCksshW/p9wZv4gsd7+PMlpXyQ4EsQ9lmcU26hBU1jVcS/6b0HQmciBfw9HVCn8lDkldG PTXMLaAOlD+GlpFiHW+hurzlJKgErRRKr9vY8rmOLRnMOe+s3nbly4JBPGBaTBM4xUV9ivp8/gP wvoim9pJlEN7PskLcePJPBlUomvrEw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120086 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp131.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 11 +++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index fd730aa37c22..26c3b5529582 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -35,6 +35,7 @@ optee { compatible =3D "linaro,optee-tz"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-all; }; =20 scmi: scmi { @@ -42,15 +43,18 @@ scmi: scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; =20 scmi_voltd: protocol@17 { @@ -88,6 +92,7 @@ intc: interrupt-controller@a0021000 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-some-ram; }; =20 timer { @@ -131,6 +136,7 @@ soc { #size-cells =3D <1>; interrupt-parent =3D <&intc>; ranges; + bootph-all; =20 timers2: timer@40000000 { #address-cells =3D <1>; @@ -791,6 +797,7 @@ rcc: rcc@50000000 { <&scmi_clk CK_SCMI_CSI>, <&scmi_clk CK_SCMI_LSE>, <&scmi_clk CK_SCMI_LSI>; + bootph-all; }; =20 pwr_regulators: pwr@50001000 { @@ -900,6 +907,7 @@ syscfg: syscon@50020000 { compatible =3D "st,stm32mp157-syscfg", "syscon"; reg =3D <0x50020000 0x400>; clocks =3D <&rcc SYSCFG>; + bootph-all; }; =20 lptimer4: timer@50023000 { @@ -1003,6 +1011,7 @@ iwdg2: watchdog@5a002000 { clocks =3D <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names =3D "pclk", "lsi"; status =3D "disabled"; + bootph-all; }; =20 rtc: rtc@5c004000 { @@ -1020,6 +1029,7 @@ bsec: efuse@5c005000 { reg =3D <0x5c005000 0x400>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 part_number_otp: part_number_otp@4 { reg =3D <0x4 0x2>; @@ -1646,6 +1656,7 @@ usbphyc: usbphyc@5a006000 { vdda1v8-supply =3D <&scmi_reg18>; access-controllers =3D <&etzpc 5>; status =3D "disabled"; + bootph-all; =20 usbphyc_port0: usb-phy@0 { #phy-cells =3D <0>; @@ -1670,6 +1681,7 @@ pinctrl: pinctrl@50002000 { ranges =3D <0 0x50002000 0x8400>; interrupt-parent =3D <&exti>; st,syscfg =3D <&exti 0x60 0xff>; + bootph-all; =20 gpioa: gpio@50002000 { gpio-controller; @@ -1681,6 +1693,7 @@ gpioa: gpio@50002000 { st,bank-name =3D "GPIOA"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 0 16>; + bootph-all; }; =20 gpiob: gpio@50003000 { @@ -1693,6 +1706,7 @@ gpiob: gpio@50003000 { st,bank-name =3D "GPIOB"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 16 16>; + bootph-all; }; =20 gpioc: gpio@50004000 { @@ -1705,6 +1719,7 @@ gpioc: gpio@50004000 { st,bank-name =3D "GPIOC"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 32 16>; + bootph-all; }; =20 gpiod: gpio@50005000 { @@ -1717,6 +1732,7 @@ gpiod: gpio@50005000 { st,bank-name =3D "GPIOD"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 48 16>; + bootph-all; }; =20 gpioe: gpio@50006000 { @@ -1729,6 +1745,7 @@ gpioe: gpio@50006000 { st,bank-name =3D "GPIOE"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 64 16>; + bootph-all; }; =20 gpiof: gpio@50007000 { @@ -1741,6 +1758,7 @@ gpiof: gpio@50007000 { st,bank-name =3D "GPIOF"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 80 16>; + bootph-all; }; =20 gpiog: gpio@50008000 { @@ -1753,6 +1771,7 @@ gpiog: gpio@50008000 { st,bank-name =3D "GPIOG"; ngpios =3D <16>; gpio-ranges =3D <&pinctrl 0 96 16>; + bootph-all; }; =20 gpioh: gpio@50009000 { @@ -1765,6 +1784,7 @@ gpioh: gpio@50009000 { st,bank-name =3D "GPIOH"; ngpios =3D <15>; gpio-ranges =3D <&pinctrl 0 112 15>; + bootph-all; }; =20 gpioi: gpio@5000a000 { @@ -1777,6 +1797,7 @@ gpioi: gpio@5000a000 { st,bank-name =3D "GPIOI"; ngpios =3D <8>; gpio-ranges =3D <&pinctrl 0 128 8>; + bootph-all; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st= /stm32mp135f-dk.dts index 9764a6bfa5b4..a05d458c9b37 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -517,9 +517,20 @@ &uart4 { pinctrl-2 =3D <&uart4_idle_pins_a>; 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To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 26 ++++++++++++ arch/arm/boot/dts/st/stm32mp151.dtsi | 29 +++++++++++++ arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++ arch/arm/boot/dts/st/stm32mp157a-dk1.dts | 43 +++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 43 +++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++ arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 60 +++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 31 ++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 36 ++++++++++++++++ 9 files changed, 296 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/s= t/stm32mp15-scmi.dtsi index 98552fe45d4e..c58d81f505be 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -13,6 +13,7 @@ optee: optee { method =3D "smc"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 scmi: scmi { @@ -20,6 +21,7 @@ scmi: scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-some-ram; =20 scmi_clk: protocol@14 { reg =3D <0x14>; @@ -64,6 +66,26 @@ scmi_usb33: regulator@2 { }; }; =20 +&iwdg2 { + bootph-all; +}; + +<dc { + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&rcc { + bootph-all; +}; + ®11 { status =3D "disabled"; }; @@ -72,6 +94,10 @@ ®18 { status =3D "disabled"; }; =20 +&scmi { + bootph-some-ram; +}; + &usb33 { status =3D "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index b1b568dfd126..7abee7ce0580 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -33,6 +33,7 @@ arm-pmu { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-some-ram; }; =20 intc: interrupt-controller@a0021000 { @@ -54,34 +55,41 @@ timer { }; =20 clocks { + bootph-all; + clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <24000000>; + bootph-all; }; =20 clk_hsi: clk-hsi { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <64000000>; + bootph-all; }; =20 clk_lse: clk-lse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32768>; + bootph-all; }; =20 clk_lsi: clk-lsi { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32000>; + bootph-all; }; =20 clk_csi: clk-csi { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <4000000>; + bootph-all; }; }; =20 @@ -122,6 +130,7 @@ soc { #size-cells =3D <1>; interrupt-parent =3D <&intc>; ranges; + bootph-all; =20 ipcc: mailbox@4c001000 { compatible =3D "st,stm32mp1-ipcc"; @@ -142,11 +151,13 @@ rcc: rcc@50000000 { reg =3D <0x50000000 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + bootph-all; }; =20 pwr_regulators: pwr@50001000 { compatible =3D "st,stm32mp1,pwr-reg"; reg =3D <0x50001000 0x10>; + bootph-all; =20 reg11: reg11 { regulator-name =3D "reg11"; @@ -354,6 +365,7 @@ ltdc: display-controller@5a001000 { clocks =3D <&rcc LTDC_PX>; clock-names =3D "lcd"; resets =3D <&rcc LTDC_R>; + bootph-some-ram; status =3D "disabled"; }; =20 @@ -364,6 +376,7 @@ iwdg2: watchdog@5a002000 { clock-names =3D "pclk", "lsi"; interrupts-extended =3D <&exti 46 IRQ_TYPE_LEVEL_HIGH>; wakeup-source; + bootph-all; status =3D "disabled"; }; =20 @@ -404,6 +417,8 @@ bsec: efuse@5c005000 { reg =3D <0x5c005000 0x400>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; + part_number_otp: part-number-otp@4 { reg =3D <0x4 0x1>; }; @@ -1876,6 +1891,7 @@ pinctrl: pinctrl@50002000 { ranges =3D <0 0x50002000 0xa400>; interrupt-parent =3D <&exti>; st,syscfg =3D <&exti 0x60 0xff>; + bootph-all; =20 gpioa: gpio@50002000 { gpio-controller; @@ -1885,6 +1901,7 @@ gpioa: gpio@50002000 { reg =3D <0x0 0x400>; clocks =3D <&rcc GPIOA>; st,bank-name =3D "GPIOA"; + bootph-all; status =3D "disabled"; }; =20 @@ -1896,6 +1913,7 @@ gpiob: gpio@50003000 { reg =3D <0x1000 0x400>; clocks =3D <&rcc GPIOB>; st,bank-name =3D "GPIOB"; + bootph-all; status =3D "disabled"; }; =20 @@ -1907,6 +1925,7 @@ gpioc: gpio@50004000 { reg =3D <0x2000 0x400>; clocks =3D <&rcc GPIOC>; st,bank-name =3D "GPIOC"; + bootph-all; status =3D "disabled"; }; =20 @@ -1918,6 +1937,7 @@ gpiod: gpio@50005000 { reg =3D <0x3000 0x400>; clocks =3D <&rcc GPIOD>; st,bank-name =3D "GPIOD"; + bootph-all; status =3D "disabled"; }; =20 @@ -1929,6 +1949,7 @@ gpioe: gpio@50006000 { reg =3D <0x4000 0x400>; clocks =3D <&rcc GPIOE>; st,bank-name =3D "GPIOE"; + bootph-all; status =3D "disabled"; }; =20 @@ -1940,6 +1961,7 @@ gpiof: gpio@50007000 { reg =3D <0x5000 0x400>; clocks =3D <&rcc GPIOF>; st,bank-name =3D "GPIOF"; + bootph-all; status =3D "disabled"; }; =20 @@ -1951,6 +1973,7 @@ gpiog: gpio@50008000 { reg =3D <0x6000 0x400>; clocks =3D <&rcc GPIOG>; st,bank-name =3D "GPIOG"; + bootph-all; status =3D "disabled"; }; =20 @@ -1962,6 +1985,7 @@ gpioh: gpio@50009000 { reg =3D <0x7000 0x400>; clocks =3D <&rcc GPIOH>; st,bank-name =3D "GPIOH"; + bootph-all; status =3D "disabled"; }; =20 @@ -1973,6 +1997,7 @@ gpioi: gpio@5000a000 { reg =3D <0x8000 0x400>; clocks =3D <&rcc GPIOI>; st,bank-name =3D "GPIOI"; + bootph-all; status =3D "disabled"; }; =20 @@ -1984,6 +2009,7 @@ gpioj: gpio@5000b000 { reg =3D <0x9000 0x400>; clocks =3D <&rcc GPIOJ>; st,bank-name =3D "GPIOJ"; + bootph-all; status =3D "disabled"; }; =20 @@ -1995,6 +2021,7 @@ gpiok: gpio@5000c000 { reg =3D <0xa000 0x400>; clocks =3D <&rcc GPIOK>; st,bank-name =3D "GPIOK"; + bootph-all; status =3D "disabled"; }; }; @@ -2006,6 +2033,7 @@ pinctrl_z: pinctrl@54004000 { ranges =3D <0 0x54004000 0x400>; interrupt-parent =3D <&exti>; st,syscfg =3D <&exti 0x60 0xff>; + bootph-all; =20 gpioz: gpio@54004000 { gpio-controller; @@ -2016,6 +2044,7 @@ gpioz: gpio@54004000 { clocks =3D <&rcc GPIOZ>; st,bank-name =3D "GPIOZ"; st,bank-ioport =3D <11>; + bootph-all; status =3D "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157a-dk1-scmi.dts index 847b360f02fc..f721c398e576 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -85,3 +85,17 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/s= t/stm32mp157a-dk1.dts index 0da3667ab1e0..c4581e28504a 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts @@ -23,3 +23,46 @@ chosen { stdout-path =3D "serial0:115200n8"; }; }; + +&i2c4 { + bootph-all; +}; + +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&pmic { + bootph-all; +}; + +&sdmmc1 { + bootph-pre-ram; +}; + +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157c-dk2.dts index 1ec3b8f2faa9..4fc670bb4cb0 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -79,6 +79,17 @@ touchscreen@38 { }; }; =20 +&i2c4 { + bootph-all; +}; + +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + <dc { status =3D "okay"; =20 @@ -93,6 +104,10 @@ ltdc_ep1_out: endpoint@1 { }; }; =20 +&pmic { + bootph-all; +}; + &rtc { pinctrl-names =3D "default"; pinctrl-0 =3D <&rtc_rsvd_pins_a>; @@ -103,6 +118,20 @@ rtc_lsco_pins_a: rtc-lsco-0 { }; }; =20 +&sdmmc1 { + bootph-pre-ram; +}; + +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + /* Wifi */ &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -127,6 +156,20 @@ brcmf: wifi@1 { }; }; =20 +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + /* Bluetooth */ &usart2 { pinctrl-names =3D "default", "sleep", "idle"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ed1-scmi.dts index 6f27d794d270..00d4855f9a85 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -90,3 +90,17 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ed1.dts index f6c478dbd041..f63a3d68d2b4 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -168,7 +168,9 @@ &i2c4 { i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; clock-frequency =3D <400000>; + bootph-all; status =3D "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; @@ -179,6 +181,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; status =3D "okay"; =20 regulators { @@ -314,6 +317,13 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; @@ -365,9 +375,30 @@ &sdmmc1 { sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-ddr50; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; @@ -381,9 +412,27 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &timers6 { status =3D "okay"; /* spare dmas for other usage */ @@ -399,11 +448,22 @@ &uart4 { pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { vbus-supply =3D <&vbus_otg>; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ev1-scmi.dts index 6ae391bffee5..802a492f2ed8 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -77,6 +77,37 @@ &optee { interrupts =3D ; }; =20 +&qspi { + bootph-pre-ram; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &rcc { compatible =3D "st,stm32mp1-rcc-secure", "syscon"; clock-names =3D "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ev1.dts index 8f99c30f1af1..879436cbb72d 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -262,6 +262,7 @@ &qspi_bk2_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x4000000>; 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To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 7 +++++++ arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 1 + arch/arm64/boot/dts/st/stm32mp231.dtsi | 22 ++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 11 +++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 27 ++++++++++++++++++++++++++- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 11 +++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 11 +++++++++++ 7 files changed, 89 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/s= t/stm32mp211.dtsi index bf888d60cd4f..81b6a71fc032 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -50,6 +50,7 @@ firmware { optee { compatible =3D "linaro,optee-tz"; method =3D "smc"; + bootph-all; }; =20 scmi: scmi { @@ -57,15 +58,18 @@ scmi: scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; }; }; @@ -73,6 +77,7 @@ scmi_reset: protocol@16 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-all; }; =20 timer { @@ -92,6 +97,7 @@ soc@0 { interrupt-parent =3D <&intc>; #address-cells =3D <1>; #size-cells =3D <2>; + bootph-all; =20 rifsc: bus@42080000 { compatible =3D "simple-bus"; @@ -100,6 +106,7 @@ rifsc: bus@42080000 { dma-ranges; #address-cells =3D <1>; #size-cells =3D <2>; + bootph-all; =20 usart2: serial@400e0000 { compatible =3D "st,stm32h7-uart"; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..bc366639744a 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -45,5 +45,6 @@ &arm_wdt { }; =20 &usart2 { + bootph-all; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 88e214d395ab..075b4419d3ae 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -57,6 +57,7 @@ optee: optee { method =3D "smc"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-all; }; =20 scmi { @@ -64,15 +65,18 @@ scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; =20 scmi_voltd: protocol@17 { @@ -114,6 +118,7 @@ scmi_vdda18adc: regulator@7 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-all; =20 cpu0_pd: power-domain-cpu0 { #power-domain-cells =3D <0>; @@ -146,6 +151,7 @@ soc@0 { interrupt-parent =3D <&intc>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 hpdma: dma-controller@40400000 { compatible =3D "st,stm32mp25-dma3"; @@ -223,6 +229,7 @@ rifsc: bus@42080000 { #address-cells =3D <1>; #size-cells =3D <1>; #access-controller-cells =3D <1>; + bootph-all; =20 i2s2: audio-controller@400b0000 { compatible =3D "st,stm32mp25-i2s"; @@ -760,6 +767,7 @@ bsec: efuse@44000000 { reg =3D <0x44000000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 part_number_otp@24 { reg =3D <0x24 0x4>; @@ -857,6 +865,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers =3D <&rifsc 156>; + bootph-all; }; =20 exti1: interrupt-controller@44220000 { @@ -955,6 +964,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible =3D "st,stm32mp23-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; + bootph-all; }; =20 pinctrl: pinctrl@44240000 { @@ -965,6 +975,7 @@ pinctrl: pinctrl@44240000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioa: gpio@44240000 { reg =3D <0x0 0x400>; @@ -974,6 +985,7 @@ gpioa: gpio@44240000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOA>; st,bank-name =3D "GPIOA"; + bootph-all; status =3D "disabled"; }; =20 @@ -985,6 +997,7 @@ gpiob: gpio@44250000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOB>; st,bank-name =3D "GPIOB"; + bootph-all; status =3D "disabled"; }; =20 @@ -996,6 +1009,7 @@ gpioc: gpio@44260000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOC>; st,bank-name =3D "GPIOC"; + bootph-all; status =3D "disabled"; }; =20 @@ -1007,6 +1021,7 @@ gpiod: gpio@44270000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOD>; st,bank-name =3D "GPIOD"; + bootph-all; status =3D "disabled"; }; =20 @@ -1018,6 +1033,7 @@ gpioe: gpio@44280000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOE>; st,bank-name =3D "GPIOE"; + bootph-all; status =3D "disabled"; }; =20 @@ -1029,6 +1045,7 @@ gpiof: gpio@44290000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOF>; st,bank-name =3D "GPIOF"; + bootph-all; status =3D "disabled"; }; =20 @@ -1040,6 +1057,7 @@ gpiog: gpio@442a0000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOG>; st,bank-name =3D "GPIOG"; + bootph-all; status =3D "disabled"; }; =20 @@ -1051,6 +1069,7 @@ gpioh: gpio@442b0000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOH>; st,bank-name =3D "GPIOH"; + bootph-all; status =3D "disabled"; }; =20 @@ -1062,6 +1081,7 @@ gpioi: gpio@442c0000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOI>; st,bank-name =3D "GPIOI"; + bootph-all; status =3D "disabled"; }; }; @@ -1084,6 +1104,7 @@ pinctrl_z: pinctrl@46200000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioz: gpio@46200000 { reg =3D <0 0x400>; @@ -1094,6 +1115,7 @@ gpioz: gpio@46200000 { clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name =3D "GPIOZ"; st,bank-ioport =3D <11>; + bootph-all; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp235f-dk.dts index c3e688068223..391494eda5e6 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -130,7 +130,18 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index a8e6e0f77b83..068720d49afa 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -66,6 +66,7 @@ optee: optee { method =3D "smc"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-all; }; =20 scmi { @@ -73,15 +74,18 @@ scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; =20 scmi_voltd: protocol@17 { @@ -142,6 +146,7 @@ v2m0: v2m@48090000 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-all; =20 CPU_PD0: power-domain-cpu0 { #power-domain-cells =3D <0>; @@ -174,7 +179,8 @@ soc@0 { #size-cells =3D <1>; interrupt-parent =3D <&intc>; ranges =3D <0x0 0x0 0x0 0x80000000>; - + bootph-all; +=09 hpdma: dma-controller@40400000 { compatible =3D "st,stm32mp25-dma3"; reg =3D <0x40400000 0x1000>; @@ -305,6 +311,7 @@ rifsc: bus@42080000 { #size-cells =3D <1>; #access-controller-cells =3D <1>; ranges; + bootph-all; =09 =20 timers2: timer@40000000 { compatible =3D "st,stm32mp25-timers"; @@ -1569,6 +1576,7 @@ trigger@4 { }; =20 ltdc: display-controller@48010000 { + bootph-all; compatible =3D "st,stm32mp251-ltdc"; reg =3D <0x48010000 0x400>; interrupts =3D , @@ -1738,6 +1746,7 @@ bsec: efuse@44000000 { reg =3D <0x44000000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 part_number_otp@24 { reg =3D <0x24 0x4>; @@ -1842,6 +1851,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers =3D <&rifsc 156>; + bootph-all; }; =20 exti1: interrupt-controller@44220000 { @@ -1941,6 +1951,7 @@ syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; #clock-cells =3D <0>; + bootph-all; }; =20 pinctrl: pinctrl@44240000 { @@ -1951,6 +1962,7 @@ pinctrl: pinctrl@44240000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioa: gpio@44240000 { gpio-controller; @@ -1960,6 +1972,7 @@ gpioa: gpio@44240000 { reg =3D <0x0 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOA>; st,bank-name =3D "GPIOA"; + bootph-all; status =3D "disabled"; }; =20 @@ -1971,6 +1984,7 @@ gpiob: gpio@44250000 { reg =3D <0x10000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOB>; st,bank-name =3D "GPIOB"; + bootph-all; status =3D "disabled"; }; =20 @@ -1982,6 +1996,7 @@ gpioc: gpio@44260000 { reg =3D <0x20000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOC>; st,bank-name =3D "GPIOC"; + bootph-all; status =3D "disabled"; }; =20 @@ -1993,6 +2008,7 @@ gpiod: gpio@44270000 { reg =3D <0x30000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOD>; st,bank-name =3D "GPIOD"; + bootph-all; status =3D "disabled"; }; =20 @@ -2004,6 +2020,7 @@ gpioe: gpio@44280000 { reg =3D <0x40000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOE>; st,bank-name =3D "GPIOE"; + bootph-all; status =3D "disabled"; }; =20 @@ -2015,6 +2032,7 @@ gpiof: gpio@44290000 { reg =3D <0x50000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOF>; st,bank-name =3D "GPIOF"; + bootph-all; status =3D "disabled"; }; =20 @@ -2026,6 +2044,7 @@ gpiog: gpio@442a0000 { reg =3D <0x60000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOG>; st,bank-name =3D "GPIOG"; + bootph-all; status =3D "disabled"; }; =20 @@ -2037,6 +2056,7 @@ gpioh: gpio@442b0000 { reg =3D <0x70000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOH>; st,bank-name =3D "GPIOH"; + bootph-all; status =3D "disabled"; }; =20 @@ -2048,6 +2068,7 @@ gpioi: gpio@442c0000 { reg =3D <0x80000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOI>; st,bank-name =3D "GPIOI"; + bootph-all; status =3D "disabled"; }; =20 @@ -2059,6 +2080,7 @@ gpioj: gpio@442d0000 { reg =3D <0x90000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOJ>; st,bank-name =3D "GPIOJ"; + bootph-all; status =3D "disabled"; }; =20 @@ -2070,6 +2092,7 @@ gpiok: gpio@442e0000 { reg =3D <0xa0000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOK>; st,bank-name =3D "GPIOK"; + bootph-all; status =3D "disabled"; }; }; @@ -2092,6 +2115,7 @@ pinctrl_z: pinctrl@46200000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioz: gpio@46200000 { gpio-controller; @@ -2102,6 +2126,7 @@ gpioz: gpio@46200000 { clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name =3D "GPIOZ"; st,bank-ioport =3D <11>; + bootph-all; =09 status =3D "disabled"; }; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index e718d888ce21..69bac9e719d7 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -130,7 +130,18 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 6e165073f732..307b9692b00a 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -477,11 +477,22 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart6_pins_a>; --=20 2.43.0