From nobody Mon Feb 9 12:02:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE996330B33; Wed, 12 Nov 2025 14:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762958014; cv=none; b=iA47gTZwww7e+KxbYc4Gkq7Pz2QgRy8EUNwd6QYPHJMVrBq8mAXwXx773eeQACA1CaMLzPFT4G1i4f39L93bX5IgC3nwuFpuhwFkKaNIwgEgMZXvzefYbDbogkZW1RBW54cNKutlDPbg8jLoynPh69nA4xj6RSa3IlAQwCUvP24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762958014; c=relaxed/simple; bh=zhH7akUfM6H1jjyVJ86y5rQ+7rbYZJfndGQJBahHkAw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ckjac7Y+kA8hybn5h6LYEYGXFejQ4k3NIMA7ZPsH3qgsW2qGtRlqX6Zx8xkYZC1eUKcCx9S9El1SYbZanOZfHSRo1i/iB2vEgcroOr38JgjtnD01M2FaJgJ6uY06haEsx5pK2ztPfHtR5MVGQZ8lVisnjvheZQTka9/aGtNAOGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SK3m/hf+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SK3m/hf+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7DFC5C19423; Wed, 12 Nov 2025 14:33:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762958014; bh=zhH7akUfM6H1jjyVJ86y5rQ+7rbYZJfndGQJBahHkAw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SK3m/hf+z6gAd99lb93I4YHdsts1OVSvpSEnnu0d5eXMAfhXg1pzznQSYU5knDeUE Cv6AEEvfLJ0DeZvW067dEA98QuFJdrTQ8stSU3k2H84Bonxt4n0NbTZdU3ai7HFQFf AAg/fgH7T0rffoGMSB/84iXmLiqrbxexvqy2WspNnkGCOKGREJLWtE1NeCCIJi7/AM OZPvX92qvd+AoMWwGgotPlWLwXebjE22vgG27sUg0OsmJHzkvFgKBjnFHt2TX7lBeU OEpDzrnJqlRjgDBjlj+cyED/rjbg/v7JyMRAA7LKDEvvTTjwOsUyR6j3CDuRnHTRJL k98LsArg2SwiA== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [RFC v1 1/4] dt-bindings: pinctrl: document polarfire soc mssio pin controller Date: Wed, 12 Nov 2025 14:31:12 +0000 Message-ID: <20251112-reappear-margarita-83b9d6c04dd6@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251112-lantern-sappy-bea86ff2a7f4@spud> References: <20251112-lantern-sappy-bea86ff2a7f4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4998; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=iNHIWtPBx0P22Oi9qXWzp6kiNAvlDd7zPsi/JxAH/S8=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkis0zrDuQVn5v57baYxwyzTWoWvByfap4VRZkpR54sK 5eUzivtKGVhEONikBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwEReXmdkONSrYrc2ZN2cDnvV lHzDv6cWhUp+amKdGbRhT5asfaexC8P/+tO9Z0Ssly0KfdmwdL7tksITM1cqTv7J8K671uyEygQ LFgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6, which determine what function in routed to them, and MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin. Document it, including several custom configuration options that stem from MSS Configurator options (the MSS Configurator is part of the FPGA tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping with an MSS Configurator option, unlike clamp-diode or lockdown, and I do not know the effect of any bits in the field. I have no been able to find an explanation for these bits in documentation. Signed-off-by: Conor Dooley Reviewed-by: Linus Walleij --- .../pinctrl/microchip,mpfs-pinctrl-mssio.yaml | 108 ++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 4 + 2 files changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpf= s-pinctrl-mssio.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinct= rl-mssio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pi= nctrl-mssio.yaml new file mode 100644 index 000000000000..32d7a31d669f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssi= o.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire SoC MSSIO pinctrl + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,mpfs-pinctrl-mssio + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + additionalProperties: false + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + description: | + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. The "reserved" function tristates a pin. + enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc + reserved, gpio, fabric-test, tied-low, tied-high, tris= tate ] + + bias-bus-hold: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + low-power-enable: true + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ] + + microchip,clamp-diode: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Reflects the "Clamp Diode" setting in the MSS Configurator f= or + this pin. + + microchip,bank-lockdown: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Reflects the "Lock Down Bank{2,4} I/Os" setting in the MSS + Configurator for this pin. + + microchip,ibufmd: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: | + Reflects the "IBUFMD" bits in the MSS Configurator output fi= les + for this pin. + + required: + - pins + - function + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@204 { + compatible =3D "microchip,mpfs-pinctrl-mssio"; + reg =3D <0x204 0x7c>; + + irkd_sd_cfg: irkd-sd-cfg { + sd-10ma-pins { + pins =3D <0>, <1>, <2>, <3>, <4>, <5>, <8>, <9>, <10>, <11>, <12= >, <13>; + function =3D "sd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sd-8ma-pins { + pins =3D <6>, <7>; + function =3D "sd"; + bias-pull-up; + drive-strength =3D <8>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 39987f722411..44e4a50c3155 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -42,6 +42,10 @@ properties: type: object $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml =20 + pinctrl@204: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml + required: - compatible - reg --=20 2.51.0 From nobody Mon Feb 9 12:02:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 071563396F7; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KJCy4yIK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD6C5C19422; Wed, 12 Nov 2025 14:33:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762958016; bh=17GDotM6+O4Q0i3MOBA56Oq5A8XOiolm5OTQUdZ2Huw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KJCy4yIKJCgurC1qb6R29QSAcYUq3k/ecA16SC1mdQ9DDO+ys5TAqEXtQYJOM2PJX rg5MilEZqVaD1+3s6Jm3yhBAk9FNi44MDc0c4rQyo4lD4WJ5JK/iSgE0K1jAF4Bts2 vi4/Sp24kmbjYiPhES86d0WHCJJ6Y6BOTW+NlUoJfaemCV/V0KvrWoOBYyDPdIiWlI /dNQ6O/npArbvPvfPpgKuZGzVrheBsYxutZmtiQ8+0wGyxKz2FjzqbezNuSNrLT4Ir Whjdbmewh3xOl358jlDlz2fSg7bkYVpIovwhjWuUOOGZm4/gPLe0dodBpWFtdOA4s8 K+4+c7GtlWnqg== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [RFC v1 2/4] pinctrl: add polarfire soc mssio pinctrl driver Date: Wed, 12 Nov 2025 14:31:13 +0000 Message-ID: <20251112-improving-tassel-06c6301b3e23@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251112-lantern-sappy-bea86ff2a7f4@spud> References: <20251112-lantern-sappy-bea86ff2a7f4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=24344; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=QmX0LR7tHTOxSAJZefaAg7EWto8xNEinboog3OXzQ/w=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkis0zP9R/a9T6ywOtP3cTLUz6EyRpW8XVzl95asurHx 5lPOhnWd5SyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAi2zIYGe6L6q3r4kjs4qwT /6c0ufTlZknlnjuufHKLJ74SC+EpWcvIcPJLwrwl/g4Bzd5btgcz2t5dmpRxXDKw7p5v6V3OmLK 3XAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6, which determine what function in routed to them, and MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin. Add a driver for this pin controller, including several custom properties that reflect aspects of the MSS's configuration. Reuse the Kconfig option for iomux0, since controlling MSSIOs without iomux0 routing a function to the MSSIOs in question is pointless, and routing a function to the MSSIOs is equally unhelpful if none of them are configured to make use of that function. Signed-off-by: Conor Dooley --- drivers/pinctrl/Kconfig | 5 +- drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mpfs-mssio.c | 798 +++++++++++++++++++++++++++ 3 files changed, 803 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/pinctrl-mpfs-mssio.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4ec2bb7f67cf..437616e5a6d5 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -506,9 +506,12 @@ config PINCTRL_PISTACHIO This support pinctrl and GPIO driver for IMG Pistachio SoC. =20 config PINCTRL_POLARFIRE_SOC - bool "Polarfire SoC pinctrl driver" + bool "Polarfire SoC pinctrl drivers" depends on ARCH_MICROCHIP || COMPILE_TEST + select PINMUX select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS default y help This selects the pinctrl driver for Microchip Polarfire SoC. diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ea4e890766e1..bf181654fe7f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PIC64GX) +=3D pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o +obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) +=3D pinctrl-mpfs-mssio.o obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) +=3D pinctrl-mpfs-iomux0.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o diff --git a/drivers/pinctrl/pinctrl-mpfs-mssio.c b/drivers/pinctrl/pinctrl= -mpfs-mssio.c new file mode 100644 index 000000000000..e1b963350016 --- /dev/null +++ b/drivers/pinctrl/pinctrl-mpfs-mssio.c @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "linux/dev_printk.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinconf.h" +#include "pinmux.h" + +#define MPFS_PINCTRL_PAD_MUX_MASK GENMASK(3, 0) + +#define MPFS_PINCTRL_IOCFG_MASK GENMASK(14, 0) +#define MPFS_PINCTRL_IBUFMD_MASK GENMASK(2, 0) +#define MPFS_PINCTRL_DRV_MASK GENMASK(6, 3) +#define MPFS_PINCTRL_CLAMP BIT(7) +#define MPFS_PINCTRL_ENHYST BIT(8) +#define MPFS_PINCTRL_LOCKDN BIT(9) +#define MPFS_PINCTRL_WPD BIT(10) +#define MPFS_PINCTRL_WPU BIT(11) +#define MPFS_PINCTRL_PULL_MASK GENMASK(11, 10) +#define MPFS_PINCTRL_LP_PERSIST_EN BIT(12) +#define MPFS_PINCTRL_LP_BYPASS_EN BIT(13) + +#define MPFS_PINCTRL_LVCMOS25 0x6 +#define MPFS_PINCTRL_BANK_VOLTAGE_MASK GENMASK(19, 16) + +#define MPFS_PINCTRL_BANK2_CFG_CR 0x1c4 +#define MPFS_PINCTRL_BANK4_CFG_CR 0x1c8 +#define MPFS_PINCTRL_IOCFG01_REG 0x234 + +#define MPFS_PINCTRL_INTER_BANK_GAP 0x4 + +#define MPFS_PINCTRL_BANK2_START 14 + +#define MPFS_PINCTRL_LOCKDOWN (PIN_CONFIG_END + 1) +#define MPFS_PINCTRL_CLAMP_DIODE (PIN_CONFIG_END + 2) +#define MPFS_PINCTRL_IBUFMD (PIN_CONFIG_END + 3) + +struct mpfs_pinctrl_mux_config { + u8 pin; + u8 function; +}; + +struct mpfs_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct mutex mutex; + struct pinctrl_desc desc; + u32 bank2_voltage; + u32 bank4_voltage; +}; + +struct mpfs_pinctrl_drive_strength { + u8 ma; + u8 val; +}; + +static struct mpfs_pinctrl_drive_strength mpfs_pinctrl_drive_strengths[8] = =3D { + { 2, 2 }, + { 4, 3 }, + { 6, 4 }, + { 8, 5 }, + { 10, 6 }, + { 12, 7 }, + { 16, 10 }, + { 20, 12 }, +}; + +static char *mpfs_pinctrl_function_names[] =3D { + "sd", + "emmc", + "qspi", + "spi", + "usb", + "uart", + "i2c", + "can", + "mdio", + "misc", + "reserved", + "gpio", + "fabric test", + "tied-low", + "tied-high", + "tristate" +}; + +static int mpfs_pinctrl_function_map(const char *function) +{ + size_t num =3D ARRAY_SIZE(mpfs_pinctrl_function_names); + + for (int i =3D 0; i < num; i++) + if (!strcmp(function, mpfs_pinctrl_function_names[i])) + return i; + + return -EINVAL; +} + +static const struct pinconf_generic_params mpfs_pinctrl_custom_bindings[] = =3D { + { "microchip,bank-lockdown", MPFS_PINCTRL_LOCKDOWN, 1 }, + { "microchip,clamp-diode", MPFS_PINCTRL_CLAMP_DIODE, 1 }, + { "microchip,ibufmd", MPFS_PINCTRL_IBUFMD, 0x0 }, +}; + +static int mpfs_pinctrl_pin_to_iomux_offset(unsigned int pin) +{ + int offset; + + switch (pin) { + case 0 ... 7: + offset =3D pin * 4; + break; + case 8 ... 13: + offset =3D (pin - 8) * 4; + break; + case 14 ... 21: + offset =3D (pin - 14) * 4; + break; + case 22 ... 29: + offset =3D (pin - 22) * 4; + break; + case 30 ... 37: + offset =3D (pin - 30) * 4; + break; + default: + offset =3D -EINVAL; + } + + return offset; +} + +static int mpfs_pinctrl_pin_to_iomux_reg(unsigned int pin) +{ + int reg; + + switch (pin) { + case 0 ... 7: + reg =3D 0x204; + break; + case 8 ... 13: + reg =3D 0x208; + break; + case 14 ... 21: + reg =3D 0x20c; + break; + case 22 ... 29: + reg =3D 0x210; + break; + case 30 ... 37: + reg =3D 0x214; + break; + default: + reg =3D -EINVAL; + } + + return reg; +} + +static int mpfs_pinctrl_pin_to_iocfg_reg(unsigned int pin) +{ + u32 reg =3D MPFS_PINCTRL_IOCFG01_REG; + + if (pin >=3D MPFS_PINCTRL_BANK2_START) + reg +=3D MPFS_PINCTRL_INTER_BANK_GAP; + + // 2 pins per 32-bit register + reg +=3D (pin / 2) * 0x4; + + return reg; +} + +static int mpfs_pinctrl_pin_to_iocfg_offset(unsigned int pin) +{ + return 16 * (pin % 2); +} + +static u32 mpfs_pinctrl_pin_to_bank_voltage(struct mpfs_pinctrl *pctrl, un= signed int pin) +{ + u32 bank_voltage; + + if (pin < MPFS_PINCTRL_BANK2_START) + bank_voltage =3D pctrl->bank4_voltage; + else + bank_voltage =3D pctrl->bank2_voltage; + + return FIELD_GET(MPFS_PINCTRL_BANK_VOLTAGE_MASK, bank_voltage); +} + +static void mpfs_pinctrl_dbg_show(struct pinctrl_dev *pctrl_dev, struct se= q_file *seq, + unsigned int pin) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + u32 func; + int reg, offset; + + reg =3D mpfs_pinctrl_pin_to_iomux_reg(pin); + offset =3D mpfs_pinctrl_pin_to_iomux_offset(pin); + + seq_printf(seq, "reg: %x, offset: %u ", reg, offset); + seq_printf(seq, "pin: %u ", pin); + + if (reg < 0 || offset < 0) + return; + + regmap_read(pctrl->regmap, reg, &func); + func =3D (func >> offset) & MPFS_PINCTRL_PAD_MUX_MASK; + seq_printf(seq, "func: %s (%x)\n", mpfs_pinctrl_function_names[func], fun= c); +} + +static int mpfs_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev, stru= ct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + struct device *dev =3D pctrl->dev; + struct device_node *child; + struct pinctrl_map *map; + const char **group_names; + const char *group_name; + int ngroups =3D 0; + int nmaps =3D 0; + int ret; + + for_each_available_child_of_node(np, child) + ngroups +=3D 1; + + group_names =3D devm_kcalloc(dev, ngroups, sizeof(*group_names), GFP_KERN= EL); + if (!group_names) + return -ENOMEM; + + map =3D kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + ngroups =3D 0; + guard(mutex)(&pctrl->mutex); + for_each_available_child_of_node_scoped(np, child) { + struct mpfs_pinctrl_mux_config *pinmuxs; + const char *function_name; + unsigned int pin, *pins; + int function, npins; + + npins =3D of_property_count_u32_elems(child, "pins"); + + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn %d\n", + np, child, npins); + return npins; + } + + group_name =3D devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!group_name) + return -ENOMEM; + + group_names[ngroups++] =3D group_name; + + pins =3D devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pinmuxs =3D devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); + if (!pinmuxs) + return -ENOMEM; + + for (int i =3D 0; i < npins; i++) { + ret =3D of_property_read_u32_index(child, "pins", i, &pin); + if (ret) + return ret; + + pins[i] =3D pin; + pinmuxs[i].pin =3D pin; + + ret =3D of_property_read_string(child, "function", &function_name); + function =3D mpfs_pinctrl_function_map(function_name); + if (function < 0) + return dev_err_probe(dev, function, "invalid function %s\n", + function_name); + pinmuxs[i].function =3D function; + } + + map[nmaps].type =3D PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function =3D np->name; + map[nmaps].data.mux.group =3D group_name; + nmaps +=3D 1; + + ret =3D pinctrl_generic_add_group(pctrl_dev, group_name, pins, npins, pi= nmuxs); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add group %s: %d\n", + group_name, ret); + + ret =3D pinconf_generic_parse_dt_config(child, pctrl_dev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) + return dev_err_probe(dev, ret, "failed to parse pin config of group %s\= n", + group_name); + + if (map[nmaps].data.configs.num_configs =3D=3D 0) + continue; + + map[nmaps].type =3D PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin =3D group_name; + nmaps +=3D 1; + } + + ret =3D pinmux_generic_add_function(pctrl_dev, np->name, group_names, ngr= oups, NULL); + if (ret < 0) { + pinctrl_utils_free_map(pctrl_dev, map, nmaps); + return dev_err_probe(dev, ret, "error adding function %s\n", np->name); + } + + *maps =3D map; + *num_maps =3D nmaps; + + return 0; +}; + +static const struct pinctrl_ops mpfs_pinctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .pin_dbg_show =3D mpfs_pinctrl_dbg_show, + .dt_node_to_map =3D mpfs_pinctrl_dt_node_to_map, + .dt_free_map =3D pinctrl_utils_free_map, +}; + +static int mpfs_pinctrl_set_pin_func(struct mpfs_pinctrl *pctrl, u8 pin, u= 8 function) +{ + struct device *dev =3D pctrl->dev; + u32 reg, func, mask, offset; + + reg =3D mpfs_pinctrl_pin_to_iomux_reg(pin); + offset =3D mpfs_pinctrl_pin_to_iomux_offset(pin); + + func =3D function << offset; + mask =3D MPFS_PINCTRL_PAD_MUX_MASK << offset; + + dev_dbg(dev, "Setting pin %u. reg: %x offset %u func %x\n", pin, reg, off= set, func); + + if (reg < 0 || offset < 0) + return -EINVAL; + + regmap_update_bits(pctrl->regmap, reg, mask, func); + + return 0; +} + +static int mpfs_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unsigned in= t fsel, + unsigned int gsel) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + const struct group_desc *group; + struct mpfs_pinctrl_mux_config *configs; + + group =3D pinctrl_generic_get_group(pctrl_dev, gsel); + if (!group) + return -EINVAL; + + configs =3D group->data; + + for (int i =3D 0; i < group->grp.npins; i++) + mpfs_pinctrl_set_pin_func(pctrl, configs[i].pin, configs[i].function); + + return 0; +} + +static const struct pinmux_ops mpfs_pinctrl_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D mpfs_pinctrl_set_mux, +}; + +static int mpfs_pinctrl_get_drive_strength_ma(u32 drive_strength) +{ + size_t num =3D ARRAY_SIZE(mpfs_pinctrl_drive_strengths); + + for (int i =3D 0; i < num; i++) + if (drive_strength =3D=3D mpfs_pinctrl_drive_strengths[i].val) + return mpfs_pinctrl_drive_strengths[i].ma; + + return -EINVAL; +} + +static int mpfs_pinctrl_get_drive_strength_val(u32 drive_strength_ma) +{ + size_t num =3D ARRAY_SIZE(mpfs_pinctrl_drive_strengths); + + if (!drive_strength_ma) + return -EINVAL; + + for (int i =3D 0; i < num; i++) + if (drive_strength_ma <=3D mpfs_pinctrl_drive_strengths[i].ma) + return mpfs_pinctrl_drive_strengths[i].val; + + return mpfs_pinctrl_drive_strengths[num - 1].val; +} + +static int mpfs_pinctrl_pinconf_get(struct pinctrl_dev *pctrl_dev, unsigne= d int pin, + unsigned long *config) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + int param =3D pinconf_to_config_param(*config); + int reg =3D mpfs_pinctrl_pin_to_iocfg_reg(pin); + int val; + u32 arg; + //TODO bank_voltage; + u8 str; + + regmap_read(pctrl->regmap, reg, &val); + + val =3D val >> mpfs_pinctrl_pin_to_iocfg_offset(pin); + val =3D val & MPFS_PINCTRL_IOCFG_MASK; + + switch (param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + if (!(val & MPFS_PINCTRL_WPD)) + return -EINVAL; + + if (!(val & MPFS_PINCTRL_WPU)) + return -EINVAL; + + arg =3D 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!(val & MPFS_PINCTRL_WPD)) + return -EINVAL; + + if (val & MPFS_PINCTRL_WPU) + return -EINVAL; + + arg =3D 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (!(val & MPFS_PINCTRL_WPU)) + return -EINVAL; + + if (val & MPFS_PINCTRL_WPD) + return -EINVAL; + + arg =3D 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + if (val & MPFS_PINCTRL_PULL_MASK) + return -EINVAL; + + arg =3D 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + str =3D FIELD_GET(MPFS_PINCTRL_DRV_MASK, val); + if (!str) + return -EINVAL; + + arg =3D mpfs_pinctrl_get_drive_strength_ma(str); + break; + //TODO @Linus, it correct to group these 3? There's no control over volta= ge. + case PIN_CONFIG_INPUT_SCHMITT: + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + case PIN_CONFIG_INPUT_SCHMITT_UV: + //TODO Is it enabled regardless of register setting, or must it + // be set for lower voltage IO? Docs are missing, MSS Configurator + // is not clear. Leaning towards the latter. + //bank_voltage =3D mpfs_pinctrl_pin_to_bank_voltage(pctrl, pin); + //if (bank_voltage < MPFS_PINCTRL_LVCMOS25) { + // arg =3D 1; + // break; + //} + + if (!FIELD_GET(MPFS_PINCTRL_ENHYST, val)) + return -EINVAL; + + arg =3D 1; + break; + case PIN_CONFIG_PERSIST_STATE: + if (!FIELD_GET(MPFS_PINCTRL_LP_PERSIST_EN, val)) + return -EINVAL; + + arg =3D 1; + break; + case PIN_CONFIG_MODE_LOW_POWER: + if (!FIELD_GET(MPFS_PINCTRL_LP_BYPASS_EN, val)) + return -EINVAL; + + arg =3D 1; + break; + case MPFS_PINCTRL_CLAMP_DIODE: + if (!FIELD_GET(MPFS_PINCTRL_CLAMP, val)) + return -EINVAL; + + arg =3D 1; + break; + case MPFS_PINCTRL_LOCKDOWN: + if (!FIELD_GET(MPFS_PINCTRL_LOCKDN, val)) + return -EINVAL; + + arg =3D 1; + break; + case MPFS_PINCTRL_IBUFMD: + arg =3D FIELD_GET(MPFS_PINCTRL_IBUFMD_MASK, val); + break; + default: + return -ENOTSUPP; + } + + *config =3D pinconf_to_config_packed(param, arg); + + return 0; +} + +static int mpfs_pinctrl_pinconf_generate_config(struct mpfs_pinctrl *pctrl= , unsigned int pin, + unsigned long *configs, unsigned int num_configs, + u32 *value) +{ + u32 val =3D 0; + + for (int i =3D 0; i < num_configs; i++) { + int param, tmp; + u32 arg; + //TODO bank_voltage; + + param =3D pinconf_to_config_param(configs[i]); + arg =3D pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + val |=3D MPFS_PINCTRL_PULL_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + //TODO always start from val =3D=3D 0, there's no reason to ever actual= ly + // clear anything AFAICT. @Linus, does the driver need to check mutual + // exclusion on these, or can I drop the clearing? + val &=3D ~MPFS_PINCTRL_PULL_MASK; + val |=3D MPFS_PINCTRL_WPD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + val &=3D ~MPFS_PINCTRL_PULL_MASK; + val |=3D MPFS_PINCTRL_WPU; + break; + case PIN_CONFIG_BIAS_DISABLE: + val &=3D ~MPFS_PINCTRL_PULL_MASK; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + tmp =3D mpfs_pinctrl_get_drive_strength_val(arg); + if (tmp < 0) + return tmp; + + val |=3D FIELD_PREP(MPFS_PINCTRL_DRV_MASK, tmp); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!arg) + break; + fallthrough; + case PIN_CONFIG_INPUT_SCHMITT: + case PIN_CONFIG_INPUT_SCHMITT_UV: + //TODO Is it enabled regardless of register setting, or must it + // be set for lower voltage IO? Docs are missing, MSS Configurator + // is not clear. Leaning towards the latter. + //bank_voltage =3D mpfs_pinctrl_pin_to_bank_voltage(pctrl, pin); + //if (bank_voltage < MPFS_PINCTRL_LVCMOS25 && !arg) { + // dev_err(pctrl->dev, + // "schmitt always enabled for 1.2, 1.5 and 1.8 volt io\n"); + // return -EINVAL; + //} + val |=3D MPFS_PINCTRL_ENHYST; + break; + case PIN_CONFIG_PERSIST_STATE: + val |=3D MPFS_PINCTRL_LP_PERSIST_EN; + break; + case PIN_CONFIG_MODE_LOW_POWER: + if (arg) + val |=3D MPFS_PINCTRL_LP_BYPASS_EN; + break; + //TODO @Linus, do I have to document these custom controls other than in= the binding? + case MPFS_PINCTRL_CLAMP_DIODE: + val |=3D MPFS_PINCTRL_CLAMP; + break; + case MPFS_PINCTRL_LOCKDOWN: + val &=3D MPFS_PINCTRL_LOCKDN; + break; + case MPFS_PINCTRL_IBUFMD: + val |=3D FIELD_PREP(MPFS_PINCTRL_IBUFMD_MASK, arg); + break; + default: + dev_err(pctrl->dev, "config %u not supported\n", param); + return -ENOTSUPP; + } + } + + *value =3D val; + return 0; +} + +static int mpfs_pinctrl_pin_set_config(struct mpfs_pinctrl *pctrl, unsigne= d int pin, u32 config) +{ + int reg =3D mpfs_pinctrl_pin_to_iocfg_reg(pin); + int offset =3D mpfs_pinctrl_pin_to_iocfg_offset(pin); + u32 val, mask; + + mask =3D MPFS_PINCTRL_IOCFG_MASK << offset; + val =3D config << offset; + + regmap_update_bits(pctrl->regmap, reg, mask, val); + + return 0; +} + +static int mpfs_pinctrl_pinconf_set(struct pinctrl_dev *pctrl_dev, unsigne= d int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + int ret; + + ret =3D mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_con= figs, &val); + if (ret) + return ret; + + return mpfs_pinctrl_pin_set_config(pctrl, pin, val); +} + +static int mpfs_pinctrl_pinconf_group_set(struct pinctrl_dev *pctrl_dev, u= nsigned int gsel, + unsigned long *configs, unsigned int num_configs) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + const struct group_desc *group; + unsigned int pin; + u32 val; + int ret; + + group =3D pinctrl_generic_get_group(pctrl_dev, gsel); + if (!group) + return -EINVAL; + + /* + * Assume that the first pin in a group is representative, as the mss + * configurator doesn't allow splitting a function between two banks. + */ + pin =3D group->grp.pins[0]; + + ret =3D mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_con= figs, &val); + if (ret) + return ret; + + for (int i =3D 0; i < group->grp.npins; i++) + mpfs_pinctrl_pin_set_config(pctrl, group->grp.pins[i], val); + + return 0; +} + +static void mpfs_pinctrl_pinconf_dbg_show(struct pinctrl_dev *pctrl_dev, s= truct seq_file *seq, + unsigned int pin) +{ + struct mpfs_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + int reg, offset; + + seq_printf(seq, ", bank voltage: 0x%x, ", mpfs_pinctrl_pin_to_bank_voltag= e(pctrl, pin)); + + reg =3D mpfs_pinctrl_pin_to_iocfg_reg(pin); + offset =3D mpfs_pinctrl_pin_to_iocfg_offset(pin); + + seq_printf(seq, "pin: %u ", pin); + seq_printf(seq, "reg: %x offset: %u ", reg, offset); + + if (reg < 0 || offset < 0) + return; + + regmap_read(pctrl->regmap, reg, &val); + val =3D (val & (MPFS_PINCTRL_IOCFG_MASK << offset)) >> offset; + seq_printf(seq, "val: %x\n", val); +} + +static const struct pinconf_ops mpfs_pinctrl_pinconf_ops =3D { + .pin_config_get =3D mpfs_pinctrl_pinconf_get, + .pin_config_set =3D mpfs_pinctrl_pinconf_set, + .pin_config_group_set =3D mpfs_pinctrl_pinconf_group_set, + .pin_config_dbg_show =3D mpfs_pinctrl_pinconf_dbg_show, + .is_generic =3D true, +}; + +static const struct pinctrl_pin_desc mpfs_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "bank 4 0"), + PINCTRL_PIN(1, "bank 4 1"), + PINCTRL_PIN(2, "bank 4 2"), + PINCTRL_PIN(3, "bank 4 3"), + PINCTRL_PIN(4, "bank 4 4"), + PINCTRL_PIN(5, "bank 4 5"), + PINCTRL_PIN(6, "bank 4 6"), + PINCTRL_PIN(7, "bank 4 7"), + PINCTRL_PIN(8, "bank 4 8"), + PINCTRL_PIN(9, "bank 4 9"), + PINCTRL_PIN(10, "bank 4 10"), + PINCTRL_PIN(11, "bank 4 11"), + PINCTRL_PIN(12, "bank 4 12"), + PINCTRL_PIN(13, "bank 4 13"), + + PINCTRL_PIN(14, "bank 2 0"), + PINCTRL_PIN(15, "bank 2 1"), + PINCTRL_PIN(16, "bank 2 2"), + PINCTRL_PIN(17, "bank 2 3"), + PINCTRL_PIN(18, "bank 2 4"), + PINCTRL_PIN(19, "bank 2 5"), + PINCTRL_PIN(20, "bank 2 6"), + PINCTRL_PIN(21, "bank 2 7"), + PINCTRL_PIN(22, "bank 2 8"), + PINCTRL_PIN(23, "bank 2 9"), + PINCTRL_PIN(24, "bank 2 10"), + PINCTRL_PIN(25, "bank 2 11"), + PINCTRL_PIN(26, "bank 2 12"), + PINCTRL_PIN(27, "bank 2 13"), + PINCTRL_PIN(28, "bank 2 14"), + PINCTRL_PIN(29, "bank 2 15"), + PINCTRL_PIN(30, "bank 2 16"), + PINCTRL_PIN(31, "bank 2 17"), + PINCTRL_PIN(32, "bank 2 18"), + PINCTRL_PIN(33, "bank 2 19"), + PINCTRL_PIN(34, "bank 2 20"), + PINCTRL_PIN(35, "bank 2 21"), + PINCTRL_PIN(36, "bank 2 22"), + PINCTRL_PIN(37, "bank 2 23"), +}; + +static int mpfs_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mpfs_pinctrl *pctrl; + struct regmap *sysreg_scb; + int ret; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(pctrl->regmap)) + dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap= \n"); + + sysreg_scb =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-= scb"); + if (IS_ERR(sysreg_scb)) + return PTR_ERR(sysreg_scb); + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D mpfs_pinctrl_pins; + pctrl->desc.npins =3D ARRAY_SIZE(mpfs_pinctrl_pins); + pctrl->desc.pctlops =3D &mpfs_pinctrl_ops; + pctrl->desc.pmxops =3D &mpfs_pinctrl_pinmux_ops; + pctrl->desc.confops =3D &mpfs_pinctrl_pinconf_ops; + pctrl->desc.owner =3D THIS_MODULE; + pctrl->desc.num_custom_params =3D ARRAY_SIZE(mpfs_pinctrl_custom_bindings= ); + pctrl->desc.custom_params =3D mpfs_pinctrl_custom_bindings; + + pctrl->dev =3D dev; + + ret =3D devm_mutex_init(dev, &pctrl->mutex); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id mpfs_pinctrl_of_match[] =3D { + { .compatible =3D "microchip,mpfs-pinctrl-mssio" }, + { } +}; +MODULE_DEVICE_TABLE(of, mpfs_pinctrl_of_match); + +static struct platform_driver mpfs_pinctrl_driver =3D { + .driver =3D { + .name =3D "mpfs-pinctrl", + .of_match_table =3D mpfs_pinctrl_of_match, + }, + .probe =3D mpfs_pinctrl_probe, +}; +module_platform_driver(mpfs_pinctrl_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("Polarfire SoC mssio pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Mon Feb 9 12:02:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3472F33A03A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fh+YfXAL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2ED3C4CEF1; Wed, 12 Nov 2025 14:33:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762958018; bh=WCTVp6YyrZb1HeS7GoDyJOELy1+STwBon/GVCLDwpZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fh+YfXAL+mE3UANP5bcmesum3lZsWbq+RC0SduO2zqZRYyZlxEYMKwBqNaBPOdMEL 7eYqa7b0eeMkKABw2NjzOm+GkbYwWane27iZW53A1eKpfoyBnkho44nE5iZln1L8fi mdp5RPfPkvtZduyw0t3j8s8RpMMqUdgfoVO16xMNu8C65LlMeXO64vhbqqf+G27ALe 8qdUd7+03O4NO/40rf+91dQsqtsxQV2Gx2ZO8brDdI0gfJizoK9aLAHXrVzMKjeXIw xsqH9NPdPBItuz1Sj7YCZw6G6+D0nsL25jZDYehdr5Tc4nAk6vxoeOOW1QJIJFEzFo fi7215j67E5kA== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [RFC v1 3/4] MAINTAINERS: add Microchip mpfs mssio driver/bindings to entry Date: Wed, 12 Nov 2025 14:31:14 +0000 Message-ID: <20251112-bungee-widget-8f7a5b947a3c@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251112-lantern-sappy-bea86ff2a7f4@spud> References: <20251112-lantern-sappy-bea86ff2a7f4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1316; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=SYXxlq6CpuOEhhmDtAirN//eVcTIugoL6YBJ+hoXwBY=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkis0w9dSuZ0uRe5G0Iu11g+Uznv32MxMMjFmKPSxYGx mj6//vZUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIl4FzEyHNUImhv4bf3PWdea mDwfei1dbTFVy7DQJaLigtz1yDOMLIwMTwS9pkw4K9UYJ3vB986UB5OTnnTN2LG08mXnLe6m987 sPAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add the new mssio driver and bindings to the existing entry for Microchip RISC-V devices. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5d4825073fcd..380970935407 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22090,6 +22090,7 @@ F: Documentation/devicetree/bindings/i2c/microchip,= corei2c.yaml F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0= .yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.= yaml F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpi= o2.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml F: Documentation/devicetree/bindings/riscv/microchip.yaml @@ -22105,6 +22106,7 @@ F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/plda/pcie-microchip-host.c F: drivers/pinctrl/pinctrl-mpfs-iomux0.c +F: drivers/pinctrl/pinctrl-mpfs-mssio.c F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c --=20 2.51.0 From nobody Mon Feb 9 12:02:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 740B533AD95; Wed, 12 Nov 2025 14:33:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762958021; cv=none; b=t/NmO3ui69EAjZt3+zflMhAPY2GGNxaSXSOF55RpdmockCz0GLw/WXh1HgpB2LEJ9BgncTmubukxvjKJiskpsWZlY/rCB57Y9cM/pRoJOIs61iOqT2S1v+KIF0CcoagjDU6qqlPYgJ2admNJWi6uvKR4xGgSL4kuWlypYRJV9vg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762958021; c=relaxed/simple; bh=LBjDojUkNLsnNazLF79Jnlg6W/Xr6nS4KXkw69u7/T0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ut1qEKMLXm0cr/gTGnT18fqpKwlyRH/GIXLSjZODcGOc01qu/HCrCxoxw5MWS99GOZkd4ui0f+wIId8SekLWOgLm1NpYHdhp/CyZKUPnRUn3zQ3A9NfGjHbIImfrTkH4GnBNl1kaS3hX2F9n+6zHYJABdA5WsTpMGXtrdCV7Nq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oW/KcfEj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oW/KcfEj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30C46C4CEF7; Wed, 12 Nov 2025 14:33:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762958021; bh=LBjDojUkNLsnNazLF79Jnlg6W/Xr6nS4KXkw69u7/T0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oW/KcfEj+96/StIPAAok4dN7dznI1aucTbXxAjnFNXvEpGlxggpGf0NICC2l6QRiW CLwwY+L1qHHox4PkQeP4AXl0aWVX35M/ChGOHc2tcZQ1RJFk3uHYNNDXYBDnMxeuOY DS7wbbZJZqWGUpfxgz7Ybh8GKfHWQzSlF5QLTsVnFH6qStT9gJqHCMCmOfyZ3pMuM2 Z03z8bnHt2N/1+MRO6IEBkJbpWdrpvJ7uC3D3ENy1hrSJ0cRXN9/A/uti/uvVIMUy+ QOLkwdGUpPnCvcPG07ehhjBIR3EcFHTGrzdrVSo77OZQ32WVHI+zhjHQiwtwDXIfOB mAi8BzKjpkBnA== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [RFC v1 4/4] riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit Date: Wed, 12 Nov 2025 14:31:15 +0000 Message-ID: <20251112-splendid-spotting-b9fdc0c7c5c8@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251112-lantern-sappy-bea86ff2a7f4@spud> References: <20251112-lantern-sappy-bea86ff2a7f4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7227; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=fEwO3DGjjDDEOIY9sEMs2OumZHERME4ZBJJXvylQ2Gk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkis8xKj7z6mfWxe/79veaOQZeM1vamR0Q/kFGUlPpxx OyOwpLyjlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExk3idGhjkKO8N+pnysWCLj lVXq/X6u8kENY70V+jXWEZHWG9TfFjL801fvZ5+zcb/FOrHI4sMrbNZ1PJLTnaFb1qvQ/VmxpIu NAQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add pinctrl nodes to PolarFire to demonstrate their use, matching the default configuration set by the HSS firmware for the Icicle kit's reference design, as a demonstration of use. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-common.dtsi | 1 - .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 63 +++++++ .../boot/dts/microchip/mpfs-pinctrl.dtsi | 165 ++++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 16 ++ 4 files changed, 244 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index b3f61c58e57c..5667805b4b14 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -3,7 +3,6 @@ =20 /dts-v1/; =20 -#include "mpfs.dtsi" #include "mpfs-icicle-kit-fabric.dtsi" #include #include diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 71f724325578..785176dabcf1 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -1,6 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 +#include "mpfs.dtsi" +#include "mpfs-pinctrl.dtsi" + / { core_pwm0: pwm@40000000 { compatible =3D "microchip,corepwm-rtl-v4"; @@ -80,6 +83,16 @@ refclk_ccc: clock-cccref { }; }; =20 +&can0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&can0_fabric>; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ikrd_can1_cfg>; +}; + &ccc_nw { clocks =3D <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>; @@ -87,3 +100,53 @@ &ccc_nw { "dll0_ref", "dll1_ref"; status =3D "okay"; }; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_fabric>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_fabric>; +}; + +&mmuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_fabric>; +}; + +&mmuart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_fabric>; +}; + +&mmuart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_fabric>; +}; + +&mmuart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart4_fabric>; +}; + +&mssio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_mssio>, <&can1_mssio>, <&mdio0_mssio>, <&mdio1_mssio= >; +}; + +&qspi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qspi_fabric>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_fabric>; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ikrd_spi1_cfg>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi b/arch/riscv/b= oot/dts/microchip/mpfs-pinctrl.dtsi new file mode 100644 index 000000000000..47fc4a523c33 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&iomux0 { + spi0_fabric: mux-spi0-fabric { + function =3D "spi0"; + groups =3D "spi0_fabric"; + }; + + spi0_mssio: mux-spi0-mssio { + function =3D "spi0"; + groups =3D "spi0_mssio"; + }; + + spi1_fabric: mux-spi1-fabric { + function =3D "spi1"; + groups =3D "spi1_fabric"; + }; + + spi1_mssio: mux-spi1-mssio { + function =3D "spi1"; + groups =3D "spi1_mssio"; + }; + + i2c0_fabric: mux-i2c0-fabric { + function =3D "i2c0"; + groups =3D "i2c0_fabric"; + }; + + i2c0_mssio: mux-i2c0-mssio { + function =3D "i2c0"; + groups =3D "i2c0_mssio"; + }; + + i2c1_fabric: mux-i2c1-fabric { + function =3D "i2c1"; + groups =3D "i2c1_fabric"; + }; + + i2c1_mssio: mux-i2c1-mssio { + function =3D "i2c1"; + groups =3D "i2c1_mssio"; + }; + + can0_fabric: mux-can0-fabric { + function =3D "can0"; + groups =3D "can0_fabric"; + }; + + can0_mssio: mux-can0-mssio { + function =3D "can0"; + groups =3D "can0_mssio"; + }; + + can1_fabric: mux-can1-fabric { + function =3D "can1"; + groups =3D "can1_fabric"; + }; + + can1_mssio: mux-can1-mssio { + function =3D "can1"; + groups =3D "can1_mssio"; + }; + + qspi_fabric: mux-qspi-fabric { + function =3D "qspi"; + groups =3D "qspi_fabric"; + }; + + qspi_mssio: mux-qspi-mssio { + function =3D "qspi"; + groups =3D "qspi_mssio"; + }; + + uart0_fabric: mux-uart0-fabric { + function =3D "uart0"; + groups =3D "uart0_fabric"; + }; + + uart0_mssio: mux-uart0-mssio { + function =3D "uart0"; + groups =3D "uart0_mssio"; + }; + + uart1_fabric: mux-uart1-fabric { + function =3D "uart1"; + groups =3D "uart1_fabric"; + }; + + uart1_mssio: mux-uart1-mssio { + function =3D "uart1"; + groups =3D "uart1_mssio"; + }; + + uart2_fabric: mux-uart2-fabric { + function =3D "uart2"; + groups =3D "uart2_fabric"; + }; + + uart2_mssio: mux-uart2-mssio { + function =3D "uart2"; + groups =3D "uart2_mssio"; + }; + + uart3_fabric: mux-uart3-fabric { + function =3D "uart3"; + groups =3D "uart3_fabric"; + }; + + uart3_mssio: mux-uart3-mssio { + function =3D "uart3"; + groups =3D "uart3_mssio"; + }; + + uart4_fabric: mux-uart4-fabric { + function =3D "uart4"; + groups =3D "uart4_fabric"; + }; + + uart4_mssio: mux-uart4-mssio { + function =3D "uart4"; + groups =3D "uart4_mssio"; + }; + + mdio0_fabric: mux-mdio0-fabric { + function =3D "mdio0"; + groups =3D "mdio0_fabric"; + }; + + mdio0_mssio: mux-mdio0-mssio { + function =3D "mdio0"; + groups =3D "mdio0_mssio"; + }; + + mdio1_fabric: mux-mdio1-fabric { + function =3D "mdio1"; + groups =3D "mdio1_fabric"; + }; + + mdio1_mssio: mux-mdio1-mssio { + function =3D "mdio1"; + groups =3D "mdio1_mssio"; + }; +}; + +&mssio { + ikrd_can1_cfg: ikrd-can1-cfg { + can1-pins { + pins =3D <34>, <35>, <36>; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <8>; + microchip,ibufmd =3D <0x1>; + }; + }; + + ikrd_spi1_cfg: ikrd-spi1-cfg { + spi1-pins { + pins =3D <30>, <31>, <32>, <33>; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <8>; + microchip,ibufmd =3D <0x1>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 5c2963e269b8..0fb94581b6cb 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -254,7 +254,23 @@ pdma: dma-controller@3000000 { mss_top_sysreg: syscon@20002000 { compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; reg =3D <0x0 0x20002000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; #reset-cells =3D <1>; + + iomux0: pinctrl@200 { + compatible =3D "microchip,mpfs-pinctrl-iomux0"; + reg =3D <0x200 0x4>; + pinctrl-use-default; + + }; + + mssio: pinctrl@204 { + compatible =3D "microchip,mpfs-pinctrl-mssio"; + reg =3D <0x204 0x7c>; + /* on icicle ref design at least */ + pinctrl-use-default; + }; }; =20 sysreg_scb: syscon@20003000 { --=20 2.51.0