From nobody Mon Feb 9 23:15:40 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE8952FDC5B for ; Wed, 12 Nov 2025 09:45:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762940739; cv=none; b=Xo06QiRXIeLYIDun6jE2nSDONV1qh3qLtaO/Ya/uiBJHPwKEdleLw6AMm3beBPf5z48rrTzGF9kiY5PprJQ4UmstbtMFxeV3DKGxo+Abs0VbuO3WkPoho+xpKFkpqjrnD6Tuu1VTwCoxREtjr7XrlnSdaSOp7lfRQWwciqFrVfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762940739; c=relaxed/simple; bh=hMJzIR4lZEcblXjR0I9hzQzbHScfcP0F6rIKaU7ffA4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BdOj4hVp4w1VxrBF28SDHfeNZkEI4d1IpaNdlsRd2+bjMXKxYz0V2TKzsR5LGcNg8+Uj42mhkUlPhyIjJkQeov5htP7wEN9JXfwR48h3dXATewhfSgzSHeacWeONSEwZ6defuzr0awGCwkMQJB1qRygNBHooC8SeKNChEcBb2wI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=p+3jHZwp; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="p+3jHZwp" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 38C511A1A09; Wed, 12 Nov 2025 09:45:36 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 07ECD6070B; Wed, 12 Nov 2025 09:45:36 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 208C810371997; Wed, 12 Nov 2025 10:45:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1762940735; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Hi/5WmyJVI8+IqSzvn7iNXPzQu9SoH12tl/3+e8BE4I=; b=p+3jHZwp/F/hDJYWcsKK2sHZ1LrLMeUS570EZnkVw6var4BvdZeI8zx3O3tgU6pTXx7k7R j8FkxliIWs7H3+HK6zyItES3GsFgEj5KpUoS5WisYgjg5WWxvMcW4B0XFVn/yPpjS4QReI CyGJ9hsUBnPpNx3i08+xdNAUnMCtf7hYlJoeg6BOHKxAy8W4CSlQZfheoPTaaCwgYb9R4x pyb+Q0PSHbao5YON3asqQVV10kXLlYB2ScnNJ6fOfm8752kWiZ9kOVY7Tmrcu0lrw0Q+85 +HTAZ/ecBYocdMlsy5LsdQmYhaDrMsGdlCLHXTRhQYZsIF/COpcFEy7bHyt8YQ== From: "Kory Maincent (TI.com)" Date: Wed, 12 Nov 2025 10:45:25 +0100 Subject: [PATCH v3 2/2] ARM: dts: am335x-bonegreen-eco: Enable 1GHz OPP by increasing vdd_mpu voltage Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251112-fix_tps65219-v3-2-e49bab4c01ce@bootlin.com> References: <20251112-fix_tps65219-v3-0-e49bab4c01ce@bootlin.com> In-Reply-To: <20251112-fix_tps65219-v3-0-e49bab4c01ce@bootlin.com> To: Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Lee Jones , Shree Ramamoorthy , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Andrew Davis , Bajjuri Praneeth , Thomas Petazzoni , linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The vdd_mpu regulator maximum voltage was previously limited to 1.2985V, which prevented the CPU from reaching the 1GHz operating point. This limitation was put in place because voltage changes were not working correctly, causing the board to stall when attempting higher frequencies. With the recent TPS65219 PMIC driver fixes that properly implement the LOCK register handling, voltage transitions now work reliably. Increase the maximum voltage to 1.3515V to allow the full 1GHz OPP to be used. Reviewed-by: Shree Ramamoorthy Signed-off-by: Kory Maincent (TI.com) --- arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts b/arch/arm/= boot/dts/ti/omap/am335x-bonegreen-eco.dts index d21118cdb6c2c..f00abfdd2cbd4 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-eco.dts @@ -63,7 +63,7 @@ regulators { buck1: buck1 { regulator-name =3D "vdd_mpu"; regulator-min-microvolt =3D <925000>; - regulator-max-microvolt =3D <1298500>; + regulator-max-microvolt =3D <1351500>; regulator-boot-on; regulator-always-on; }; --=20 2.43.0