From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9FEB326941 for ; Tue, 11 Nov 2025 21:22:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762896142; cv=none; b=ME7dMPCqK1y0r1HMYLFirNsQKtyp7uoWiodG1ql5WLooFKTP0MAK4ZPmMNIwdd44uaCzFjz+kMwPWGrlTXHSbtXUlb97hmn+s00YKx/ViemKBbNISO8nEAA9aQgT1e7S3jnFU0wlcTIktPgrAyLIANR2TKyJs0ZcoR2fjmZvM7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762896142; c=relaxed/simple; bh=5gugg7lkraj9TC0kZ6NwAUfMZ08oCZLBOSh79lmJK3Q=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Content-Type; b=IG5u7YzPcdCjQ+auEeg5J2dwjBP8/yyloIv3wZ0Qca/lny/HDNTXAJFs1hUPn57kirQ4IKnzHaYpBlyC9MgoA6bCcWwBWRupCFygz2IriMdesPS1+jvBF21CQM+zv9A4roR0Zm5m58aj/jj1uSAry8qgkXRT30Iu4n7Ri7l9ulE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=0hTwjozp; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="0hTwjozp" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-297f587dc2eso1705845ad.2 for ; Tue, 11 Nov 2025 13:22:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1762896140; x=1763500940; darn=vger.kernel.org; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=C/I124Vpc3AJUGEYy3T6Y6dhWjIbeIJN7sVjw18uSEg=; b=0hTwjozpGdxWjbFMV6w+UozK8zYddvSjiO2FOFF5U19V4oSjuGxITOwwSRfr8+Gp2e xYfyepruKHpb63PuS8SKy2/F/YQa51K3PCSrc3VGm8eJz4fv8dQLbBNtBDpej9kvpEXX rBosqACF8NLPkrB/X2ff//pKIa780XHTTygmQKZdn0ia/UKdjrooJ/uZL77U3gJWoumk a9AOY/SCEhQWPq7ACx42qT8/8Pgal+ov/XOyzuNizD6XEbS/Bl1PKZftQAjsTX5J3JCU 4aRH+gIXM7+RftsbP5L6II344v4rrwdTXEusSt+LGUtJWuE4ivO+cpfVVOb/76o5Zgyz ez8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762896140; x=1763500940; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=C/I124Vpc3AJUGEYy3T6Y6dhWjIbeIJN7sVjw18uSEg=; b=rQ5PCFZiYHDh+VTPtucVKOhJqHBTlDZMgXltivsqfHw46AQWWxoIAOWGvZjNpgf8ht Du3YzmIPfRAFAU+bj88S8+FxzRDAt6cb9VeiS6ec2Xy0qXwRY9Gm0SPx5NylFSMsUhkr yfzm/SqSysLIEF/PBmM4LztPLThDgzTSSHshN5/FvdEiC+HYIPyFNHSeYgvjYbwFV+9F jTBsyflTDu77ivltgSjD2YOOEadqEu47sf63fYJn2xfcqYzBI6Y7PAgoqBKfwtpyP+HP wSPeqCShwEGysNfVJr0Y2rNFGwD95GMnbXwZR67x/C26v95xQxHmMZwgJvnqW+QFS9lM yo3w== X-Forwarded-Encrypted: i=1; AJvYcCXTQcmEi5ub79F7dBHc2q/BO3OMd8qlgAGEcWr6oyXfVQjLhzDgMDIx3bnbzun60YJZAG/ymYcjtj9R2+U=@vger.kernel.org X-Gm-Message-State: AOJu0YxJ7A+CjqSln1sWsw/ZXHzuDgIgZ7chsGX5aF1205dJo/gx7jZC s5MGgquM05CDXfOMZO8YuEu8NxfNnEG99bf+lDYj5ukNhbjWNr5q9TF0wI/BUndoeqNHrMdjny+ vXnG5beSvfA== X-Google-Smtp-Source: AGHT+IH77PgtCbJqxJY6j7wxvIM1OCk1GNbCoybLq2jRWIiFzzIPoEgt/LwNMf2l6xiRGSL/U3Zi+fPm3mUa X-Received: from dyek27.prod.google.com ([2002:a05:7300:641b:b0:2a4:4d2a:a9ba]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:28c:b0:294:f70d:5e33 with SMTP id d9443c01a7336-2984ed281b2mr9475375ad.12.1762896139956; Tue, 11 Nov 2025 13:22:19 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:49 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-2-irogers@google.com> Subject: [PATCH v4 01/18] perf metricgroup: Add care to picking the evsel for displaying a metric From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than using the first evsel in the matched events, try to find the least shared non-tool evsel. The aim is to pick the first evsel that typifies the metric within the list of metrics. This addresses an issue where Default metric group metrics may lose their counter value due to how the stat displaying hides counters for default event/metric output. For a metricgroup like TopdownL1 on an Intel Alderlake the change is, before there are 4 events with metrics: ``` $ perf stat -M topdownL1 -a sleep 1 Performance counter stats for 'system wide': 7,782,334,296 cpu_core/TOPDOWN.SLOTS/ # 10.4 % tma_= bad_speculation # 19.7 % tma_fronten= d_bound 2,668,927,977 cpu_core/topdown-retiring/ # 35.7 % tma_= backend_bound # 34.1 % tma_retiring 803,623,987 cpu_core/topdown-bad-spec/ 167,514,386 cpu_core/topdown-heavy-ops/ 1,555,265,776 cpu_core/topdown-fe-bound/ 2,792,733,013 cpu_core/topdown-be-bound/ 279,769,310 cpu_atom/TOPDOWN_RETIRING.ALL/ # 12.2 % tma_= retiring # 15.1 % tma_bad_spe= culation 457,917,232 cpu_atom/CPU_CLK_UNHALTED.CORE/ # 38.4 % tma_= backend_bound # 34.2 % tma_fronten= d_bound 783,519,226 cpu_atom/TOPDOWN_FE_BOUND.ALL/ 10,790,192 cpu_core/INT_MISC.UOP_DROPPING/ 879,845,633 cpu_atom/TOPDOWN_BE_BOUND.ALL/ ``` After there are 6 events with metrics: ``` $ perf stat -M topdownL1 -a sleep 1 Performance counter stats for 'system wide': 2,377,551,258 cpu_core/TOPDOWN.SLOTS/ # 7.9 % tma_= bad_speculation # 36.4 % tma_fronten= d_bound 480,791,142 cpu_core/topdown-retiring/ # 35.5 % tma_= backend_bound 186,323,991 cpu_core/topdown-bad-spec/ 65,070,590 cpu_core/topdown-heavy-ops/ # 20.1 % tma_= retiring 871,733,444 cpu_core/topdown-fe-bound/ 848,286,598 cpu_core/topdown-be-bound/ 260,936,456 cpu_atom/TOPDOWN_RETIRING.ALL/ # 12.4 % tma_= retiring # 17.6 % tma_bad_spe= culation 419,576,513 cpu_atom/CPU_CLK_UNHALTED.CORE/ 797,132,597 cpu_atom/TOPDOWN_FE_BOUND.ALL/ # 38.0 % tma_= frontend_bound 3,055,447 cpu_core/INT_MISC.UOP_DROPPING/ 671,014,164 cpu_atom/TOPDOWN_BE_BOUND.ALL/ # 32.0 % tma_= backend_bound ``` Signed-off-by: Ian Rogers --- tools/perf/util/metricgroup.c | 48 ++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 48936e517803..76092ee26761 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1323,6 +1323,51 @@ static int parse_ids(bool metric_no_merge, bool fake= _pmu, return ret; } =20 +/* How many times will a given evsel be used in a set of metrics? */ +static int count_uses(struct list_head *metric_list, struct evsel *evsel) +{ + const char *metric_id =3D evsel__metric_id(evsel); + struct metric *m; + int uses =3D 0; + + list_for_each_entry(m, metric_list, nd) { + if (hashmap__find(m->pctx->ids, metric_id, NULL)) + uses++; + } + return uses; +} + +/* + * Select the evsel that stat-display will use to trigger shadow/metric + * printing. Pick the least shared non-tool evsel, encouraging metrics to = be + * with a hardware counter that is specific to them. + */ +static struct evsel *pick_display_evsel(struct list_head *metric_list, + struct evsel **metric_events) +{ + struct evsel *selected =3D metric_events[0]; + size_t selected_uses; + bool selected_is_tool; + + if (!selected) + return NULL; + + selected_uses =3D count_uses(metric_list, selected); + selected_is_tool =3D evsel__is_tool(selected); + for (int i =3D 1; metric_events[i]; i++) { + struct evsel *candidate =3D metric_events[i]; + size_t candidate_uses =3D count_uses(metric_list, candidate); + + if ((selected_is_tool && !evsel__is_tool(candidate)) || + (candidate_uses < selected_uses)) { + selected =3D candidate; + selected_uses =3D candidate_uses; + selected_is_tool =3D evsel__is_tool(selected); + } + } + return selected; +} + static int parse_groups(struct evlist *perf_evlist, const char *pmu, const char *str, bool metric_no_group, @@ -1430,7 +1475,8 @@ static int parse_groups(struct evlist *perf_evlist, goto out; } =20 - me =3D metricgroup__lookup(&perf_evlist->metric_events, metric_events[0], + me =3D metricgroup__lookup(&perf_evlist->metric_events, + pick_display_evsel(&metric_list, metric_events), /*create=3D*/true); =20 expr =3D malloc(sizeof(struct metric_expr)); --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A67732695F for ; Tue, 11 Nov 2025 21:22:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762896144; cv=none; b=RKcWBCqzUjH2M6ufuxxYrecG8jCpm7H5fnYHaSba6+ISL/WrfFFFDKmIsir5siPWOMeB8N4p9ngzm+jOpzdiyTaAZ276zb3aFc5mIb6PZzpi7yzT5aACVFg4w9qag26pRk7atoMCkP8aYVSXzTf8KUQ7gpdlVecM0JmbCbh+U/I= ARC-Message-Signature: i=1; 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charset="utf-8" For CPU nanoseconds a lot of the stat-shadow metrics use either task-clock or cpu-clock, the latter being used when target__has_cpu. Add a #target_cpu literal so that json metrics can perform the same test. Signed-off-by: Ian Rogers --- tools/perf/util/expr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/perf/util/expr.c b/tools/perf/util/expr.c index 7fda0ff89c16..4df56f2b283d 100644 --- a/tools/perf/util/expr.c +++ b/tools/perf/util/expr.c @@ -409,6 +409,9 @@ double expr__get_literal(const char *literal, const str= uct expr_scanner_ctx *ctx } else if (!strcmp("#core_wide", literal)) { result =3D core_wide(ctx->system_wide, ctx->user_requested_cpu_list) ? 1.0 : 0.0; + } else if (!strcmp("#target_cpu", literal)) { + result =3D (ctx->system_wide || ctx->user_requested_cpu_list) + ? 1.0 : 0.0; } else { pr_err("Unrecognized literal '%s'", literal); } --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8658E326929 for ; Tue, 11 Nov 2025 21:22:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 11 Nov 2025 13:22:23 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:51 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-4-irogers@google.com> Subject: [PATCH v4 03/18] perf jevents: Add set of common metrics based on default ones From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to getting a common set of metrics from a default table. It simplifies the generation to add json metrics at the same time. The metrics added are CPUs_utilized, cs_per_second, migrations_per_second, page_faults_per_second, insn_per_cycle, stalled_cycles_per_instruction, frontend_cycles_idle, backend_cycles_idle, cycles_frequency, branch_frequency and branch_miss_rate based on the shadow metric definitions. Following this change the default perf stat output on an alderlake looks like: ``` $ perf stat -a -- sleep 2 Performance counter stats for 'system wide': 0.00 msec cpu-clock # 0.000 CPUs ut= ilized 77,739 context-switches 15,033 cpu-migrations 321,313 page-faults 14,355,634,225 cpu_atom/instructions/ # 1.40 insn pe= r cycle (35.37%) 134,561,560,583 cpu_core/instructions/ # 3.44 insn pe= r cycle (57.85%) 10,263,836,145 cpu_atom/cycles/ = (35.42%) 39,138,632,894 cpu_core/cycles/ = (57.60%) 2,989,658,777 cpu_atom/branches/ = (42.60%) 32,170,570,388 cpu_core/branches/ = (57.39%) 29,789,870 cpu_atom/branch-misses/ # 1.00% of all = branches (42.69%) 165,991,152 cpu_core/branch-misses/ # 0.52% of all = branches (57.19%) (software) # nan cs/sec cs_per= _second TopdownL1 (cpu_core) # 11.9 % tma_bad_spe= culation # 19.6 % tma_fronten= d_bound (63.97%) TopdownL1 (cpu_core) # 18.8 % tma_backend= _bound # 49.7 % tma_retirin= g (63.97%) (software) # nan faults/sec pa= ge_faults_per_second # nan GHz cycles_fr= equency (42.88%) # nan GHz cycles_fr= equency (69.88%) TopdownL1 (cpu_atom) # 11.7 % tma_bad_spe= culation # 29.9 % tma_retirin= g (50.07%) TopdownL1 (cpu_atom) # 31.3 % tma_fronten= d_bound (43.09%) (cpu_atom) # nan M/sec branch_= frequency (43.09%) # nan M/sec branch_= frequency (70.07%) # nan migrations/sec= migrations_per_second TopdownL1 (cpu_atom) # 27.1 % tma_backend= _bound (43.08%) (software) # 0.0 CPUs CPUs_uti= lized # 1.4 instructions = insn_per_cycle (43.04%) # 3.5 instructions = insn_per_cycle (69.99%) # 1.0 % branch_miss= _rate (35.46%) # 0.5 % branch_miss= _rate (65.02%) 2.005626564 seconds time elapsed ``` Signed-off-by: Ian Rogers --- .../arch/common/common/metrics.json | 86 +++++++++++++ tools/perf/pmu-events/empty-pmu-events.c | 115 +++++++++++++----- tools/perf/pmu-events/jevents.py | 21 +++- tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/util/metricgroup.c | 31 +++-- 5 files changed, 212 insertions(+), 42 deletions(-) create mode 100644 tools/perf/pmu-events/arch/common/common/metrics.json diff --git a/tools/perf/pmu-events/arch/common/common/metrics.json b/tools/= perf/pmu-events/arch/common/common/metrics.json new file mode 100644 index 000000000000..d915be51e300 --- /dev/null +++ b/tools/perf/pmu-events/arch/common/common/metrics.json @@ -0,0 +1,86 @@ +[ + { + "BriefDescription": "Average CPU utilization", + "MetricExpr": "(software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #t= arget_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@) / (duration_= time * 1e9)", + "MetricGroup": "Default", + "MetricName": "CPUs_utilized", + "ScaleUnit": "1CPUs", + "MetricConstraint": "NO_GROUP_EVENTS" + }, + { + "BriefDescription": "Context switches per CPU second", + "MetricExpr": "(software@context\\-switches\\,name\\=3Dcontext\\-s= witches@ * 1e9) / (software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_= cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)", + "MetricGroup": "Default", + "MetricName": "cs_per_second", + "ScaleUnit": "1cs/sec", + "MetricConstraint": "NO_GROUP_EVENTS" + }, + { + "BriefDescription": "Process migrations to a new CPU per CPU secon= d", + "MetricExpr": "(software@cpu\\-migrations\\,name\\=3Dcpu\\-migrati= ons@ * 1e9) / (software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu = else software@task\\-clock\\,name\\=3Dtask\\-clock@)", + "MetricGroup": "Default", + "MetricName": "migrations_per_second", + "ScaleUnit": "1migrations/sec", + "MetricConstraint": "NO_GROUP_EVENTS" + }, + { + "BriefDescription": "Page faults per CPU second", + "MetricExpr": "(software@page\\-faults\\,name\\=3Dpage\\-faults@ *= 1e9) / (software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else s= oftware@task\\-clock\\,name\\=3Dtask\\-clock@)", + "MetricGroup": "Default", + "MetricName": "page_faults_per_second", + "ScaleUnit": "1faults/sec", + "MetricConstraint": "NO_GROUP_EVENTS" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "instructions / cpu\\-cycles", + "MetricGroup": "Default", + "MetricName": "insn_per_cycle", + "MetricThreshold": "insn_per_cycle < 1", + "ScaleUnit": "1instructions" + }, + { + "BriefDescription": "Max front or backend stalls per instruction", + "MetricExpr": "max(stalled\\-cycles\\-frontend, stalled\\-cycles\\= -backend) / instructions", + "MetricGroup": "Default", + "MetricName": "stalled_cycles_per_instruction" + }, + { + "BriefDescription": "Frontend stalls per cycle", + "MetricExpr": "stalled\\-cycles\\-frontend / cpu\\-cycles", + "MetricGroup": "Default", + "MetricName": "frontend_cycles_idle", + "MetricThreshold": "frontend_cycles_idle > 0.1" + }, + { + "BriefDescription": "Backend stalls per cycle", + "MetricExpr": "stalled\\-cycles\\-backend / cpu\\-cycles", + "MetricGroup": "Default", + "MetricName": "backend_cycles_idle", + "MetricThreshold": "backend_cycles_idle > 0.2" + }, + { + "BriefDescription": "Cycles per CPU second", + "MetricExpr": "cpu\\-cycles / (software@cpu\\-clock\\,name\\=3Dcpu= \\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock= @)", + "MetricGroup": "Default", + "MetricName": "cycles_frequency", + "ScaleUnit": "1GHz", + "MetricConstraint": "NO_GROUP_EVENTS" + }, + { + "BriefDescription": "Branches per CPU second", + "MetricExpr": "branches / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)", + "MetricGroup": "Default", + "MetricName": "branch_frequency", + "ScaleUnit": "1000M/sec", + "MetricConstraint": "NO_GROUP_EVENTS" + }, + { + "BriefDescription": "Branch miss rate", + "MetricExpr": "branch\\-misses / branches", + "MetricGroup": "Default", + "MetricName": "branch_miss_rate", + "MetricThreshold": "branch_miss_rate > 0.05", + "ScaleUnit": "100%" + } +] diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 2fdf4fbf36e2..e4d00f6b2b5d 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -1303,21 +1303,32 @@ static const char *const big_c_string =3D /* offset=3D127519 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycle= s event\000config=3D0x2c\0000x01\00000\000\000\000\000\000" /* offset=3D127596 */ "uncore_sys_cmn_pmu\000" /* offset=3D127615 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts tota= l cache misses in first lookup result (high priority)\000eventid=3D1,type= =3D5\000(434|436|43c|43a).*\00000\000\000\000\000\000" -/* offset=3D127758 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 0" -/* offset=3D127780 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\00000" -/* offset=3D127843 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3D128009 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D128073 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D128140 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3D128211 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3D128305 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\00000" -/* offset=3D128439 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\00000" -/* offset=3D128503 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D128571 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D128641 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 0" -/* offset=3D128663 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 0" -/* offset=3D128685 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3D128705 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\00000" +/* offset=3D127758 */ "CPUs_utilized\000Default\000(software@cpu\\-clock\\= ,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\= =3Dtask\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\00= 0\0001CPUs\000\000\000\00001" +/* offset=3D127943 */ "cs_per_second\000Default\000software@context\\-swit= ches\\,name\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\= 00001" +/* offset=3D128175 */ "migrations_per_second\000Default\000software@cpu\\-= migrations\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,nam= e\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtas= k\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001m= igrations/sec\000\000\000\00001" +/* offset=3D128434 */ "page_faults_per_second\000Default\000software@page\= \-faults\\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\0= 0001" +/* offset=3D128664 */ "insn_per_cycle\000Default\000instructions / cpu\\-c= ycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\= 000\000\000\00000" +/* offset=3D128776 */ "stalled_cycles_per_instruction\000Default\000max(st= alled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\0= 00Max front or backend stalls per instruction\000\000\000\000\000\00000" +/* offset=3D128939 */ "frontend_cycles_idle\000Default\000stalled\\-cycles= \\-frontend / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls= per cycle\000\000\000\000\000\00000" +/* offset=3D129068 */ "backend_cycles_idle\000Default\000stalled\\-cycles\= \-backend / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per= cycle\000\000\000\000\000\00000" +/* offset=3D129193 */ "cycles_frequency\000Default\000cpu\\-cycles / (soft= ware@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\= \-clock\\,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\= 000\000\000\00001" +/* offset=3D129368 */ "branch_frequency\000Default\000branches / (software= @cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-cl= ock\\,name\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/s= ec\000\000\000\00001" +/* offset=3D129547 */ "branch_miss_rate\000Default\000branch\\-misses / br= anches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\0= 00\00000" +/* offset=3D129650 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 0" +/* offset=3D129672 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\00000" +/* offset=3D129735 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3D129901 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D129965 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D130032 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3D130103 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3D130197 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\00000" +/* offset=3D130331 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\00000" +/* offset=3D130395 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D130463 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D130533 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 0" +/* offset=3D130555 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 0" +/* offset=3D130577 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3D130597 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\00000" ; =20 static const struct compact_pmu_event pmu_events__common_default_core[] = =3D { @@ -2603,6 +2614,29 @@ static const struct pmu_table_entry pmu_events__comm= on[] =3D { }, }; =20 +static const struct compact_pmu_event pmu_metrics__common_default_core[] = =3D { +{ 127758 }, /* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPU= s\000\000\000\00001 */ +{ 129068 }, /* backend_cycles_idle\000Default\000stalled\\-cycles\\-backen= d / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per cycle\0= 00\000\000\000\000\00000 */ +{ 129368 }, /* branch_frequency\000Default\000branches / (software@cpu\\-c= lock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,na= me\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\0= 00\000\00001 */ +{ 129547 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\0= 00branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\00000= */ +{ 127943 }, /* cs_per_second\000Default\000software@context\\-switches\\,n= ame\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-= clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\= 000\000Context switches per CPU second\000\0001cs/sec\000\000\000\00001 */ +{ 129193 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu= \\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\= \,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\= 000\00001 */ +{ 128939 }, /* frontend_cycles_idle\000Default\000stalled\\-cycles\\-front= end / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls per cyc= le\000\000\000\000\000\00000 */ +{ 128664 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\00= 0insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\= 000\00000 */ +{ 128175 }, /* migrations_per_second\000Default\000software@cpu\\-migratio= ns\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcp= u\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-cloc= k@)\000\000Process migrations to a new CPU per CPU second\000\0001migration= s/sec\000\000\000\00001 */ +{ 128434 }, /* page_faults_per_second\000Default\000software@page\\-faults= \\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\0= 00\000Page faults per CPU second\000\0001faults/sec\000\000\000\00001 */ +{ 128776 }, /* stalled_cycles_per_instruction\000Default\000max(stalled\\-= cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\000Max fr= ont or backend stalls per instruction\000\000\000\000\000\00000 */ + +}; + +static const struct pmu_table_entry pmu_metrics__common[] =3D { +{ + .entries =3D pmu_metrics__common_default_core, + .num_entries =3D ARRAY_SIZE(pmu_metrics__common_default_core), + .pmu_name =3D { 0 /* default_core\000 */ }, +}, +}; + static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { { 126205 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event= =3D0x8a\000\00000\000\000\000\000\000 */ { 126267 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event= =3D0x8b\000\00000\000\000\000\000\000 */ @@ -2664,21 +2698,21 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_cpu[] =3D { }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 127758 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 128439 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\00000 */ -{ 128211 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 128305 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\00000 */ -{ 128503 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ -{ 128571 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\00000 */ -{ 127843 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 127780 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\00000 */ -{ 128705 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\00000 */ -{ 128641 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 128663 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 128685 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 128140 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\00000 */ -{ 128009 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\00000 */ -{ 128073 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\00000 */ +{ 129650 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 130331 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\00000 */ +{ 130103 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 130197 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\00000 */ +{ 130395 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ +{ 130463 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\00000 */ +{ 129735 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 129672 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\00000 */ +{ 130597 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\00000 */ +{ 130533 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 130555 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 130577 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 130032 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\00000 */ +{ 129901 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\00000 */ +{ 129965 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\00000 */ =20 }; =20 @@ -2759,7 +2793,10 @@ static const struct pmu_events_map pmu_events_map[] = =3D { .pmus =3D pmu_events__common, .num_pmus =3D ARRAY_SIZE(pmu_events__common), }, - .metric_table =3D {}, + .metric_table =3D { + .pmus =3D pmu_metrics__common, + .num_pmus =3D ARRAY_SIZE(pmu_metrics__common), + }, }, { .arch =3D "testarch", @@ -3208,6 +3245,22 @@ const struct pmu_metrics_table *pmu_metrics_table__f= ind(void) return map ? &map->metric_table : NULL; } =20 +const struct pmu_metrics_table *pmu_metrics_table__default(void) +{ + int i =3D 0; + + for (;;) { + const struct pmu_events_map *map =3D &pmu_events_map[i++]; + + if (!map->arch) + break; + + if (!strcmp(map->cpuid, "common")) + return &map->metric_table; + } + return NULL; +} + const struct pmu_events_table *find_core_events_table(const char *arch, co= nst char *cpuid) { for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 786a7049363f..5d3f4b44cfb7 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -755,7 +755,10 @@ static const struct pmu_events_map pmu_events_map[] = =3D { \t\t.pmus =3D pmu_events__common, \t\t.num_pmus =3D ARRAY_SIZE(pmu_events__common), \t}, -\t.metric_table =3D {}, +\t.metric_table =3D { +\t\t.pmus =3D pmu_metrics__common, +\t\t.num_pmus =3D ARRAY_SIZE(pmu_metrics__common), +\t}, }, """) else: @@ -1237,6 +1240,22 @@ const struct pmu_metrics_table *pmu_metrics_table__f= ind(void) return map ? &map->metric_table : NULL; } =20 +const struct pmu_metrics_table *pmu_metrics_table__default(void) +{ + int i =3D 0; + + for (;;) { + const struct pmu_events_map *map =3D &pmu_events_map[i++]; + + if (!map->arch) + break; + + if (!strcmp(map->cpuid, "common")) + return &map->metric_table; + } + return NULL; +} + const struct pmu_events_table *find_core_events_table(const char *arch, co= nst char *cpuid) { for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index e0535380c0b2..559265a903c8 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -127,6 +127,7 @@ int pmu_metrics_table__find_metric(const struct pmu_met= rics_table *table, const struct pmu_events_table *perf_pmu__find_events_table(struct perf_pmu= *pmu); const struct pmu_events_table *perf_pmu__default_core_events_table(void); const struct pmu_metrics_table *pmu_metrics_table__find(void); +const struct pmu_metrics_table *pmu_metrics_table__default(void); const struct pmu_events_table *find_core_events_table(const char *arch, co= nst char *cpuid); const struct pmu_metrics_table *find_core_metrics_table(const char *arch, = const char *cpuid); int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data); diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 76092ee26761..e67e04ce01c9 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -424,10 +424,18 @@ int metricgroup__for_each_metric(const struct pmu_met= rics_table *table, pmu_metr .fn =3D fn, .data =3D data, }; + const struct pmu_metrics_table *tables[2] =3D { + table, + pmu_metrics_table__default(), + }; + + for (size_t i =3D 0; i < ARRAY_SIZE(tables); i++) { + int ret; =20 - if (table) { - int ret =3D pmu_metrics_table__for_each_metric(table, fn, data); + if (!tables[i]) + continue; =20 + ret =3D pmu_metrics_table__for_each_metric(tables[i], fn, data); if (ret) return ret; } @@ -1581,19 +1589,22 @@ static int metricgroup__has_metric_or_groups_callba= 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Tue, 11 Nov 2025 13:22:25 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:52 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-5-irogers@google.com> Subject: [PATCH v4 04/18] perf jevents: Add metric DefaultShowEvents From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Default group metrics require their events showing for consistency with perf's previous behavior. Add a flag to indicate when this is the case and use it in stat-display. As events are coming from Default metrics remove that default hardware and software events from perf stat. Following this change the default perf stat output on an alderlake looks li= ke: ``` $ perf stat -a -- sleep 1 Performance counter stats for 'system wide': 20,550 context-switches # nan cs/sec = cs_per_second TopdownL1 (cpu_core) # 9.0 % tma_bad_spe= culation # 28.1 % tma_fronten= d_bound TopdownL1 (cpu_core) # 29.2 % tma_backend= _bound # 33.7 % tma_retiring 6,685 page-faults # nan faults/= sec page_faults_per_second 790,091,064 cpu_atom/cpu-cycles/ # nan GHz cycles_fr= equency (49.83%) 2,563,918,366 cpu_core/cpu-cycles/ # nan GHz cycles_fr= equency # 12.3 % tma_bad_spe= culation # 14.5 % tma_retirin= g (50.20%) # 33.8 % tma_fronten= d_bound (50.24%) 76,390,322 cpu_atom/branches/ # nan M/sec = branch_frequency (60.20%) 1,015,173,047 cpu_core/branches/ # nan M/sec = branch_frequency 1,325 cpu-migrations # nan migrati= ons/sec migrations_per_second # 39.3 % tma_backend= _bound (60.17%) 0.00 msec cpu-clock # 0.000 CPUs ut= ilized # 0.0 CPUs CPUs_uti= lized 554,347,072 cpu_atom/instructions/ # 0.64 insn pe= r cycle # 0.6 instructions = insn_per_cycle (60.14%) 5,228,931,991 cpu_core/instructions/ # 2.04 insn pe= r cycle # 2.0 instructions = insn_per_cycle 4,308,874 cpu_atom/branch-misses/ # 5.65% of all = branches # 5.6 % branch_miss= _rate (49.76%) 9,890,606 cpu_core/branch-misses/ # 0.97% of all = branches # 1.0 % branch_miss= _rate 1.005477803 seconds time elapsed ``` Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 42 +------ .../arch/common/common/metrics.json | 33 ++++-- tools/perf/pmu-events/empty-pmu-events.c | 106 +++++++++--------- tools/perf/pmu-events/jevents.py | 7 +- tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/util/evsel.h | 1 + tools/perf/util/metricgroup.c | 13 +++ tools/perf/util/stat-display.c | 4 +- tools/perf/util/stat-shadow.c | 2 +- 9 files changed, 102 insertions(+), 107 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 3c46b92a53ab..31c762695d4b 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1857,16 +1857,6 @@ static int perf_stat_init_aggr_mode_file(struct perf= _stat *st) return 0; } =20 -/* Add given software event to evlist without wildcarding. */ -static int parse_software_event(struct evlist *evlist, const char *event, - struct parse_events_error *err) -{ - char buf[256]; - - snprintf(buf, sizeof(buf), "software/%s,name=3D%s/", event, event); - return parse_events(evlist, buf, err); -} - /* Add legacy hardware/hardware-cache event to evlist for all core PMUs wi= thout wildcarding. */ static int parse_hardware_event(struct evlist *evlist, const char *event, struct parse_events_error *err) @@ -2011,36 +2001,10 @@ static int add_default_events(void) stat_config.topdown_level =3D 1; =20 if (!evlist->core.nr_entries && !evsel_list->core.nr_entries) { - /* No events so add defaults. */ - const char *sw_events[] =3D { - target__has_cpu(&target) ? "cpu-clock" : "task-clock", - "context-switches", - "cpu-migrations", - "page-faults", - }; - const char *hw_events[] =3D { - "instructions", - "cycles", - "stalled-cycles-frontend", - "stalled-cycles-backend", - "branches", - "branch-misses", - }; - - for (size_t i =3D 0; i < ARRAY_SIZE(sw_events); i++) { - ret =3D parse_software_event(evlist, sw_events[i], &err); - if (ret) - goto out; - } - for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { - ret =3D parse_hardware_event(evlist, hw_events[i], &err); - if (ret) - goto out; - } - /* - * Add TopdownL1 metrics if they exist. To minimize - * multiplexing, don't request threshold computation. + * Add Default metrics. To minimize multiplexing, don't request + * threshold computation, but it will be computed if the events + * are present. */ if (metricgroup__has_metric_or_groups(pmu, "Default")) { struct evlist *metric_evlist =3D evlist__new(); diff --git a/tools/perf/pmu-events/arch/common/common/metrics.json b/tools/= perf/pmu-events/arch/common/common/metrics.json index d915be51e300..d6ea967a4045 100644 --- a/tools/perf/pmu-events/arch/common/common/metrics.json +++ b/tools/perf/pmu-events/arch/common/common/metrics.json @@ -5,7 +5,8 @@ "MetricGroup": "Default", "MetricName": "CPUs_utilized", "ScaleUnit": "1CPUs", - "MetricConstraint": "NO_GROUP_EVENTS" + "MetricConstraint": "NO_GROUP_EVENTS", + "DefaultShowEvents": "1" }, { "BriefDescription": "Context switches per CPU second", @@ -13,7 +14,8 @@ "MetricGroup": "Default", "MetricName": "cs_per_second", "ScaleUnit": "1cs/sec", - "MetricConstraint": "NO_GROUP_EVENTS" + "MetricConstraint": "NO_GROUP_EVENTS", + "DefaultShowEvents": "1" }, { "BriefDescription": "Process migrations to a new CPU per CPU secon= d", @@ -21,7 +23,8 @@ "MetricGroup": "Default", "MetricName": "migrations_per_second", "ScaleUnit": "1migrations/sec", - "MetricConstraint": "NO_GROUP_EVENTS" + "MetricConstraint": "NO_GROUP_EVENTS", + "DefaultShowEvents": "1" }, { "BriefDescription": "Page faults per CPU second", @@ -29,7 +32,8 @@ "MetricGroup": "Default", "MetricName": "page_faults_per_second", "ScaleUnit": "1faults/sec", - "MetricConstraint": "NO_GROUP_EVENTS" + "MetricConstraint": "NO_GROUP_EVENTS", + "DefaultShowEvents": "1" }, { "BriefDescription": "Instructions Per Cycle", @@ -37,27 +41,31 @@ "MetricGroup": "Default", "MetricName": "insn_per_cycle", "MetricThreshold": "insn_per_cycle < 1", - "ScaleUnit": "1instructions" + "ScaleUnit": "1instructions", + "DefaultShowEvents": "1" }, { "BriefDescription": "Max front or backend stalls per instruction", "MetricExpr": "max(stalled\\-cycles\\-frontend, stalled\\-cycles\\= -backend) / instructions", "MetricGroup": "Default", - "MetricName": "stalled_cycles_per_instruction" + "MetricName": "stalled_cycles_per_instruction", + "DefaultShowEvents": "1" }, { "BriefDescription": "Frontend stalls per cycle", "MetricExpr": "stalled\\-cycles\\-frontend / cpu\\-cycles", "MetricGroup": "Default", "MetricName": "frontend_cycles_idle", - "MetricThreshold": "frontend_cycles_idle > 0.1" + "MetricThreshold": "frontend_cycles_idle > 0.1", + "DefaultShowEvents": "1" }, { "BriefDescription": "Backend stalls per cycle", "MetricExpr": "stalled\\-cycles\\-backend / cpu\\-cycles", "MetricGroup": "Default", "MetricName": "backend_cycles_idle", - "MetricThreshold": "backend_cycles_idle > 0.2" + "MetricThreshold": "backend_cycles_idle > 0.2", + "DefaultShowEvents": "1" }, { "BriefDescription": "Cycles per CPU second", @@ -65,7 +73,8 @@ "MetricGroup": "Default", "MetricName": "cycles_frequency", "ScaleUnit": "1GHz", - "MetricConstraint": "NO_GROUP_EVENTS" + "MetricConstraint": "NO_GROUP_EVENTS", + "DefaultShowEvents": "1" }, { "BriefDescription": "Branches per CPU second", @@ -73,7 +82,8 @@ "MetricGroup": "Default", "MetricName": "branch_frequency", "ScaleUnit": "1000M/sec", - "MetricConstraint": "NO_GROUP_EVENTS" + "MetricConstraint": "NO_GROUP_EVENTS", + "DefaultShowEvents": "1" }, { "BriefDescription": "Branch miss rate", @@ -81,6 +91,7 @@ "MetricGroup": "Default", "MetricName": "branch_miss_rate", "MetricThreshold": "branch_miss_rate > 0.05", - "ScaleUnit": "100%" + "ScaleUnit": "100%", + "DefaultShowEvents": "1" } ] diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index e4d00f6b2b5d..333a44930910 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -1303,32 +1303,32 @@ static const char *const big_c_string =3D /* offset=3D127519 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycle= s event\000config=3D0x2c\0000x01\00000\000\000\000\000\000" /* offset=3D127596 */ "uncore_sys_cmn_pmu\000" /* offset=3D127615 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts tota= l cache misses in first lookup result (high priority)\000eventid=3D1,type= =3D5\000(434|436|43c|43a).*\00000\000\000\000\000\000" -/* offset=3D127758 */ "CPUs_utilized\000Default\000(software@cpu\\-clock\\= ,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\= =3Dtask\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\00= 0\0001CPUs\000\000\000\00001" -/* offset=3D127943 */ "cs_per_second\000Default\000software@context\\-swit= ches\\,name\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\= 00001" -/* offset=3D128175 */ "migrations_per_second\000Default\000software@cpu\\-= migrations\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,nam= e\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtas= k\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001m= igrations/sec\000\000\000\00001" -/* offset=3D128434 */ "page_faults_per_second\000Default\000software@page\= \-faults\\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\0= 0001" -/* offset=3D128664 */ "insn_per_cycle\000Default\000instructions / cpu\\-c= ycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\= 000\000\000\00000" -/* offset=3D128776 */ "stalled_cycles_per_instruction\000Default\000max(st= alled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\0= 00Max front or backend stalls per instruction\000\000\000\000\000\00000" -/* offset=3D128939 */ "frontend_cycles_idle\000Default\000stalled\\-cycles= \\-frontend / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls= per cycle\000\000\000\000\000\00000" -/* offset=3D129068 */ "backend_cycles_idle\000Default\000stalled\\-cycles\= \-backend / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per= cycle\000\000\000\000\000\00000" -/* offset=3D129193 */ "cycles_frequency\000Default\000cpu\\-cycles / (soft= ware@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\= \-clock\\,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\= 000\000\000\00001" -/* offset=3D129368 */ "branch_frequency\000Default\000branches / (software= @cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-cl= ock\\,name\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/s= ec\000\000\000\00001" -/* offset=3D129547 */ "branch_miss_rate\000Default\000branch\\-misses / br= anches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\0= 00\00000" -/* offset=3D129650 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 0" -/* offset=3D129672 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\00000" -/* offset=3D129735 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3D129901 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D129965 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D130032 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3D130103 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3D130197 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\00000" -/* offset=3D130331 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\00000" -/* offset=3D130395 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D130463 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D130533 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 0" -/* offset=3D130555 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 0" -/* offset=3D130577 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3D130597 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\00000" +/* offset=3D127758 */ "CPUs_utilized\000Default\000(software@cpu\\-clock\\= ,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\= =3Dtask\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\00= 0\0001CPUs\000\000\000\000011" +/* offset=3D127944 */ "cs_per_second\000Default\000software@context\\-swit= ches\\,name\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\= 000011" +/* offset=3D128177 */ "migrations_per_second\000Default\000software@cpu\\-= migrations\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,nam= e\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtas= k\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001m= igrations/sec\000\000\000\000011" +/* offset=3D128437 */ "page_faults_per_second\000Default\000software@page\= \-faults\\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\0= 00011" +/* offset=3D128668 */ "insn_per_cycle\000Default\000instructions / cpu\\-c= ycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\= 000\000\000\000001" +/* offset=3D128781 */ "stalled_cycles_per_instruction\000Default\000max(st= alled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\0= 00Max front or backend stalls per instruction\000\000\000\000\000\000001" +/* offset=3D128945 */ "frontend_cycles_idle\000Default\000stalled\\-cycles= \\-frontend / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls= per cycle\000\000\000\000\000\000001" +/* offset=3D129075 */ "backend_cycles_idle\000Default\000stalled\\-cycles\= \-backend / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per= cycle\000\000\000\000\000\000001" +/* offset=3D129201 */ "cycles_frequency\000Default\000cpu\\-cycles / (soft= ware@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\= \-clock\\,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\= 000\000\000\000011" +/* offset=3D129377 */ "branch_frequency\000Default\000branches / (software= @cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-cl= ock\\,name\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/s= ec\000\000\000\000011" +/* offset=3D129557 */ "branch_miss_rate\000Default\000branch\\-misses / br= anches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\0= 00\000001" +/* offset=3D129661 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 00" +/* offset=3D129684 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\000000" +/* offset=3D129748 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000" +/* offset=3D129915 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\000000" +/* offset=3D129980 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\000000" +/* offset=3D130048 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\000000" +/* offset=3D130120 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000" +/* offset=3D130215 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\000000" +/* offset=3D130350 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\000000" +/* offset=3D130415 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\000000" +/* offset=3D130484 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\000000" +/* offset=3D130555 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 00" +/* offset=3D130578 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 00" +/* offset=3D130601 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\000000" +/* offset=3D130622 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\000000" ; =20 static const struct compact_pmu_event pmu_events__common_default_core[] = =3D { @@ -2615,17 +2615,17 @@ static const struct pmu_table_entry pmu_events__com= mon[] =3D { }; =20 static const struct compact_pmu_event pmu_metrics__common_default_core[] = =3D { -{ 127758 }, /* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPU= s\000\000\000\00001 */ -{ 129068 }, /* backend_cycles_idle\000Default\000stalled\\-cycles\\-backen= d / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per cycle\0= 00\000\000\000\000\00000 */ -{ 129368 }, /* branch_frequency\000Default\000branches / (software@cpu\\-c= lock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,na= me\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\0= 00\000\00001 */ -{ 129547 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\0= 00branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\00000= */ -{ 127943 }, /* cs_per_second\000Default\000software@context\\-switches\\,n= ame\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-= clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\= 000\000Context switches per CPU second\000\0001cs/sec\000\000\000\00001 */ -{ 129193 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu= \\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\= \,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\= 000\00001 */ -{ 128939 }, /* frontend_cycles_idle\000Default\000stalled\\-cycles\\-front= end / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls per cyc= le\000\000\000\000\000\00000 */ -{ 128664 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\00= 0insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\= 000\00000 */ -{ 128175 }, /* migrations_per_second\000Default\000software@cpu\\-migratio= ns\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcp= u\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-cloc= k@)\000\000Process migrations to a new CPU per CPU second\000\0001migration= s/sec\000\000\000\00001 */ -{ 128434 }, /* page_faults_per_second\000Default\000software@page\\-faults= \\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\0= 00\000Page faults per CPU second\000\0001faults/sec\000\000\000\00001 */ -{ 128776 }, /* stalled_cycles_per_instruction\000Default\000max(stalled\\-= cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\000Max fr= ont or backend stalls per instruction\000\000\000\000\000\00000 */ +{ 127758 }, /* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPU= s\000\000\000\000011 */ +{ 129075 }, /* backend_cycles_idle\000Default\000stalled\\-cycles\\-backen= d / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per cycle\0= 00\000\000\000\000\000001 */ +{ 129377 }, /* branch_frequency\000Default\000branches / (software@cpu\\-c= lock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,na= me\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\0= 00\000\000011 */ +{ 129557 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\0= 00branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\00000= 1 */ +{ 127944 }, /* cs_per_second\000Default\000software@context\\-switches\\,n= ame\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-= clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\= 000\000Context switches per CPU second\000\0001cs/sec\000\000\000\000011 */ +{ 129201 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu= \\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\= \,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\= 000\000011 */ +{ 128945 }, /* frontend_cycles_idle\000Default\000stalled\\-cycles\\-front= end / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls per cyc= le\000\000\000\000\000\000001 */ +{ 128668 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\00= 0insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\= 000\000001 */ +{ 128177 }, /* migrations_per_second\000Default\000software@cpu\\-migratio= ns\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcp= u\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-cloc= k@)\000\000Process migrations to a new CPU per CPU second\000\0001migration= s/sec\000\000\000\000011 */ +{ 128437 }, /* page_faults_per_second\000Default\000software@page\\-faults= \\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\0= 00\000Page faults per CPU second\000\0001faults/sec\000\000\000\000011 */ +{ 128781 }, /* stalled_cycles_per_instruction\000Default\000max(stalled\\-= cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\000Max fr= ont or backend stalls per instruction\000\000\000\000\000\000001 */ =20 }; =20 @@ -2698,21 +2698,21 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_cpu[] =3D { }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 129650 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 130331 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\00000 */ -{ 130103 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 130197 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\00000 */ -{ 130395 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ -{ 130463 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\00000 */ -{ 129735 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 129672 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\00000 */ -{ 130597 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\00000 */ -{ 130533 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 130555 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 130577 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 130032 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\00000 */ -{ 129901 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\00000 */ -{ 129965 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\00000 */ +{ 129661 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */ +{ 130350 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\000000 */ +{ 130120 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000 */ +{ 130215 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\000000 */ +{ 130415 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\000000 */ +{ 130484 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\000000 */ +{ 129748 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000 */ +{ 129684 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\000000 */ +{ 130622 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\000000 */ +{ 130555 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */ +{ 130578 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */ +{ 130601 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */ +{ 130048 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\000000 */ +{ 129915 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\000000 */ +{ 129980 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\000000 */ =20 }; =20 @@ -2894,6 +2894,8 @@ static void decompress_metric(int offset, struct pmu_= metric *pm) pm->aggr_mode =3D *p - '0'; p++; pm->event_grouping =3D *p - '0'; + p++; + pm->default_show_events =3D *p - '0'; } =20 static int pmu_events_table__for_each_event_pmu(const struct pmu_events_ta= ble *table, diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 5d3f4b44cfb7..3413ee5d0227 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -58,10 +58,12 @@ _json_event_attributes =3D [ _json_metric_attributes =3D [ 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', 'desc', 'long_desc', 'unit', 'compat', 'metricgroup_no_group', - 'default_metricgroup_name', 'aggr_mode', 'event_grouping' + 'default_metricgroup_name', 'aggr_mode', 'event_grouping', + 'default_show_events' ] # Attributes that are bools or enum int values, encoded as '0', '1',... -_json_enum_attributes =3D ['aggr_mode', 'deprecated', 'event_grouping', 'p= erpkg'] +_json_enum_attributes =3D ['aggr_mode', 'deprecated', 'event_grouping', 'p= erpkg', + 'default_show_events'] =20 def removesuffix(s: str, suffix: str) -> str: """Remove the suffix from a string @@ -356,6 +358,7 @@ class JsonEvent: self.metricgroup_no_group =3D jd.get('MetricgroupNoGroup') self.default_metricgroup_name =3D jd.get('DefaultMetricgroupName') self.event_grouping =3D convert_metric_constraint(jd.get('MetricConstr= aint')) + self.default_show_events =3D jd.get('DefaultShowEvents') self.metric_expr =3D None if 'MetricExpr' in jd: self.metric_expr =3D metric.ParsePerfJson(jd['MetricExpr']).Simplify= () diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index 559265a903c8..d3b24014c6ff 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -74,6 +74,7 @@ struct pmu_metric { const char *default_metricgroup_name; enum aggr_mode_class aggr_mode; enum metric_event_groups event_grouping; + bool default_show_events; }; =20 struct pmu_events_table; diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 71f74c7036ef..3ae4ac8f9a37 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -122,6 +122,7 @@ struct evsel { bool reset_group; bool needs_auxtrace_mmap; bool default_metricgroup; /* A member of the Default metricgroup */ + bool default_show_events; /* If a default group member, show the event = */ bool needs_uniquify; struct hashmap *per_pkg_mask; int err; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index e67e04ce01c9..25c75fdbfc52 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -152,6 +152,8 @@ struct metric { * Should events of the metric be grouped? */ bool group_events; + /** Show events even if in the Default metric group. */ + bool default_show_events; /** * Parsed events for the metric. Optional as events may be taken from a * different metric whose group contains all the IDs necessary for this @@ -255,6 +257,7 @@ static struct metric *metric__new(const struct pmu_metr= ic *pm, m->pctx->sctx.runtime =3D runtime; m->pctx->sctx.system_wide =3D system_wide; m->group_events =3D !metric_no_group && metric__group_events(pm, metric_n= o_threshold); + m->default_show_events =3D pm->default_show_events; m->metric_refs =3D NULL; m->evlist =3D NULL; =20 @@ -1513,6 +1516,16 @@ static int parse_groups(struct evlist *perf_evlist, free(metric_events); goto out; } + if (m->default_show_events) { + struct evsel *pos; + + for (int i =3D 0; metric_events[i]; i++) + metric_events[i]->default_show_events =3D true; + evlist__for_each_entry(metric_evlist, pos) { + if (pos->metric_leader && pos->metric_leader->default_show_events) + pos->default_show_events =3D true; + } + } expr->metric_threshold =3D m->metric_threshold; expr->metric_unit =3D m->metric_unit; expr->metric_events =3D metric_events; diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index a67b991f4e81..4d0e353846ea 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -872,7 +872,7 @@ static void printout(struct perf_stat_config *config, s= truct outstate *os, out.ctx =3D os; out.force_header =3D false; =20 - if (!config->metric_only && !counter->default_metricgroup) { + if (!config->metric_only && (!counter->default_metricgroup || counter->de= fault_show_events)) { abs_printout(config, os, os->id, os->aggr_nr, counter, uval, ok); =20 print_noise(config, os, counter, noise, /*before_metric=3D*/true); @@ -880,7 +880,7 @@ static void printout(struct perf_stat_config *config, s= truct outstate *os, } =20 if (ok) { - if (!config->metric_only && counter->default_metricgroup) { + if (!config->metric_only && counter->default_metricgroup && !counter->de= fault_show_events) { void *from =3D NULL; =20 aggr_printout(config, os, os->evsel, os->id, os->aggr_nr); diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index abaf6b579bfc..4df614f8e200 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -665,7 +665,7 @@ void *perf_stat__print_shadow_stats_metricgroup(struct = perf_stat_config *config, if (strcmp(name, mexp->default_metricgroup_name)) return (void *)mexp; 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Tue, 11 Nov 2025 13:22:27 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:53 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-6-irogers@google.com> Subject: [PATCH v4 05/18] perf stat: Add detail -d,-dd,-ddd metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add metrics for the stat-shadow -d, -dd and -ddd events and hard coded metrics. Remove the events as these now come from the metrics. Following this change a detailed perf stat output looks like: ``` $ perf stat -a -ddd -- sleep 1 Performance counter stats for 'system wide': 21,089 context-switches # nan cs/sec = cs_per_second TopdownL1 (cpu_core) # 14.1 % tma_bad_spe= culation # 27.3 % tma_fronten= d_bound (30.56%) TopdownL1 (cpu_core) # 31.5 % tma_backend= _bound # 27.2 % tma_retirin= g (30.56%) 6,302 page-faults # nan faults/= sec page_faults_per_second 928,495,163 cpu_atom/cpu-cycles/ # nan GHz cycles_fr= equency (28.41%) 1,841,409,834 cpu_core/cpu-cycles/ # nan GHz cycles_fr= equency (38.51%) # 14.5 % tma_bad_spe= culation # 16.0 % tma_retirin= g (28.41%) # 36.8 % tma_fronten= d_bound (35.57%) 100,859,118 cpu_atom/branches/ # nan M/sec = branch_frequency (42.73%) 572,657,734 cpu_core/branches/ # nan M/sec = branch_frequency (54.43%) 1,527 cpu-migrations # nan migrati= ons/sec migrations_per_second # 32.7 % tma_backend= _bound (42.73%) 0.00 msec cpu-clock # 0.000 CPUs ut= ilized # 0.0 CPUs CPUs_uti= lized 498,668,509 cpu_atom/instructions/ # 0.57 insn pe= r cycle # 0.6 instructions = insn_per_cycle (42.97%) 3,281,762,225 cpu_core/instructions/ # 1.84 insn pe= r cycle # 1.8 instructions = insn_per_cycle (62.20%) 4,919,511 cpu_atom/branch-misses/ # 5.43% of all = branches # 5.4 % branch_miss= _rate (35.80%) 7,431,776 cpu_core/branch-misses/ # 1.39% of all = branches # 1.4 % branch_miss= _rate (62.20%) 2,517,007 cpu_atom/LLC-loads/ # 0.1 % llc_= miss_rate (28.62%) 3,931,318 cpu_core/LLC-loads/ # 40.4 % llc_= miss_rate (45.98%) 14,918,674 cpu_core/L1-dcache-load-misses/ # 2.25% of all = L1-dcache accesses # nan % l1d_miss_ra= te (37.80%) 27,067,264 cpu_atom/L1-icache-load-misses/ # 15.92% of all = L1-icache accesses # 15.9 % l1i_miss_ra= te (21.47%) 116,848,994 cpu_atom/dTLB-loads/ # 0.8 % dtlb= _miss_rate (21.47%) 764,870,407 cpu_core/dTLB-loads/ # 0.1 % dtlb= _miss_rate (15.12%) 1.006181526 seconds time elapsed ``` Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 100 +++--------------- .../arch/common/common/metrics.json | 54 ++++++++++ tools/perf/pmu-events/empty-pmu-events.c | 72 +++++++------ 3 files changed, 113 insertions(+), 113 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 31c762695d4b..7862094b93c8 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1857,28 +1857,6 @@ static int perf_stat_init_aggr_mode_file(struct perf= _stat *st) return 0; } =20 -/* Add legacy hardware/hardware-cache event to evlist for all core PMUs wi= thout wildcarding. */ -static int parse_hardware_event(struct evlist *evlist, const char *event, - struct parse_events_error *err) -{ - char buf[256]; - struct perf_pmu *pmu =3D NULL; - - while ((pmu =3D perf_pmus__scan_core(pmu)) !=3D NULL) { - int ret; - - if (perf_pmus__num_core_pmus() =3D=3D 1) - snprintf(buf, sizeof(buf), "%s/%s,name=3D%s/", pmu->name, event, event); - else - snprintf(buf, sizeof(buf), "%s/%s/", pmu->name, event); - - ret =3D parse_events(evlist, buf, err); - if (ret) - return ret; - } - return 0; -} - /* * Add default events, if there were no attributes specified or * if -d/--detailed, -d -d or -d -d -d is used: @@ -2006,22 +1984,34 @@ static int add_default_events(void) * threshold computation, but it will be computed if the events * are present. */ - if (metricgroup__has_metric_or_groups(pmu, "Default")) { - struct evlist *metric_evlist =3D evlist__new(); + const char *default_metricgroup_names[] =3D { + "Default", "Default2", "Default3", "Default4", + }; + + for (size_t i =3D 0; i < ARRAY_SIZE(default_metricgroup_names); i++) { + struct evlist *metric_evlist; + + if (!metricgroup__has_metric_or_groups(pmu, default_metricgroup_names[i= ])) + continue; + + if ((int)i > detailed_run) + break; =20 + metric_evlist =3D evlist__new(); if (!metric_evlist) { ret =3D -ENOMEM; - goto out; + break; } - if (metricgroup__parse_groups(metric_evlist, pmu, "Default", + if (metricgroup__parse_groups(metric_evlist, pmu, default_metricgroup_n= ames[i], /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/true, stat_config.user_requested_cpu_list, stat_config.system_wide, stat_config.hardware_aware_grouping) < 0) { + evlist__delete(metric_evlist); ret =3D -1; - goto out; + break; } =20 evlist__for_each_entry(metric_evlist, evsel) @@ -2034,62 +2024,6 @@ static int add_default_events(void) evlist__delete(metric_evlist); } } - - /* Detailed events get appended to the event list: */ - - if (!ret && detailed_run >=3D 1) { - /* - * Detailed stats (-d), covering the L1 and last level data - * caches: - */ - const char *hw_events[] =3D { - "L1-dcache-loads", - "L1-dcache-load-misses", - "LLC-loads", - "LLC-load-misses", - }; - - for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { - ret =3D parse_hardware_event(evlist, hw_events[i], &err); - if (ret) - goto out; - } - } - if (!ret && detailed_run >=3D 2) { - /* - * Very detailed stats (-d -d), covering the instruction cache - * and the TLB caches: - */ - const char *hw_events[] =3D { - "L1-icache-loads", - "L1-icache-load-misses", - "dTLB-loads", - "dTLB-load-misses", - "iTLB-loads", - "iTLB-load-misses", - }; - - for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { - ret =3D parse_hardware_event(evlist, hw_events[i], &err); - if (ret) - goto out; - } - } - if (!ret && detailed_run >=3D 3) { - /* - * Very, very detailed stats (-d -d -d), adding prefetch events: - */ - const char *hw_events[] =3D { - "L1-dcache-prefetches", - "L1-dcache-prefetch-misses", - }; - - for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { - ret =3D parse_hardware_event(evlist, hw_events[i], &err); - if (ret) - goto out; - } - } out: if (!ret) { evlist__for_each_entry(evlist, evsel) { diff --git a/tools/perf/pmu-events/arch/common/common/metrics.json b/tools/= perf/pmu-events/arch/common/common/metrics.json index d6ea967a4045..0d010b3ebc6d 100644 --- a/tools/perf/pmu-events/arch/common/common/metrics.json +++ b/tools/perf/pmu-events/arch/common/common/metrics.json @@ -93,5 +93,59 @@ "MetricThreshold": "branch_miss_rate > 0.05", "ScaleUnit": "100%", "DefaultShowEvents": "1" + }, + { + "BriefDescription": "L1D miss rate", + "MetricExpr": "L1\\-dcache\\-load\\-misses / L1\\-dcache\\-loads", + "MetricGroup": "Default2", + "MetricName": "l1d_miss_rate", + "MetricThreshold": "l1d_miss_rate > 0.05", + "ScaleUnit": "100%", + "DefaultShowEvents": "1" + }, + { + "BriefDescription": "LLC miss rate", + "MetricExpr": "LLC\\-load\\-misses / LLC\\-loads", + "MetricGroup": "Default2", + "MetricName": "llc_miss_rate", + "MetricThreshold": "llc_miss_rate > 0.05", + "ScaleUnit": "100%", + "DefaultShowEvents": "1" + }, + { + "BriefDescription": "L1I miss rate", + "MetricExpr": "L1\\-icache\\-load\\-misses / L1\\-icache\\-loads", + "MetricGroup": "Default3", + "MetricName": "l1i_miss_rate", + "MetricThreshold": "l1i_miss_rate > 0.05", + "ScaleUnit": "100%", + "DefaultShowEvents": "1" + }, + { + "BriefDescription": "dTLB miss rate", + "MetricExpr": "dTLB\\-load\\-misses / dTLB\\-loads", + "MetricGroup": "Default3", + "MetricName": "dtlb_miss_rate", + "MetricThreshold": "dtlb_miss_rate > 0.05", + "ScaleUnit": "100%", + "DefaultShowEvents": "1" + }, + { + "BriefDescription": "iTLB miss rate", + "MetricExpr": "iTLB\\-load\\-misses / iTLB\\-loads", + "MetricGroup": "Default3", + "MetricName": "itlb_miss_rate", + "MetricThreshold": "itlb_miss_rate > 0.05", + "ScaleUnit": "100%", + "DefaultShowEvents": "1" + }, + { + "BriefDescription": "L1 prefetch miss rate", + "MetricExpr": "L1\\-dcache\\-prefetch\\-misses / L1\\-dcache\\-pre= fetches", + "MetricGroup": "Default4", + "MetricName": "l1_prefetch_miss_rate", + "MetricThreshold": "l1_prefetch_miss_rate > 0.05", + "ScaleUnit": "100%", + "DefaultShowEvents": "1" } ] diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 333a44930910..7fa42f13300f 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -1314,21 +1314,27 @@ static const char *const big_c_string =3D /* offset=3D129201 */ "cycles_frequency\000Default\000cpu\\-cycles / (soft= ware@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\= \-clock\\,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\= 000\000\000\000011" /* offset=3D129377 */ "branch_frequency\000Default\000branches / (software= @cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-cl= ock\\,name\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/s= ec\000\000\000\000011" /* offset=3D129557 */ "branch_miss_rate\000Default\000branch\\-misses / br= anches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\0= 00\000001" -/* offset=3D129661 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 00" -/* offset=3D129684 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\000000" -/* offset=3D129748 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000" -/* offset=3D129915 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\000000" -/* offset=3D129980 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\000000" -/* offset=3D130048 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\000000" -/* offset=3D130120 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000" -/* offset=3D130215 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\000000" -/* offset=3D130350 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\000000" -/* offset=3D130415 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\000000" -/* offset=3D130484 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\000000" -/* offset=3D130555 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 00" -/* offset=3D130578 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 00" -/* offset=3D130601 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\000000" -/* offset=3D130622 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\000000" +/* offset=3D129661 */ "l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-m= isses / L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\0= 00100%\000\000\000\000001" +/* offset=3D129777 */ "llc_miss_rate\000Default2\000LLC\\-load\\-misses / = LLC\\-loads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\00= 0\000001" +/* offset=3D129878 */ "l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-m= isses / L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\00= 0100%\000\000\000\000001" +/* offset=3D129993 */ "dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses = / dTLB\\-loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\0= 00\000\000001" +/* offset=3D130099 */ "itlb_miss_rate\000Default3\000iTLB\\-load\\-misses = / iTLB\\-loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\0= 00\000\000001" +/* offset=3D130205 */ "l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-= prefetch\\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.0= 5\000L1 prefetch miss rate\000\000100%\000\000\000\000001" +/* offset=3D130353 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 00" +/* offset=3D130376 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\000000" +/* offset=3D130440 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000" +/* offset=3D130607 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\000000" +/* offset=3D130672 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\000000" +/* offset=3D130740 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\000000" +/* offset=3D130812 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000" +/* offset=3D130907 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\000000" +/* offset=3D131042 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\000000" +/* offset=3D131107 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\000000" +/* offset=3D131176 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\000000" +/* offset=3D131247 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 00" +/* offset=3D131270 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 00" +/* offset=3D131293 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\000000" +/* offset=3D131314 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\000000" ; =20 static const struct compact_pmu_event pmu_events__common_default_core[] = =3D { @@ -2621,8 +2627,14 @@ static const struct compact_pmu_event pmu_metrics__c= ommon_default_core[] =3D { { 129557 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\0= 00branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\00000= 1 */ { 127944 }, /* cs_per_second\000Default\000software@context\\-switches\\,n= ame\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-= clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\= 000\000Context switches per CPU second\000\0001cs/sec\000\000\000\000011 */ { 129201 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu= \\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\= \,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\= 000\000011 */ +{ 129993 }, /* dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\= -loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\000\000\0= 00001 */ { 128945 }, /* frontend_cycles_idle\000Default\000stalled\\-cycles\\-front= end / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls per cyc= le\000\000\000\000\000\000001 */ { 128668 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\00= 0insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\= 000\000001 */ +{ 130099 }, /* itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\= -loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\000\000\0= 00001 */ +{ 130205 }, /* l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch= \\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.05\000L1 = prefetch miss rate\000\000100%\000\000\000\000001 */ +{ 129661 }, /* l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / = L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\000100%\0= 00\000\000\000001 */ +{ 129878 }, /* l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / = L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\000100%\00= 0\000\000\000001 */ +{ 129777 }, /* llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-lo= ads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\000\000001= */ { 128177 }, /* migrations_per_second\000Default\000software@cpu\\-migratio= ns\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcp= u\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-cloc= k@)\000\000Process migrations to a new CPU per CPU second\000\0001migration= s/sec\000\000\000\000011 */ { 128437 }, /* page_faults_per_second\000Default\000software@page\\-faults= \\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\0= 00\000Page faults per CPU second\000\0001faults/sec\000\000\000\000011 */ { 128781 }, /* stalled_cycles_per_instruction\000Default\000max(stalled\\-= cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\000Max fr= ont or backend stalls per instruction\000\000\000\000\000\000001 */ @@ -2698,21 +2710,21 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_cpu[] =3D { }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 129661 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */ -{ 130350 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\000000 */ -{ 130120 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000 */ -{ 130215 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\000000 */ -{ 130415 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\000000 */ -{ 130484 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\000000 */ -{ 129748 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000 */ -{ 129684 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\000000 */ -{ 130622 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\000000 */ -{ 130555 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */ -{ 130578 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */ -{ 130601 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */ -{ 130048 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\000000 */ -{ 129915 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\000000 */ -{ 129980 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\000000 */ +{ 130353 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */ +{ 131042 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\000000 */ +{ 130812 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000 */ +{ 130907 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\000000 */ +{ 131107 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\000000 */ +{ 131176 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\000000 */ +{ 130440 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000 */ +{ 130376 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\000000 */ +{ 131314 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\000000 */ +{ 131247 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */ +{ 131270 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */ +{ 131293 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */ +{ 130740 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\000000 */ +{ 130607 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\000000 */ +{ 130672 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\000000 */ =20 }; =20 --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher 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<20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-7-irogers@google.com> Subject: [PATCH v4 06/18] perf script: Change metric format to use json metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The metric format option isn't properly supported. This change improves that by making the sample events update the counts of an evsel, where the shadow metric code expects to read the values. To support printing metrics, metrics need to be found. This is done on the first attempt to print a metric. Every metric is parsed and then the evsels in the metric's evlist compared to those in perf script using the perf_event_attr type and config. If the metric matches then it is added for printing. As an event in the perf script's evlist may have >1 metric id, or different leader for aggregation, the first metric matched will be displayed in those cases. An example use is: ``` $ perf record -a -e '{instructions,cpu-cycles}:S' -a -- sleep 1 $ perf script -F period,metric ... 867817 metric: 0.30 insn per cycle 125394 metric: 0.04 insn per cycle 313516 metric: 0.11 insn per cycle metric: 1.00 insn per cycle ``` Signed-off-by: Ian Rogers --- tools/perf/builtin-script.c | 252 ++++++++++++++++++++++++++++++++---- 1 file changed, 230 insertions(+), 22 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index d813adbf9889..8bab5b264f61 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -33,6 +33,7 @@ #include "util/path.h" #include "util/event.h" #include "util/mem-info.h" +#include "util/metricgroup.h" #include "ui/ui.h" #include "print_binary.h" #include "print_insn.h" @@ -341,9 +342,6 @@ struct evsel_script { char *filename; FILE *fp; u64 samples; - /* For metric output */ - u64 val; - int gnum; }; =20 static inline struct evsel_script *evsel_script(struct evsel *evsel) @@ -2132,13 +2130,161 @@ static void script_new_line(struct perf_stat_confi= g *config __maybe_unused, fputs("\tmetric: ", mctx->fp); } =20 -static void perf_sample__fprint_metric(struct perf_script *script, - struct thread *thread, +struct script_find_metrics_args { + struct evlist *evlist; + bool system_wide; +}; + +static struct evsel *map_metric_evsel_to_script_evsel(struct evlist *scrip= t_evlist, + struct evsel *metric_evsel) +{ + struct evsel *script_evsel; + + evlist__for_each_entry(script_evlist, script_evsel) { + /* Skip if perf_event_attr differ. */ + if (metric_evsel->core.attr.type !=3D script_evsel->core.attr.type) + continue; + if (metric_evsel->core.attr.config !=3D script_evsel->core.attr.config) + continue; + /* Skip if the script event has a metric_id that doesn't match. */ + if (script_evsel->metric_id && + strcmp(evsel__metric_id(metric_evsel), evsel__metric_id(script_evsel= ))) { + pr_debug("Skipping matching evsel due to differing metric ids '%s' vs '= %s'\n", + evsel__metric_id(metric_evsel), evsel__metric_id(script_evsel)); + continue; + } + return script_evsel; + } + return NULL; +} + +static int script_find_metrics(const struct pmu_metric *pm, + const struct pmu_metrics_table *table __maybe_unused, + void *data) +{ + struct script_find_metrics_args *args =3D data; + struct evlist *script_evlist =3D args->evlist; + struct evlist *metric_evlist =3D evlist__new(); + struct evsel *metric_evsel; + int ret =3D metricgroup__parse_groups(metric_evlist, + /*pmu=3D*/"all", + pm->metric_name, + /*metric_no_group=3D*/false, + /*metric_no_merge=3D*/false, + /*metric_no_threshold=3D*/true, + /*user_requested_cpu_list=3D*/NULL, + args->system_wide, + /*hardware_aware_grouping=3D*/false); + + if (ret) { + /* Metric parsing failed but continue the search. */ + goto out; + } + + /* + * Check the script_evlist has an entry for each metric_evlist entry. If + * the script evsel was already set up avoid changing data that may + * break it. + */ + evlist__for_each_entry(metric_evlist, metric_evsel) { + struct evsel *script_evsel =3D + map_metric_evsel_to_script_evsel(script_evlist, metric_evsel); + struct evsel *new_metric_leader; + + if (!script_evsel) { + pr_debug("Skipping metric '%s' as evsel '%s' / '%s' is missing\n", + pm->metric_name, evsel__name(metric_evsel), + evsel__metric_id(metric_evsel)); + goto out; + } + + if (script_evsel->metric_leader =3D=3D NULL) + continue; + + if (metric_evsel->metric_leader =3D=3D metric_evsel) { + new_metric_leader =3D script_evsel; + } else { + new_metric_leader =3D + map_metric_evsel_to_script_evsel(script_evlist, + metric_evsel->metric_leader); + } + /* Mismatching evsel leaders. */ + if (script_evsel->metric_leader !=3D new_metric_leader) { + pr_debug("Skipping metric '%s' due to mismatching evsel metric leaders = '%s' vs '%s'\n", + pm->metric_name, evsel__metric_id(metric_evsel), + evsel__metric_id(script_evsel)); + goto out; + } + } + /* + * Metric events match those in the script evlist, copy metric evsel + * data into the script evlist. + */ + evlist__for_each_entry(metric_evlist, metric_evsel) { + struct evsel *script_evsel =3D + map_metric_evsel_to_script_evsel(script_evlist, metric_evsel); + struct metric_event *metric_me =3D metricgroup__lookup(&metric_evlist->m= etric_events, + metric_evsel, + /*create=3D*/false); + + if (script_evsel->metric_id =3D=3D NULL) { + script_evsel->metric_id =3D metric_evsel->metric_id; + metric_evsel->metric_id =3D NULL; + } + + if (script_evsel->metric_leader =3D=3D NULL) { + if (metric_evsel->metric_leader =3D=3D metric_evsel) { + script_evsel->metric_leader =3D script_evsel; + } else { + script_evsel->metric_leader =3D + map_metric_evsel_to_script_evsel(script_evlist, + metric_evsel->metric_leader); + } + } + + if (metric_me) { + struct metric_expr *expr; + struct metric_event *script_me =3D + metricgroup__lookup(&script_evlist->metric_events, + script_evsel, + /*create=3D*/true); + + if (!script_me) { + /* + * As the metric_expr is created, the only + * failure is a lack of memory. + */ + goto out; + } + list_splice_init(&metric_me->head, &script_me->head); + list_for_each_entry(expr, &script_me->head, nd) { + for (int i =3D 0; expr->metric_events[i]; i++) { + expr->metric_events[i] =3D + map_metric_evsel_to_script_evsel(script_evlist, + expr->metric_events[i]); + } + } + } + } + pr_debug("Found metric '%s' whose evsels match those of in the perf data\= n", + pm->metric_name); + evlist__delete(metric_evlist); +out: + return 0; +} + +static struct aggr_cpu_id script_aggr_cpu_id_get(struct perf_stat_config *= config __maybe_unused, + struct perf_cpu cpu) +{ + return aggr_cpu_id__global(cpu, /*data=3D*/NULL); +} + +static void perf_sample__fprint_metric(struct thread *thread, struct evsel *evsel, struct perf_sample *sample, FILE *fp) { - struct evsel *leader =3D evsel__leader(evsel); + static bool init_metrics; struct perf_stat_output_ctx ctx =3D { .print_metric =3D script_print_metric, .new_line =3D script_new_line, @@ -2150,23 +2296,85 @@ static void perf_sample__fprint_metric(struct perf_= script *script, }, .force_header =3D false, }; - struct evsel *ev2; - u64 val; + struct perf_counts_values *count, *old_count; + int cpu_map_idx, thread_map_idx, aggr_idx; + struct evsel *pos; + + if (!init_metrics) { + /* One time initialization of stat_config and metric data. */ + struct script_find_metrics_args args =3D { + .evlist =3D evsel->evlist, + .system_wide =3D perf_thread_map__pid(evsel->core.threads, /*idx=3D*/0)= =3D=3D -1, + + }; + if (!stat_config.output) + stat_config.output =3D stdout; + + if (!stat_config.aggr_map) { + /* TODO: currently only global aggregation is supported. */ + assert(stat_config.aggr_mode =3D=3D AGGR_GLOBAL); + stat_config.aggr_get_id =3D script_aggr_cpu_id_get; + stat_config.aggr_map =3D + cpu_aggr_map__new(evsel->evlist->core.user_requested_cpus, + aggr_cpu_id__global, /*data=3D*/NULL, + /*needs_sort=3D*/false); + } + + metricgroup__for_each_metric(pmu_metrics_table__find(), script_find_metr= ics, &args); + init_metrics =3D true; + } + + if (!evsel->stats) { + if (evlist__alloc_stats(&stat_config, evsel->evlist, /*alloc_raw=3D*/tru= e) < 0) + return; + } + if (!evsel->stats->aggr) { + if (evlist__alloc_aggr_stats(evsel->evlist, stat_config.aggr_map->nr) < = 0) + return; + } =20 - if (!evsel->stats) - evlist__alloc_stats(&stat_config, script->session->evlist, /*alloc_raw= =3D*/false); - if (evsel_script(leader)->gnum++ =3D=3D 0) - perf_stat__reset_shadow_stats(); - val =3D sample->period * evsel->scale; - evsel_script(evsel)->val =3D val; - if (evsel_script(leader)->gnum =3D=3D leader->core.nr_members) { - for_each_group_member (ev2, leader) { - perf_stat__print_shadow_stats(&stat_config, ev2, - evsel_script(ev2)->val, - sample->cpu, - &ctx); + /* Update the evsel's count using the sample's data. */ + cpu_map_idx =3D perf_cpu_map__idx(evsel->core.cpus, (struct perf_cpu){sam= ple->cpu}); + if (cpu_map_idx < 0) { + /* Missing CPU, check for any CPU. */ + if (perf_cpu_map__cpu(evsel->core.cpus, /*idx=3D*/0).cpu =3D=3D -1 || + sample->cpu =3D=3D (u32)-1) { + /* Place the counts in the which ever CPU is first in the map. */ + cpu_map_idx =3D 0; + } else { + pr_info("Missing CPU map entry for CPU %d\n", sample->cpu); + return; + } + } + thread_map_idx =3D perf_thread_map__idx(evsel->core.threads, sample->tid); + if (thread_map_idx < 0) { + /* Missing thread, check for any thread. */ + if (perf_thread_map__pid(evsel->core.threads, /*idx=3D*/0) =3D=3D -1 || + sample->tid =3D=3D (u32)-1) { + /* Place the counts in the which ever thread is first in the map. */ + thread_map_idx =3D 0; + } else { + pr_info("Missing thread map entry for thread %d\n", sample->tid); + return; + } + } + count =3D perf_counts(evsel->counts, cpu_map_idx, thread_map_idx); + old_count =3D perf_counts(evsel->prev_raw_counts, cpu_map_idx, thread_map= _idx); + count->val =3D old_count->val + sample->period; + count->run =3D old_count->run + 1; + count->ena =3D old_count->ena + 1; + + /* Update the aggregated stats. */ + perf_stat_process_counter(&stat_config, evsel); + + /* Display all metrics. */ + evlist__for_each_entry(evsel->evlist, pos) { + cpu_aggr_map__for_each_idx(aggr_idx, stat_config.aggr_map) { + perf_stat__print_shadow_stats(&stat_config, pos, + count->val, + aggr_idx, + &ctx); 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AJvYcCULD6HMJLM5ZyTS4tCyjbPoZSopaKekmNNCOliHRdg616D+4bg2D6HdQMpjmaHD9NOXpqGRRh6IQ8+ewZg=@vger.kernel.org X-Gm-Message-State: AOJu0Yytqz7wMxPilzhZZfzNqKhIEofE+XJQbrUD00/cB/VRbUFVG/jZ ejxynFU8fwERf0OiFCpTP+zhOtBxS4VNBVbJxxHAB5zqd3tyGuqLu/Jh9ikW2reD7fPnVXPdyWS HYpzHQfL4pA== X-Google-Smtp-Source: AGHT+IGZE2TnYn3ggysbmJYtqexaZ66TOGuBgUHD/FxJIpw1QySmT8FD6ARVi8vKRVW72M9IzxpgtzuQLPNr X-Received: from dyon3.prod.google.com ([2002:a05:7300:6d03:b0:2a4:6de5:76ea]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:244a:b0:295:105:c87d with SMTP id d9443c01a7336-2984eda98ecmr8260445ad.32.1762896151603; Tue, 11 Nov 2025 13:22:31 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:55 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-8-irogers@google.com> Subject: [PATCH v4 07/18] perf stat: Remove hard coded shadow metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the metrics are encoded in common json the hard coded printing means the metrics are shown twice. Remove the hard coded version. This means that when specifying events, and those events correspond to a hard coded metric, the metric will no longer be displayed. The metric will be displayed if the metric is requested. Due to the adhoc printing in the previous approach it was often found frustrating, the new approach avoids this. The default perf stat output on an alderlake now looks like: ``` $ perf stat -a -- sleep 1 Performance counter stats for 'system wide': 19,697 context-switches # nan cs/sec = cs_per_second TopdownL1 (cpu_core) # 10.7 % tma_bad_spe= culation # 24.9 % tma_fronten= d_bound TopdownL1 (cpu_core) # 34.3 % tma_backend= _bound # 30.1 % tma_retiring 6,593 page-faults # nan faults/= sec page_faults_per_second 729,065,658 cpu_atom/cpu-cycles/ # nan GHz cy= cles_frequency (49.79%) 1,605,131,101 cpu_core/cpu-cycles/ # nan GHz cy= cles_frequency # 19.7 % tma_bad_spe= culation # 14.2 % tma_retirin= g (50.14%) # 37.3 % tma_fronten= d_bound (50.31%) 87,302,268 cpu_atom/branches/ # nan M/sec = branch_frequency (60.27%) 512,046,956 cpu_core/branches/ # nan M/sec = branch_frequency 1,111 cpu-migrations # nan migrati= ons/sec migrations_per_second # 28.8 % tma_backend= _bound (60.26%) 0.00 msec cpu-clock # 0.0 CPUs C= PUs_utilized 392,509,323 cpu_atom/instructions/ # 0.6 instruc= tions insn_per_cycle (60.19%) 2,990,369,310 cpu_core/instructions/ # 1.9 instruc= tions insn_per_cycle 3,493,478 cpu_atom/branch-misses/ # 5.9 % bran= ch_miss_rate (49.69%) 7,297,531 cpu_core/branch-misses/ # 1.4 % bran= ch_miss_rate 1.006621701 seconds time elapsed ``` Signed-off-by: Ian Rogers --- tools/perf/builtin-script.c | 1 - tools/perf/util/stat-display.c | 4 +- tools/perf/util/stat-shadow.c | 392 +-------------------------------- tools/perf/util/stat.h | 2 +- 4 files changed, 6 insertions(+), 393 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 8bab5b264f61..cf0040bbaba9 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2371,7 +2371,6 @@ static void perf_sample__fprint_metric(struct thread = *thread, evlist__for_each_entry(evsel->evlist, pos) { cpu_aggr_map__for_each_idx(aggr_idx, stat_config.aggr_map) { perf_stat__print_shadow_stats(&stat_config, pos, - count->val, aggr_idx, &ctx); } diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index 4d0e353846ea..eabeab5e6614 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -902,7 +902,7 @@ static void printout(struct perf_stat_config *config, s= truct outstate *os, &num, from, &out); } while (from !=3D NULL); } else { - perf_stat__print_shadow_stats(config, counter, uval, aggr_idx, &out); + perf_stat__print_shadow_stats(config, counter, aggr_idx, &out); } } else { pm(config, os, METRIC_THRESHOLD_UNKNOWN, /*format=3D*/NULL, /*unit=3D*/N= ULL, /*val=3D*/0); @@ -1274,7 +1274,7 @@ static void print_metric_headers(struct perf_stat_con= fig *config, =20 os.evsel =3D counter; =20 - perf_stat__print_shadow_stats(config, counter, 0, 0, &out); + perf_stat__print_shadow_stats(config, counter, /*aggr_idx=3D*/0, &out); } =20 if (!config->json_output) diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 4df614f8e200..afbc49e8cb31 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -20,357 +20,12 @@ struct stats walltime_nsecs_stats; struct rusage_stats ru_stats; =20 -enum { - CTX_BIT_USER =3D 1 << 0, - CTX_BIT_KERNEL =3D 1 << 1, - CTX_BIT_HV =3D 1 << 2, - CTX_BIT_HOST =3D 1 << 3, - CTX_BIT_IDLE =3D 1 << 4, - CTX_BIT_MAX =3D 1 << 5, -}; - -enum stat_type { - STAT_NONE =3D 0, - STAT_NSECS, - STAT_CYCLES, - STAT_INSTRUCTIONS, - STAT_STALLED_CYCLES_FRONT, - STAT_STALLED_CYCLES_BACK, - STAT_BRANCHES, - STAT_BRANCH_MISS, - STAT_CACHE_REFS, - STAT_CACHE_MISSES, - STAT_L1_DCACHE, - STAT_L1_ICACHE, - STAT_LL_CACHE, - STAT_ITLB_CACHE, - STAT_DTLB_CACHE, - STAT_L1D_MISS, - STAT_L1I_MISS, - STAT_LL_MISS, - STAT_DTLB_MISS, - STAT_ITLB_MISS, - STAT_MAX -}; - -static int evsel_context(const struct evsel *evsel) -{ - int ctx =3D 0; - - if (evsel->core.attr.exclude_kernel) - ctx |=3D CTX_BIT_KERNEL; - if (evsel->core.attr.exclude_user) - ctx |=3D CTX_BIT_USER; - if (evsel->core.attr.exclude_hv) - ctx |=3D CTX_BIT_HV; - if (evsel->core.attr.exclude_host) - ctx |=3D CTX_BIT_HOST; - if (evsel->core.attr.exclude_idle) - ctx |=3D CTX_BIT_IDLE; - - return ctx; -} - void perf_stat__reset_shadow_stats(void) { memset(&walltime_nsecs_stats, 0, sizeof(walltime_nsecs_stats)); memset(&ru_stats, 0, sizeof(ru_stats)); } =20 -static enum stat_type evsel__stat_type(struct evsel *evsel) -{ - /* Fake perf_hw_cache_op_id values for use with evsel__match. */ - u64 PERF_COUNT_hw_cache_l1d_miss =3D PERF_COUNT_HW_CACHE_L1D | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); - u64 PERF_COUNT_hw_cache_l1i_miss =3D PERF_COUNT_HW_CACHE_L1I | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); - u64 PERF_COUNT_hw_cache_ll_miss =3D PERF_COUNT_HW_CACHE_LL | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); - u64 PERF_COUNT_hw_cache_dtlb_miss =3D PERF_COUNT_HW_CACHE_DTLB | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); - u64 PERF_COUNT_hw_cache_itlb_miss =3D PERF_COUNT_HW_CACHE_ITLB | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); - - if (evsel__is_clock(evsel)) - return STAT_NSECS; - else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) - return STAT_CYCLES; - else if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) - return STAT_INSTRUCTIONS; - else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) - return STAT_STALLED_CYCLES_FRONT; - else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) - return STAT_STALLED_CYCLES_BACK; - else if (evsel__match(evsel, HARDWARE, HW_BRANCH_INSTRUCTIONS)) - return STAT_BRANCHES; - else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) - return STAT_BRANCH_MISS; - else if (evsel__match(evsel, HARDWARE, HW_CACHE_REFERENCES)) - return STAT_CACHE_REFS; - else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) - return STAT_CACHE_MISSES; - else if (evsel__match(evsel, HW_CACHE, HW_CACHE_L1D)) - return STAT_L1_DCACHE; - else if (evsel__match(evsel, HW_CACHE, HW_CACHE_L1I)) - return STAT_L1_ICACHE; - else if (evsel__match(evsel, HW_CACHE, HW_CACHE_LL)) - return STAT_LL_CACHE; - else if (evsel__match(evsel, HW_CACHE, HW_CACHE_DTLB)) - return STAT_DTLB_CACHE; - else if (evsel__match(evsel, HW_CACHE, HW_CACHE_ITLB)) - return STAT_ITLB_CACHE; - else if (evsel__match(evsel, HW_CACHE, hw_cache_l1d_miss)) - return STAT_L1D_MISS; - else if (evsel__match(evsel, HW_CACHE, hw_cache_l1i_miss)) - return STAT_L1I_MISS; - else if (evsel__match(evsel, HW_CACHE, hw_cache_ll_miss)) - return STAT_LL_MISS; - else if (evsel__match(evsel, HW_CACHE, hw_cache_dtlb_miss)) - return STAT_DTLB_MISS; - else if (evsel__match(evsel, HW_CACHE, hw_cache_itlb_miss)) - return STAT_ITLB_MISS; - return STAT_NONE; -} - -static enum metric_threshold_classify get_ratio_thresh(const double ratios= [3], double val) -{ - assert(ratios[0] > ratios[1]); - assert(ratios[1] > ratios[2]); - - return val > ratios[1] - ? (val > ratios[0] ? METRIC_THRESHOLD_BAD : METRIC_THRESHOLD_NEARLY_BAD) - : (val > ratios[2] ? METRIC_THRESHOLD_LESS_GOOD : METRIC_THRESHOLD_GOOD); -} - -static double find_stat(const struct evsel *evsel, int aggr_idx, enum stat= _type type) -{ - struct evsel *cur; - int evsel_ctx =3D evsel_context(evsel); - struct perf_pmu *evsel_pmu =3D evsel__find_pmu(evsel); - - evlist__for_each_entry(evsel->evlist, cur) { - struct perf_stat_aggr *aggr; - - /* Ignore the evsel that is being searched from. */ - if (evsel =3D=3D cur) - continue; - - /* Ignore evsels that are part of different groups. */ - if (evsel->core.leader->nr_members > 1 && - evsel->core.leader !=3D cur->core.leader) - continue; - /* Ignore evsels with mismatched modifiers. */ - if (evsel_ctx !=3D evsel_context(cur)) - continue; - /* Ignore if not the cgroup we're looking for. */ - if (evsel->cgrp !=3D cur->cgrp) - continue; - /* Ignore if not the stat we're looking for. */ - if (type !=3D evsel__stat_type(cur)) - continue; - - /* - * Except the SW CLOCK events, - * ignore if not the PMU we're looking for. - */ - if ((type !=3D STAT_NSECS) && (evsel_pmu !=3D evsel__find_pmu(cur))) - continue; - - aggr =3D &cur->stats->aggr[aggr_idx]; - if (type =3D=3D STAT_NSECS) - return aggr->counts.val; - return aggr->counts.val * cur->scale; - } - return 0.0; -} - -static void print_ratio(struct perf_stat_config *config, - const struct evsel *evsel, int aggr_idx, - double numerator, struct perf_stat_output_ctx *out, - enum stat_type denominator_type, - const double thresh_ratios[3], const char *_unit) -{ - double denominator =3D find_stat(evsel, aggr_idx, denominator_type); - double ratio =3D 0; - enum metric_threshold_classify thresh =3D METRIC_THRESHOLD_UNKNOWN; - const char *fmt =3D NULL; - const char *unit =3D NULL; - - if (numerator && denominator) { - ratio =3D numerator / denominator * 100.0; - thresh =3D get_ratio_thresh(thresh_ratios, ratio); - fmt =3D "%7.2f%%"; - unit =3D _unit; - } - out->print_metric(config, out->ctx, thresh, fmt, unit, ratio); -} - -static void print_stalled_cycles_front(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double stalled, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {50.0, 30.0, 10.0}; - - print_ratio(config, evsel, aggr_idx, stalled, out, STAT_CYCLES, thresh_ra= tios, - "frontend cycles idle"); -} - -static void print_stalled_cycles_back(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double stalled, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {75.0, 50.0, 20.0}; - - print_ratio(config, evsel, aggr_idx, stalled, out, STAT_CYCLES, thresh_ra= tios, - "backend cycles idle"); -} - -static void print_branch_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_BRANCHES, thresh_r= atios, - "of all branches"); -} - -static void print_l1d_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_L1_DCACHE, thresh_= ratios, - "of all L1-dcache accesses"); -} - -static void print_l1i_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_L1_ICACHE, thresh_= ratios, - "of all L1-icache accesses"); -} - -static void print_ll_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_LL_CACHE, thresh_r= atios, - "of all LL-cache accesses"); -} - -static void print_dtlb_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_DTLB_CACHE, thresh= _ratios, - "of all dTLB cache accesses"); -} - -static void print_itlb_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_ITLB_CACHE, thresh= _ratios, - "of all iTLB cache accesses"); -} - -static void print_cache_miss(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out) -{ - const double thresh_ratios[3] =3D {20.0, 10.0, 5.0}; - - print_ratio(config, evsel, aggr_idx, misses, out, STAT_CACHE_REFS, thresh= _ratios, - "of all cache refs"); -} - -static void print_instructions(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double instructions, - struct perf_stat_output_ctx *out) -{ - print_metric_t print_metric =3D out->print_metric; - void *ctxp =3D out->ctx; - double cycles =3D find_stat(evsel, aggr_idx, STAT_CYCLES); - double max_stalled =3D max(find_stat(evsel, aggr_idx, STAT_STALLED_CYCLES= _FRONT), - find_stat(evsel, aggr_idx, STAT_STALLED_CYCLES_BACK)); - - if (cycles) { - print_metric(config, ctxp, METRIC_THRESHOLD_UNKNOWN, "%7.2f ", - "insn per cycle", instructions / cycles); - } else { - print_metric(config, ctxp, METRIC_THRESHOLD_UNKNOWN, /*fmt=3D*/NULL, - "insn per cycle", 0); - } - if (max_stalled && instructions) { - if (out->new_line) - out->new_line(config, ctxp); - print_metric(config, ctxp, METRIC_THRESHOLD_UNKNOWN, "%7.2f ", - "stalled cycles per insn", max_stalled / instructions); - } -} - -static void print_cycles(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double cycles, - struct perf_stat_output_ctx *out) -{ - double nsecs =3D find_stat(evsel, aggr_idx, STAT_NSECS); - - if (cycles && nsecs) { - double ratio =3D cycles / nsecs; - - out->print_metric(config, out->ctx, METRIC_THRESHOLD_UNKNOWN, "%8.3f", - "GHz", ratio); - } else { - out->print_metric(config, out->ctx, METRIC_THRESHOLD_UNKNOWN, /*fmt=3D*/= NULL, - "GHz", 0); - } -} - -static void print_nsecs(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx __maybe_unused, double nsecs, - struct perf_stat_output_ctx *out) -{ - print_metric_t print_metric =3D out->print_metric; - void *ctxp =3D out->ctx; - double wall_time =3D avg_stats(&walltime_nsecs_stats); - - if (wall_time) { - print_metric(config, ctxp, METRIC_THRESHOLD_UNKNOWN, "%8.3f", "CPUs util= ized", - nsecs / (wall_time * evsel->scale)); - } else { - print_metric(config, ctxp, METRIC_THRESHOLD_UNKNOWN, /*fmt=3D*/NULL, - "CPUs utilized", 0); - } -} - static int prepare_metric(const struct metric_expr *mexp, const struct evsel *evsel, struct expr_parse_ctx *pctx, @@ -682,56 +337,15 @@ void *perf_stat__print_shadow_stats_metricgroup(struc= t perf_stat_config *config, =20 void perf_stat__print_shadow_stats(struct perf_stat_config *config, struct evsel *evsel, - double avg, int aggr_idx, + int aggr_idx, struct perf_stat_output_ctx *out) { - typedef void (*stat_print_function_t)(struct perf_stat_config *config, - const struct evsel *evsel, - int aggr_idx, double misses, - struct perf_stat_output_ctx *out); - static const stat_print_function_t stat_print_function[STAT_MAX] =3D { - [STAT_INSTRUCTIONS] =3D print_instructions, - [STAT_BRANCH_MISS] =3D print_branch_miss, - [STAT_L1D_MISS] =3D print_l1d_miss, - [STAT_L1I_MISS] =3D print_l1i_miss, - [STAT_DTLB_MISS] =3D print_dtlb_miss, - [STAT_ITLB_MISS] =3D print_itlb_miss, - [STAT_LL_MISS] =3D print_ll_miss, - [STAT_CACHE_MISSES] =3D print_cache_miss, - [STAT_STALLED_CYCLES_FRONT] =3D print_stalled_cycles_front, - [STAT_STALLED_CYCLES_BACK] =3D print_stalled_cycles_back, - [STAT_CYCLES] =3D print_cycles, - [STAT_NSECS] =3D print_nsecs, - }; print_metric_t print_metric =3D out->print_metric; void *ctxp =3D out->ctx; - int num =3D 1; + int num =3D 0; =20 - if (config->iostat_run) { + if (config->iostat_run) iostat_print_metric(config, evsel, out); - } else { - stat_print_function_t fn =3D stat_print_function[evsel__stat_type(evsel)= ]; - - if (fn) - fn(config, evsel, aggr_idx, avg, out); - else { - double nsecs =3D find_stat(evsel, aggr_idx, STAT_NSECS); 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Tue, 11 Nov 2025 13:22:33 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:56 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-9-irogers@google.com> Subject: [PATCH v4 08/18] perf stat: Fix default metricgroup display on hybrid From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The logic to skip output of a default metric line was firing on Alderlake and not displaying 'TopdownL1 (cpu_atom)'. Remove the need_full_name check as it is equivalent to the different PMU test in the cases we care about, merge the 'if's and flip the evsel of the PMU test. The 'if' is now basically saying, if the output matches the last printed output then skip the output. Before: ``` TopdownL1 (cpu_core) # 11.3 % tma_bad_spe= culation # 24.3 % tma_fronten= d_bound TopdownL1 (cpu_core) # 33.9 % tma_backend= _bound # 30.6 % tma_retiring # 42.2 % tma_backend= _bound # 25.0 % tma_fronten= d_bound (49.81%) # 12.8 % tma_bad_spe= culation # 20.0 % tma_retirin= g (59.46%) ``` After: ``` TopdownL1 (cpu_core) # 8.3 % tma_bad_spe= culation # 43.7 % tma_fronten= d_bound # 30.7 % tma_backend= _bound # 17.2 % tma_retiring TopdownL1 (cpu_atom) # 31.9 % tma_backend= _bound # 37.6 % tma_fronten= d_bound (49.66%) # 18.0 % tma_bad_spe= culation # 12.6 % tma_retirin= g (59.58%) ``` Signed-off-by: Ian Rogers --- tools/perf/util/stat-shadow.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index afbc49e8cb31..c1547128c396 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -256,11 +256,9 @@ static void perf_stat__print_metricgroup_header(struct= perf_stat_config *config, * event. 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charset="utf-8" To improve the readability of default events/metrics, sort the evsels after the Default metric groups have be parsed. Before: ``` $ perf stat -a sleep 1 Performance counter stats for 'system wide': 22,087 context-switches # nan cs/sec = cs_per_second TopdownL1 (cpu_core) # 10.3 % tma_bad_spe= culation # 25.8 % tma_fronten= d_bound # 34.5 % tma_backend= _bound # 29.3 % tma_retiring 7,829 page-faults # nan faults/= sec page_faults_per_second 880,144,270 cpu_atom/cpu-cycles/ # nan GHz cy= cles_frequency (50.10%) 1,693,081,235 cpu_core/cpu-cycles/ # nan GHz cy= cles_frequency TopdownL1 (cpu_atom) # 20.5 % tma_bad_spe= culation # 13.8 % tma_retirin= g (50.26%) # 34.6 % tma_fronten= d_bound (50.23%) 89,326,916 cpu_atom/branches/ # nan M/sec = branch_frequency (60.19%) 538,123,088 cpu_core/branches/ # nan M/sec = branch_frequency 1,368 cpu-migrations # nan migrati= ons/sec migrations_per_second # 31.1 % tma_backend= _bound (60.19%) 0.00 msec cpu-clock # 0.0 CPUs C= PUs_utilized 485,744,856 cpu_atom/instructions/ # 0.6 instruc= tions insn_per_cycle (59.87%) 3,093,112,283 cpu_core/instructions/ # 1.8 instruc= tions insn_per_cycle 4,939,427 cpu_atom/branch-misses/ # 5.0 % bran= ch_miss_rate (49.77%) 7,632,248 cpu_core/branch-misses/ # 1.4 % bran= ch_miss_rate 1.005084693 seconds time elapsed ``` After: ``` $ perf stat -a sleep 1 Performance counter stats for 'system wide': 22,165 context-switches # nan cs/sec = cs_per_second 0.00 msec cpu-clock # 0.0 CPUs C= PUs_utilized 2,260 cpu-migrations # nan migrati= ons/sec migrations_per_second 20,476 page-faults # nan faults/= sec page_faults_per_second 17,052,357 cpu_core/branch-misses/ # 1.5 % bran= ch_miss_rate 1,120,090,590 cpu_core/branches/ # nan M/sec = branch_frequency 3,402,892,275 cpu_core/cpu-cycles/ # nan GHz cy= cles_frequency 6,129,236,701 cpu_core/instructions/ # 1.8 instruc= tions insn_per_cycle 6,159,523 cpu_atom/branch-misses/ # 3.1 % bran= ch_miss_rate (49.86%) 222,158,812 cpu_atom/branches/ # nan M/sec = branch_frequency (50.25%) 1,547,610,244 cpu_atom/cpu-cycles/ # nan GHz cy= cles_frequency (50.40%) 1,304,901,260 cpu_atom/instructions/ # 0.8 instruc= tions insn_per_cycle (50.41%) TopdownL1 (cpu_core) # 13.7 % tma_bad_spe= culation # 23.5 % tma_fronten= d_bound # 33.3 % tma_backend= _bound # 29.6 % tma_retiring TopdownL1 (cpu_atom) # 32.1 % tma_backend= _bound (59.65%) # 30.1 % tma_fronten= d_bound (59.51%) # 22.3 % tma_bad_spe= culation # 15.5 % tma_retirin= g (59.53%) 1.008405429 seconds time elapsed ``` Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 7862094b93c8..095016b2209e 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -74,6 +74,7 @@ #include "util/intel-tpebs.h" #include "asm/bug.h" =20 +#include #include #include #include @@ -1857,6 +1858,35 @@ static int perf_stat_init_aggr_mode_file(struct perf= _stat *st) return 0; } =20 +static int default_evlist_evsel_cmp(void *priv __maybe_unused, + const struct list_head *l, + const struct list_head *r) +{ + const struct perf_evsel *lhs_core =3D container_of(l, struct perf_evsel, = node); + const struct evsel *lhs =3D container_of(lhs_core, struct evsel, core); + const struct perf_evsel *rhs_core =3D container_of(r, struct perf_evsel, = node); + const struct evsel *rhs =3D container_of(rhs_core, struct evsel, core); + + if (evsel__leader(lhs) =3D=3D evsel__leader(rhs)) { + /* Within the same group, respect the original order. */ + return lhs_core->idx - rhs_core->idx; + } + + /* Sort default metrics evsels first, and default show events before thos= e. */ + if (lhs->default_metricgroup !=3D rhs->default_metricgroup) + return lhs->default_metricgroup ? -1 : 1; + + if (lhs->default_show_events !=3D rhs->default_show_events) + return lhs->default_show_events ? -1 : 1; + + /* Sort by PMU type (prefers legacy types first). */ + if (lhs->pmu !=3D rhs->pmu) + return lhs->pmu->type - rhs->pmu->type; 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Tue, 11 Nov 2025 13:22:37 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:58 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-11-irogers@google.com> Subject: [PATCH v4 10/18] perf stat: Remove "unit" workarounds for metric-only From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove code that tested the "unit" as in KB/sec for certain hard coded metric values and did workarounds. Signed-off-by: Ian Rogers --- tools/perf/util/stat-display.c | 47 ++++++---------------------------- 1 file changed, 8 insertions(+), 39 deletions(-) diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index eabeab5e6614..b3596f9f5cdd 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -592,42 +592,18 @@ static void print_metricgroup_header_std(struct perf_= stat_config *config, fprintf(config->output, "%*s", MGROUP_LEN - n - 1, ""); } =20 -/* Filter out some columns that don't work well in metrics only mode */ - -static bool valid_only_metric(const char *unit) -{ - if (!unit) - return false; - if (strstr(unit, "/sec") || - strstr(unit, "CPUs utilized")) - return false; - return true; -} - -static const char *fixunit(char *buf, struct evsel *evsel, - const char *unit) -{ - if (!strncmp(unit, "of all", 6)) { - snprintf(buf, 1024, "%s %s", evsel__name(evsel), - unit); - return buf; - } - return unit; -} - static void print_metric_only(struct perf_stat_config *config, void *ctx, enum metric_threshold_classify thresh, const char *fmt, const char *unit, double val) { struct outstate *os =3D ctx; FILE *out =3D os->fh; - char buf[1024], str[1024]; + char str[1024]; unsigned mlen =3D config->metric_only_len; const char *color =3D metric_threshold_classify__color(thresh); =20 - if (!valid_only_metric(unit)) - return; - unit =3D fixunit(buf, os->evsel, unit); + if (!unit) + unit =3D ""; if (mlen < strlen(unit)) mlen =3D strlen(unit) + 1; =20 @@ -643,16 +619,15 @@ static void print_metric_only_csv(struct perf_stat_co= nfig *config __maybe_unused void *ctx, enum metric_threshold_classify thresh __maybe_unused, const char *fmt, - const char *unit, double val) + const char *unit __maybe_unused, double val) { struct outstate *os =3D ctx; FILE *out =3D os->fh; char buf[64], *vals, *ends; - char tbuf[1024]; =20 - if (!valid_only_metric(unit)) + if (!unit) return; - unit =3D fixunit(tbuf, os->evsel, unit); + snprintf(buf, sizeof(buf), fmt ?: "", val); ends =3D vals =3D skip_spaces(buf); while (isdigit(*ends) || *ends =3D=3D '.') @@ -670,13 +645,9 @@ static void print_metric_only_json(struct perf_stat_co= nfig *config __maybe_unuse { struct outstate *os =3D ctx; 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Tue, 11 Nov 2025 13:22:39 -0800 (PST) Date: Tue, 11 Nov 2025 13:21:59 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-12-irogers@google.com> Subject: [PATCH v4 11/18] perf test stat+json: Improve metric-only testing From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When testing metric-only, pass a metric to perf rather than expecting a hard coded metric value to be generated. Remove keys that were really metric-only units and instead don't expect metric only to have a matching json key as it encodes metrics as {"metric_name", "metric_value"}. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/lib/perf_json_output_lint.py | 4 ++-- tools/perf/tests/shell/stat+json_output.sh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/tests/shell/lib/perf_json_output_lint.py b/tools/pe= rf/tests/shell/lib/perf_json_output_lint.py index c6750ef06c0f..1369baaa0361 100644 --- a/tools/perf/tests/shell/lib/perf_json_output_lint.py +++ b/tools/perf/tests/shell/lib/perf_json_output_lint.py @@ -65,8 +65,6 @@ def check_json_output(expected_items): 'socket': lambda x: True, 'thread': lambda x: True, 'unit': lambda x: True, - 'insn per cycle': lambda x: isfloat(x), - 'GHz': lambda x: True, # FIXME: it seems unintended for --metric-on= ly } input =3D '[\n' + ','.join(Lines) + '\n]' for item in json.loads(input): @@ -88,6 +86,8 @@ def check_json_output(expected_items): f' in \'{item}\'') for key, value in item.items(): if key not in checks: + if args.metric_only: + continue raise RuntimeError(f'Unexpected key: key=3D{key} value=3D{value}') if not checks[key](value): raise RuntimeError(f'Check failed for: key=3D{key} value=3D{value}= ') diff --git a/tools/perf/tests/shell/stat+json_output.sh b/tools/perf/tests/= shell/stat+json_output.sh index 98fb65274ac4..85d1ad7186c6 100755 --- a/tools/perf/tests/shell/stat+json_output.sh +++ b/tools/perf/tests/shell/stat+json_output.sh @@ -181,7 +181,7 @@ check_metric_only() echo "[Skip] CPU-measurement counter facility not installed" return fi - perf stat -j --metric-only -e instructions,cycles -o "${stat_output}" true + perf stat -j --metric-only -M page_faults_per_second -o "${stat_output}" = true $PYTHON $pythonchecker --metric-only --file "${stat_output}" echo "[Success]" } --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92BA635E554 for ; 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Tue, 11 Nov 2025 13:22:40 -0800 (PST) Date: Tue, 11 Nov 2025 13:22:00 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-13-irogers@google.com> Subject: [PATCH v4 12/18] perf test stat: Ignore failures in Default[234] metricgroups From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Default[234] metric groups may contain unsupported legacy events. Allow those metric groups to fail. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/stat_all_metricgroups.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/perf/tests/shell/stat_all_metricgroups.sh b/tools/perf/t= ests/shell/stat_all_metricgroups.sh index c6d61a4ac3e7..1400880ec01f 100755 --- a/tools/perf/tests/shell/stat_all_metricgroups.sh +++ b/tools/perf/tests/shell/stat_all_metricgroups.sh @@ -37,6 +37,9 @@ do then err=3D2 # Skip fi + elif [[ "$m" =3D=3D @(Default2|Default3|Default4) ]] + then + echo "Ignoring failures in $m that may contain unsupported legacy ev= ents" else echo "Metric group $m failed" echo $result --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A3F33624AD for ; Tue, 11 Nov 2025 21:22:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 11 Nov 2025 13:22:42 -0800 (PST) Date: Tue, 11 Nov 2025 13:22:01 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-14-irogers@google.com> Subject: [PATCH v4 13/18] perf test stat: Update std_output testing metric expectations From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the expectations match json metrics rather than the previous hard coded ones. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/stat+std_output.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/shell/stat+std_output.sh b/tools/perf/tests/s= hell/stat+std_output.sh index ec41f24299d9..9c4b92ecf448 100755 --- a/tools/perf/tests/shell/stat+std_output.sh +++ b/tools/perf/tests/shell/stat+std_output.sh @@ -12,8 +12,8 @@ set -e stat_output=3D$(mktemp /tmp/__perf_test.stat_output.std.XXXXX) =20 event_name=3D(cpu-clock task-clock context-switches cpu-migrations page-fa= ults stalled-cycles-frontend stalled-cycles-backend cycles instructions bra= nches branch-misses) -event_metric=3D("CPUs utilized" "CPUs utilized" "/sec" "/sec" "/sec" "fron= tend cycles idle" "backend cycles idle" "GHz" "insn per cycle" "/sec" "of a= ll branches") -skip_metric=3D("stalled cycles per insn" "tma_" "retiring" "frontend_bound= " "bad_speculation" "backend_bound" "TopdownL1" "percent of slots") +event_metric=3D("CPUs_utilized" "CPUs_utilized" "cs/sec" "migrations/sec" = "faults/sec" "frontend_cycles_idle" "backend_cycles_idle" "GHz" "insn_per_c= ycle" "/sec" "branch_miss_rate") +skip_metric=3D("tma_" "TopdownL1") =20 cleanup() { rm -f "${stat_output}" --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28B343624D0 for ; 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Tue, 11 Nov 2025 13:22:44 -0800 (PST) Date: Tue, 11 Nov 2025 13:22:02 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-15-irogers@google.com> Subject: [PATCH v4 14/18] perf test metrics: Update all metrics for possibly failing default metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Default metrics may use unsupported events and be ignored. These metrics shouldn't cause metric testing to fail. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/stat_all_metrics.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/stat_all_metrics.sh b/tools/perf/tests/= shell/stat_all_metrics.sh index 6fa585a1e34c..a7edf01b3943 100755 --- a/tools/perf/tests/shell/stat_all_metrics.sh +++ b/tools/perf/tests/shell/stat_all_metrics.sh @@ -25,8 +25,13 @@ for m in $(perf list --raw-dump metrics); do # No error result and metric shown. continue fi - if [[ "$result" =3D~ "Cannot resolve IDs for" ]] + if [[ "$result" =3D~ "Cannot resolve IDs for" || "$result" =3D~ "No supp= orted events found" ]] then + if [[ "$m" =3D=3D @(l1_prefetch_miss_rate|stalled_cycles_per_instructi= on) ]] + then + # Default metrics that may use unsupported events. + continue + fi echo "Metric contains missing events" echo $result err=3D1 # Fail --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0077364025 for ; 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Tue, 11 Nov 2025 13:22:46 -0800 (PST) Date: Tue, 11 Nov 2025 13:22:03 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-16-irogers@google.com> Subject: [PATCH v4 15/18] perf test stat: Update shadow test to use metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously '-e cycles,instructions' would implicitly create an IPC metric. This now has to be explicit with '-M insn_per_cycle'. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/stat+shadow_stat.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/shell/stat+shadow_stat.sh b/tools/perf/tests/= shell/stat+shadow_stat.sh index 8824f445d343..cabbbf17c662 100755 --- a/tools/perf/tests/shell/stat+shadow_stat.sh +++ b/tools/perf/tests/shell/stat+shadow_stat.sh @@ -14,7 +14,7 @@ perf stat -a -e cycles sleep 1 2>&1 | grep -e cpu_core &&= exit 2 =20 test_global_aggr() { - perf stat -a --no-big-num -e cycles,instructions sleep 1 2>&1 | \ + perf stat -a --no-big-num -M insn_per_cycle sleep 1 2>&1 | \ grep -e cycles -e instructions | \ while read num evt _ ipc rest do @@ -53,7 +53,7 @@ test_global_aggr() =20 test_no_aggr() { - perf stat -a -A --no-big-num -e cycles,instructions sleep 1 2>&1 | \ + perf stat -a -A --no-big-num -M insn_per_cycle sleep 1 2>&1 | \ grep ^CPU | \ while read cpu num evt _ ipc rest do --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sun Feb 8 04:30:51 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8F5C364044 for ; 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Tue, 11 Nov 2025 13:22:48 -0800 (PST) Date: Tue, 11 Nov 2025 13:22:04 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-17-irogers@google.com> Subject: [PATCH v4 16/18] perf test stat: Update test expectations and events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" test_stat_record_report and test_stat_record_script used default output which triggers a bug when sending metrics. As this isn't relevant to the test switch to using named software events. Update the match in test_hybrid as the cycles event is now cpu-cycles to workaround potential ARM issues. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/stat.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/tests/shell/stat.sh b/tools/perf/tests/shell/stat.sh index 8a100a7f2dc1..985adc02749e 100755 --- a/tools/perf/tests/shell/stat.sh +++ b/tools/perf/tests/shell/stat.sh @@ -18,7 +18,7 @@ test_default_stat() { =20 test_stat_record_report() { echo "stat record and report test" - if ! perf stat record -o - true | perf stat report -i - 2>&1 | \ + if ! perf stat record -e task-clock -o - true | perf stat report -i - 2>= &1 | \ grep -E -q "Performance counter stats for 'pipe':" then echo "stat record and report test [Failed]" @@ -30,7 +30,7 @@ test_stat_record_report() { =20 test_stat_record_script() { echo "stat record and script test" - if ! perf stat record -o - true | perf script -i - 2>&1 | \ + if ! perf stat record -e task-clock -o - true | perf script -i - 2>&1 | \ grep -E -q "CPU[[:space:]]+THREAD[[:space:]]+VAL[[:space:]]+ENA[[:spac= e:]]+RUN[[:space:]]+TIME[[:space:]]+EVENT" then echo "stat record and script test [Failed]" @@ -196,7 +196,7 @@ test_hybrid() { fi =20 # Run default Perf stat - cycles_events=3D$(perf stat -- true 2>&1 | grep -E "/cycles/[uH]*| cycl= es[:uH]* " -c) + cycles_events=3D$(perf stat -a -- sleep 0.1 2>&1 | grep -E "/cpu-cycles/= [uH]*| cpu-cycles[:uH]* " -c) =20 # The expectation is that default output will have a cycles events on ea= ch # hybrid PMU. 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charset="utf-8" Explicitly use a metric rather than implicitly expecting '-e instructions,cycles' to produce a metric. Use a metric with software events to make it more compatible. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/lib/stat_output.sh | 2 +- tools/perf/tests/shell/stat+csv_output.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/shell/lib/stat_output.sh b/tools/perf/tests/s= hell/lib/stat_output.sh index c2ec7881ec1d..3c36e80fe422 100644 --- a/tools/perf/tests/shell/lib/stat_output.sh +++ b/tools/perf/tests/shell/lib/stat_output.sh @@ -156,7 +156,7 @@ check_metric_only() echo "[Skip] CPU-measurement counter facility not installed" return fi - perf stat --metric-only $2 -e instructions,cycles true + perf stat --metric-only $2 -M page_faults_per_second true commachecker --metric-only echo "[Success]" } diff --git a/tools/perf/tests/shell/stat+csv_output.sh b/tools/perf/tests/s= hell/stat+csv_output.sh index 7a6f6e177402..cd6fff597091 100755 --- a/tools/perf/tests/shell/stat+csv_output.sh +++ b/tools/perf/tests/shell/stat+csv_output.sh @@ -44,7 +44,7 @@ function commachecker() ;; "--per-die") exp=3D8 ;; "--per-cluster") exp=3D8 ;; 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AJvYcCUawH8bqqUpXpdGAFBobq6wtGaYK8PRwEFcNYbpqHNauDtlV13DPK2btuYBiN+fE6Ni1gWPmimVxW3I9Fw=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1zNVXnczIiOW0WddWHHGlQy/FTKhRKwBygiGg85HesAX2AcCJ 0lwvlG2QDlzixsx7zKGjnGZ44VWAL84TkBdLv1OVTGbdCGqFIgEXH4vnK/KJG3johpxfje7mPs9 cT3dINmy2HA== X-Google-Smtp-Source: AGHT+IFm04vCDo4qChLVMI8yEVkGMN1wBjSvdxv31AE6WY5yDKYX3muLeyaYR04xWKNSF1hzQ4SsLzOZNcBZ X-Received: from pfdr27.prod.google.com ([2002:aa7:8b9b:0:b0:7ae:a150:ac8]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:3a12:b0:783:c2c4:9aa5 with SMTP id d2e1a72fcca58-7b7a5997a03mr549061b3a.32.1762896172061; Tue, 11 Nov 2025 13:22:52 -0800 (PST) Date: Tue, 11 Nov 2025 13:22:06 -0800 In-Reply-To: <20251111212206.631711-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251111212206.631711-1-irogers@google.com> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog Message-ID: <20251111212206.631711-19-irogers@google.com> Subject: [PATCH v4 18/18] perf tool_pmu: Make core_wide and target_cpu json events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Xu Yang , Chun-Tse Shao , Thomas Richter , Sumanth Korikkar , Collin Funk , Thomas Falcon , Howard Chu , Dapeng Mi , Levi Yun , Yang Li , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Andi Kleen , Weilin Wang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the sake of better documentation, add core_wide and target_cpu to the tool.json. When the values of system_wide and user_requested_cpu_list are unknown, use the values from the global stat_config. Example output showing how '-a' modifies the values in `perf stat`: ``` $ perf stat -e core_wide,target_cpu true Performance counter stats for 'true': 0 core_wide 0 target_cpu 0.000993787 seconds time elapsed 0.001128000 seconds user 0.000000000 seconds sys $ perf stat -e core_wide,target_cpu -a true Performance counter stats for 'system wide': 1 core_wide 1 target_cpu 0.002271723 seconds time elapsed $ perf list ... tool: core_wide [1 if not SMT,if SMT are events being gathered on all SMT threads 1 = otherwise 0. Unit: tool] ... target_cpu [1 if CPUs being analyzed,0 if threads/processes. Unit: tool] ... ``` Signed-off-by: Ian Rogers --- .../pmu-events/arch/common/common/tool.json | 12 + tools/perf/pmu-events/empty-pmu-events.c | 228 +++++++++--------- tools/perf/util/expr.c | 11 +- tools/perf/util/stat-shadow.c | 2 + tools/perf/util/tool_pmu.c | 24 +- tools/perf/util/tool_pmu.h | 9 +- 6 files changed, 163 insertions(+), 123 deletions(-) diff --git a/tools/perf/pmu-events/arch/common/common/tool.json b/tools/per= f/pmu-events/arch/common/common/tool.json index 12f2ef1813a6..14d0d60a1976 100644 --- a/tools/perf/pmu-events/arch/common/common/tool.json +++ b/tools/perf/pmu-events/arch/common/common/tool.json @@ -70,5 +70,17 @@ "EventName": "system_tsc_freq", "BriefDescription": "The amount a Time Stamp Counter (TSC) increases p= er second", "ConfigCode": "12" + }, + { + "Unit": "tool", + "EventName": "core_wide", + "BriefDescription": "1 if not SMT, if SMT are events being gathered on= all SMT threads 1 otherwise 0", + "ConfigCode": "13" + }, + { + "Unit": "tool", + "EventName": "target_cpu", + "BriefDescription": "1 if CPUs being analyzed, 0 if threads/processes", + "ConfigCode": "14" } ] diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 7fa42f13300f..76c395cf513c 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -1279,62 +1279,64 @@ static const char *const big_c_string =3D /* offset=3D125889 */ "slots\000tool\000Number of functional units that in= parallel can execute parts of an instruction\000config=3D0xa\000\00000\000= \000\000\000\000" /* offset=3D125999 */ "smt_on\000tool\0001 if simultaneous multithreading = (aka hyperthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\00= 0\000\000\000" /* offset=3D126106 */ "system_tsc_freq\000tool\000The amount a Time Stamp = Counter (TSC) increases per second\000config=3D0xc\000\00000\000\000\000\00= 0\000" -/* offset=3D126205 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\00= 0event=3D0x8a\000\00000\000\000\000\000\000" -/* offset=3D126267 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\00= 0event=3D0x8b\000\00000\000\000\000\000\000" -/* offset=3D126329 */ "l3_cache_rd\000cache\000L3 cache access, read\000ev= ent=3D0x40\000\00000\000\000\000\000Attributable Level 3 cache access, read= \000" -/* offset=3D126427 */ "segment_reg_loads.any\000other\000Number of segment= register loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000= \000\000\000" -/* offset=3D126529 */ "dispatch_blocked.any\000other\000Memory cluster sig= nals to block micro-op dispatch for any reason\000event=3D9,period=3D200000= ,umask=3D0x20\000\00000\000\000\000\000\000" -/* offset=3D126662 */ "eist_trans\000other\000Number of Enhanced Intel Spe= edStep(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000= \00000\000\000\000\000\000" -/* offset=3D126780 */ "hisi_sccl,ddrc\000" -/* offset=3D126795 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write = commands\000event=3D2\000\00000\000\000\000\000\000" -/* offset=3D126865 */ "uncore_cbox\000" -/* offset=3D126877 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A = cross-core snoop resulted from L3 Eviction which misses in some processor c= ore\000event=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000" -/* offset=3D127031 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event= =3D0xe0\000\00000\000\000\000\000\000" -/* offset=3D127085 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000eve= nt=3D0xc0\000\00000\000\000\000\000\000" -/* offset=3D127143 */ "hisi_sccl,l3c\000" -/* offset=3D127157 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total rea= d hits\000event=3D7\000\00000\000\000\000\000\000" -/* offset=3D127225 */ "uncore_imc_free_running\000" -/* offset=3D127249 */ "uncore_imc_free_running.cache_miss\000uncore\000Tot= al cache misses\000event=3D0x12\000\00000\000\000\000\000\000" -/* offset=3D127329 */ "uncore_imc\000" -/* offset=3D127340 */ "uncore_imc.cache_hits\000uncore\000Total cache hits= \000event=3D0x34\000\00000\000\000\000\000\000" -/* offset=3D127405 */ "uncore_sys_ddr_pmu\000" -/* offset=3D127424 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cyc= les event\000event=3D0x2b\000v8\00000\000\000\000\000\000" -/* offset=3D127500 */ "uncore_sys_ccn_pmu\000" -/* offset=3D127519 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycle= s event\000config=3D0x2c\0000x01\00000\000\000\000\000\000" -/* offset=3D127596 */ "uncore_sys_cmn_pmu\000" -/* offset=3D127615 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts tota= l cache misses in first lookup result (high priority)\000eventid=3D1,type= =3D5\000(434|436|43c|43a).*\00000\000\000\000\000\000" -/* offset=3D127758 */ "CPUs_utilized\000Default\000(software@cpu\\-clock\\= ,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\= =3Dtask\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\00= 0\0001CPUs\000\000\000\000011" -/* offset=3D127944 */ "cs_per_second\000Default\000software@context\\-swit= ches\\,name\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\= 000011" -/* offset=3D128177 */ "migrations_per_second\000Default\000software@cpu\\-= migrations\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,nam= e\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtas= k\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001m= igrations/sec\000\000\000\000011" -/* offset=3D128437 */ "page_faults_per_second\000Default\000software@page\= \-faults\\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\0= 00011" -/* offset=3D128668 */ "insn_per_cycle\000Default\000instructions / cpu\\-c= ycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\= 000\000\000\000001" -/* offset=3D128781 */ "stalled_cycles_per_instruction\000Default\000max(st= alled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\0= 00Max front or backend stalls per instruction\000\000\000\000\000\000001" -/* offset=3D128945 */ "frontend_cycles_idle\000Default\000stalled\\-cycles= \\-frontend / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls= per cycle\000\000\000\000\000\000001" -/* offset=3D129075 */ "backend_cycles_idle\000Default\000stalled\\-cycles\= \-backend / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per= cycle\000\000\000\000\000\000001" -/* offset=3D129201 */ "cycles_frequency\000Default\000cpu\\-cycles / (soft= ware@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\= \-clock\\,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\= 000\000\000\000011" -/* offset=3D129377 */ "branch_frequency\000Default\000branches / (software= @cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-cl= ock\\,name\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/s= ec\000\000\000\000011" -/* offset=3D129557 */ "branch_miss_rate\000Default\000branch\\-misses / br= anches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\0= 00\000001" -/* offset=3D129661 */ "l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-m= isses / L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\0= 00100%\000\000\000\000001" -/* offset=3D129777 */ "llc_miss_rate\000Default2\000LLC\\-load\\-misses / = LLC\\-loads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\00= 0\000001" -/* offset=3D129878 */ "l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-m= isses / L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\00= 0100%\000\000\000\000001" -/* offset=3D129993 */ "dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses = / dTLB\\-loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\0= 00\000\000001" -/* offset=3D130099 */ "itlb_miss_rate\000Default3\000iTLB\\-load\\-misses = / iTLB\\-loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\0= 00\000\000001" -/* offset=3D130205 */ "l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-= prefetch\\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.0= 5\000L1 prefetch miss rate\000\000100%\000\000\000\000001" -/* offset=3D130353 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 00" -/* offset=3D130376 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\000000" -/* offset=3D130440 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000" -/* offset=3D130607 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\000000" -/* offset=3D130672 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\000000" -/* offset=3D130740 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\000000" -/* offset=3D130812 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000" -/* offset=3D130907 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\000000" -/* offset=3D131042 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\000000" -/* offset=3D131107 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\000000" -/* offset=3D131176 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\000000" -/* offset=3D131247 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 00" -/* offset=3D131270 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 00" -/* offset=3D131293 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\000000" -/* offset=3D131314 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\000000" +/* offset=3D126205 */ "core_wide\000tool\0001 if not SMT, if SMT are event= s being gathered on all SMT threads 1 otherwise 0\000config=3D0xd\000\00000= \000\000\000\000\000" +/* offset=3D126319 */ "target_cpu\000tool\0001 if CPUs being analyzed, 0 i= f threads/processes\000config=3D0xe\000\00000\000\000\000\000\000" +/* offset=3D126403 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\00= 0event=3D0x8a\000\00000\000\000\000\000\000" +/* offset=3D126465 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\00= 0event=3D0x8b\000\00000\000\000\000\000\000" +/* offset=3D126527 */ "l3_cache_rd\000cache\000L3 cache access, read\000ev= ent=3D0x40\000\00000\000\000\000\000Attributable Level 3 cache access, read= \000" +/* offset=3D126625 */ "segment_reg_loads.any\000other\000Number of segment= register loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000= \000\000\000" +/* offset=3D126727 */ "dispatch_blocked.any\000other\000Memory cluster sig= nals to block micro-op dispatch for any reason\000event=3D9,period=3D200000= ,umask=3D0x20\000\00000\000\000\000\000\000" +/* offset=3D126860 */ "eist_trans\000other\000Number of Enhanced Intel Spe= edStep(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000= \00000\000\000\000\000\000" +/* offset=3D126978 */ "hisi_sccl,ddrc\000" +/* offset=3D126993 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write = commands\000event=3D2\000\00000\000\000\000\000\000" +/* offset=3D127063 */ "uncore_cbox\000" +/* offset=3D127075 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A = cross-core snoop resulted from L3 Eviction which misses in some processor c= ore\000event=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000" +/* offset=3D127229 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event= =3D0xe0\000\00000\000\000\000\000\000" +/* offset=3D127283 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000eve= nt=3D0xc0\000\00000\000\000\000\000\000" +/* offset=3D127341 */ "hisi_sccl,l3c\000" +/* offset=3D127355 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total rea= d hits\000event=3D7\000\00000\000\000\000\000\000" +/* offset=3D127423 */ "uncore_imc_free_running\000" +/* offset=3D127447 */ "uncore_imc_free_running.cache_miss\000uncore\000Tot= al cache misses\000event=3D0x12\000\00000\000\000\000\000\000" +/* offset=3D127527 */ "uncore_imc\000" +/* offset=3D127538 */ "uncore_imc.cache_hits\000uncore\000Total cache hits= \000event=3D0x34\000\00000\000\000\000\000\000" +/* offset=3D127603 */ "uncore_sys_ddr_pmu\000" +/* offset=3D127622 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cyc= les event\000event=3D0x2b\000v8\00000\000\000\000\000\000" +/* offset=3D127698 */ "uncore_sys_ccn_pmu\000" +/* offset=3D127717 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycle= s event\000config=3D0x2c\0000x01\00000\000\000\000\000\000" +/* offset=3D127794 */ "uncore_sys_cmn_pmu\000" +/* offset=3D127813 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts tota= l cache misses in first lookup result (high priority)\000eventid=3D1,type= =3D5\000(434|436|43c|43a).*\00000\000\000\000\000\000" +/* offset=3D127956 */ "CPUs_utilized\000Default\000(software@cpu\\-clock\\= ,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\= =3Dtask\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\00= 0\0001CPUs\000\000\000\000011" +/* offset=3D128142 */ "cs_per_second\000Default\000software@context\\-swit= ches\\,name\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\= 000011" +/* offset=3D128375 */ "migrations_per_second\000Default\000software@cpu\\-= migrations\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,nam= e\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtas= k\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001m= igrations/sec\000\000\000\000011" +/* offset=3D128635 */ "page_faults_per_second\000Default\000software@page\= \-faults\\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\0= 00011" +/* offset=3D128866 */ "insn_per_cycle\000Default\000instructions / cpu\\-c= ycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\= 000\000\000\000001" +/* offset=3D128979 */ "stalled_cycles_per_instruction\000Default\000max(st= alled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\0= 00Max front or backend stalls per instruction\000\000\000\000\000\000001" +/* offset=3D129143 */ "frontend_cycles_idle\000Default\000stalled\\-cycles= \\-frontend / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls= per cycle\000\000\000\000\000\000001" +/* offset=3D129273 */ "backend_cycles_idle\000Default\000stalled\\-cycles\= \-backend / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per= cycle\000\000\000\000\000\000001" +/* offset=3D129399 */ "cycles_frequency\000Default\000cpu\\-cycles / (soft= ware@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\= \-clock\\,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\= 000\000\000\000011" +/* offset=3D129575 */ "branch_frequency\000Default\000branches / (software= @cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-cl= ock\\,name\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/s= ec\000\000\000\000011" +/* offset=3D129755 */ "branch_miss_rate\000Default\000branch\\-misses / br= anches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\0= 00\000001" +/* offset=3D129859 */ "l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-m= isses / L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\0= 00100%\000\000\000\000001" +/* offset=3D129975 */ "llc_miss_rate\000Default2\000LLC\\-load\\-misses / = LLC\\-loads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\00= 0\000001" +/* offset=3D130076 */ "l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-m= isses / L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\00= 0100%\000\000\000\000001" +/* offset=3D130191 */ "dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses = / dTLB\\-loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\0= 00\000\000001" +/* offset=3D130297 */ "itlb_miss_rate\000Default3\000iTLB\\-load\\-misses = / iTLB\\-loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\0= 00\000\000001" +/* offset=3D130403 */ "l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-= prefetch\\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.0= 5\000L1 prefetch miss rate\000\000100%\000\000\000\000001" +/* offset=3D130551 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 00" +/* offset=3D130574 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\000000" +/* offset=3D130638 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000" +/* offset=3D130805 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\000000" +/* offset=3D130870 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\000000" +/* offset=3D130938 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\000000" +/* offset=3D131010 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000" +/* offset=3D131105 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\000000" +/* offset=3D131240 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\000000" +/* offset=3D131305 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\000000" +/* offset=3D131374 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\000000" +/* offset=3D131445 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 00" +/* offset=3D131468 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 00" +/* offset=3D131491 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\000000" +/* offset=3D131512 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\000000" ; =20 static const struct compact_pmu_event pmu_events__common_default_core[] = =3D { @@ -2587,6 +2589,7 @@ static const struct compact_pmu_event pmu_events__com= mon_software[] =3D { { 123607 }, /* task-clock\000software\000Per-task high-resolution timer ba= sed event\000config=3D1\000\000001e-6msec\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__common_tool[] =3D { +{ 126205 }, /* core_wide\000tool\0001 if not SMT, if SMT are events being = gathered on all SMT threads 1 otherwise 0\000config=3D0xd\000\00000\000\000= \000\000\000 */ { 125072 }, /* duration_time\000tool\000Wall clock interval time in nanose= conds\000config=3D1\000\00000\000\000\000\000\000 */ { 125286 }, /* has_pmem\000tool\0001 if persistent memory installed otherw= ise 0\000config=3D4\000\00000\000\000\000\000\000 */ { 125362 }, /* num_cores\000tool\000Number of cores. A core consists of 1 = or more thread, with each thread being associated with a logical Linux CPU\= 000config=3D5\000\00000\000\000\000\000\000 */ @@ -2598,6 +2601,7 @@ static const struct compact_pmu_event pmu_events__com= mon_tool[] =3D { { 125999 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyp= erthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000\000\00= 0\000 */ { 125218 }, /* system_time\000tool\000System/kernel time in nanoseconds\00= 0config=3D3\000\00000\000\000\000\000\000 */ { 126106 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter = (TSC) increases per second\000config=3D0xc\000\00000\000\000\000\000\000 */ +{ 126319 }, /* target_cpu\000tool\0001 if CPUs being analyzed, 0 if thread= s/processes\000config=3D0xe\000\00000\000\000\000\000\000 */ { 125148 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\= 000config=3D2\000\00000\000\000\000\000\000 */ =20 }; @@ -2621,23 +2625,23 @@ static const struct pmu_table_entry pmu_events__com= mon[] =3D { }; =20 static const struct compact_pmu_event pmu_metrics__common_default_core[] = =3D { -{ 127758 }, /* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPU= s\000\000\000\000011 */ -{ 129075 }, /* backend_cycles_idle\000Default\000stalled\\-cycles\\-backen= d / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per cycle\0= 00\000\000\000\000\000001 */ -{ 129377 }, /* branch_frequency\000Default\000branches / (software@cpu\\-c= lock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,na= me\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\0= 00\000\000011 */ -{ 129557 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\0= 00branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\00000= 1 */ -{ 127944 }, /* cs_per_second\000Default\000software@context\\-switches\\,n= ame\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-= clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\= 000\000Context switches per CPU second\000\0001cs/sec\000\000\000\000011 */ -{ 129201 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu= \\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\= \,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\= 000\000011 */ -{ 129993 }, /* dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\= -loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\000\000\0= 00001 */ -{ 128945 }, /* frontend_cycles_idle\000Default\000stalled\\-cycles\\-front= end / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls per cyc= le\000\000\000\000\000\000001 */ -{ 128668 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\00= 0insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\= 000\000001 */ -{ 130099 }, /* itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\= -loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\000\000\0= 00001 */ -{ 130205 }, /* l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch= \\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.05\000L1 = prefetch miss rate\000\000100%\000\000\000\000001 */ -{ 129661 }, /* l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / = L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\000100%\0= 00\000\000\000001 */ -{ 129878 }, /* l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / = L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\000100%\00= 0\000\000\000001 */ -{ 129777 }, /* llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-lo= ads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\000\000001= */ -{ 128177 }, /* migrations_per_second\000Default\000software@cpu\\-migratio= ns\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcp= u\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-cloc= k@)\000\000Process migrations to a new CPU per CPU second\000\0001migration= s/sec\000\000\000\000011 */ -{ 128437 }, /* page_faults_per_second\000Default\000software@page\\-faults= \\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\0= 00\000Page faults per CPU second\000\0001faults/sec\000\000\000\000011 */ -{ 128781 }, /* stalled_cycles_per_instruction\000Default\000max(stalled\\-= cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\000Max fr= ont or backend stalls per instruction\000\000\000\000\000\000001 */ +{ 127956 }, /* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPU= s\000\000\000\000011 */ +{ 129273 }, /* backend_cycles_idle\000Default\000stalled\\-cycles\\-backen= d / cpu\\-cycles\000backend_cycles_idle > 0.2\000Backend stalls per cycle\0= 00\000\000\000\000\000001 */ +{ 129575 }, /* branch_frequency\000Default\000branches / (software@cpu\\-c= lock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,na= me\\=3Dtask\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\0= 00\000\000011 */ +{ 129755 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\0= 00branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\00000= 1 */ +{ 128142 }, /* cs_per_second\000Default\000software@context\\-switches\\,n= ame\\=3Dcontext\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-= clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\= 000\000Context switches per CPU second\000\0001cs/sec\000\000\000\000011 */ +{ 129399 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu= \\-clock\\,name\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\= \,name\\=3Dtask\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\= 000\000011 */ +{ 130191 }, /* dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\= -loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\000\000\0= 00001 */ +{ 129143 }, /* frontend_cycles_idle\000Default\000stalled\\-cycles\\-front= end / cpu\\-cycles\000frontend_cycles_idle > 0.1\000Frontend stalls per cyc= le\000\000\000\000\000\000001 */ +{ 128866 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\00= 0insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\= 000\000001 */ +{ 130297 }, /* itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\= -loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\000\000\0= 00001 */ +{ 130403 }, /* l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch= \\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.05\000L1 = prefetch miss rate\000\000100%\000\000\000\000001 */ +{ 129859 }, /* l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / = L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\000100%\0= 00\000\000\000001 */ +{ 130076 }, /* l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / = L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\000100%\00= 0\000\000\000001 */ +{ 129975 }, /* llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-lo= ads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\000\000001= */ +{ 128375 }, /* migrations_per_second\000Default\000software@cpu\\-migratio= ns\\,name\\=3Dcpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcp= u\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-cloc= k@)\000\000Process migrations to a new CPU per CPU second\000\0001migration= s/sec\000\000\000\000011 */ +{ 128635 }, /* page_faults_per_second\000Default\000software@page\\-faults= \\,name\\=3Dpage\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-c= lock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\0= 00\000Page faults per CPU second\000\0001faults/sec\000\000\000\000011 */ +{ 128979 }, /* stalled_cycles_per_instruction\000Default\000max(stalled\\-= cycles\\-frontend, stalled\\-cycles\\-backend) / instructions\000\000Max fr= ont or backend stalls per instruction\000\000\000\000\000\000001 */ =20 }; =20 @@ -2650,29 +2654,29 @@ static const struct pmu_table_entry pmu_metrics__co= mmon[] =3D { }; =20 static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { -{ 126205 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event= =3D0x8a\000\00000\000\000\000\000\000 */ -{ 126267 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event= =3D0x8b\000\00000\000\000\000\000\000 */ -{ 126529 }, /* dispatch_blocked.any\000other\000Memory cluster signals to = block micro-op dispatch for any reason\000event=3D9,period=3D200000,umask= =3D0x20\000\00000\000\000\000\000\000 */ -{ 126662 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R= ) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\0= 00\000\000\000\000 */ -{ 126329 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x= 40\000\00000\000\000\000\000Attributable Level 3 cache access, read\000 */ -{ 126427 }, /* segment_reg_loads.any\000other\000Number of segment registe= r loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000\000\000= \000 */ +{ 126403 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event= =3D0x8a\000\00000\000\000\000\000\000 */ +{ 126465 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event= =3D0x8b\000\00000\000\000\000\000\000 */ +{ 126727 }, /* dispatch_blocked.any\000other\000Memory cluster signals to = block micro-op dispatch for any reason\000event=3D9,period=3D200000,umask= =3D0x20\000\00000\000\000\000\000\000 */ +{ 126860 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R= ) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\0= 00\000\000\000\000 */ +{ 126527 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x= 40\000\00000\000\000\000\000Attributable Level 3 cache access, read\000 */ +{ 126625 }, /* segment_reg_loads.any\000other\000Number of segment registe= r loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000\000\000= \000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_d= drc[] =3D { -{ 126795 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands= \000event=3D2\000\00000\000\000\000\000\000 */ +{ 126993 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands= \000event=3D2\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l= 3c[] =3D { -{ 127157 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\0= 00event=3D7\000\00000\000\000\000\000\000 */ +{ 127355 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\0= 00event=3D7\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox= [] =3D { -{ 127031 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\00= 0\00000\000\000\000\000\000 */ -{ 127085 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc= 0\000\00000\000\000\000\000\000 */ -{ 126877 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-co= re snoop resulted from L3 Eviction which misses in some processor core\000e= vent=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000 */ +{ 127229 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\00= 0\00000\000\000\000\000\000 */ +{ 127283 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc= 0\000\00000\000\000\000\000\000 */ +{ 127075 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-co= re snoop resulted from L3 Eviction which misses in some processor core\000e= vent=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[= ] =3D { -{ 127340 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000even= t=3D0x34\000\00000\000\000\000\000\000 */ +{ 127538 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000even= t=3D0x34\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_= free_running[] =3D { -{ 127249 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache= misses\000event=3D0x12\000\00000\000\000\000\000\000 */ +{ 127447 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache= misses\000event=3D0x12\000\00000\000\000\000\000\000 */ =20 }; =20 @@ -2685,46 +2689,46 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_cpu[] =3D { { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name =3D { 126780 /* hisi_sccl,ddrc\000 */ }, + .pmu_name =3D { 126978 /* hisi_sccl,ddrc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name =3D { 127143 /* hisi_sccl,l3c\000 */ }, + .pmu_name =3D { 127341 /* hisi_sccl,l3c\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_cbox, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name =3D { 126865 /* uncore_cbox\000 */ }, + .pmu_name =3D { 127063 /* uncore_cbox\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name =3D { 127329 /* uncore_imc\000 */ }, + .pmu_name =3D { 127527 /* uncore_imc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_= running), - .pmu_name =3D { 127225 /* uncore_imc_free_running\000 */ }, + .pmu_name =3D { 127423 /* uncore_imc_free_running\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 130353 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */ -{ 131042 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\000000 */ -{ 130812 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000 */ -{ 130907 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\000000 */ -{ 131107 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\000000 */ -{ 131176 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\000000 */ -{ 130440 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000 */ -{ 130376 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\000000 */ -{ 131314 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\000000 */ -{ 131247 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */ -{ 131270 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */ -{ 131293 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */ -{ 130740 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\000000 */ -{ 130607 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\000000 */ -{ 130672 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\000000 */ +{ 130551 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */ +{ 131240 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\000000 */ +{ 131010 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000 */ +{ 131105 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\000000 */ +{ 131305 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\000000 */ +{ 131374 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\000000 */ +{ 130638 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000 */ +{ 130574 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\000000 */ +{ 131512 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\000000 */ +{ 131445 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */ +{ 131468 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */ +{ 131491 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */ +{ 130938 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\000000 */ +{ 130805 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\000000 */ +{ 130870 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\000000 */ =20 }; =20 @@ -2737,13 +2741,13 @@ static const struct pmu_table_entry pmu_metrics__te= st_soc_cpu[] =3D { }; =20 static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ccn_pmu[] =3D { -{ 127519 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\= 000config=3D0x2c\0000x01\00000\000\000\000\000\000 */ +{ 127717 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\= 000config=3D0x2c\0000x01\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= cmn_pmu[] =3D { -{ 127615 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache = misses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(4= 34|436|43c|43a).*\00000\000\000\000\000\000 */ +{ 127813 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache = misses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(4= 34|436|43c|43a).*\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ddr_pmu[] =3D { -{ 127424 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles even= t\000event=3D0x2b\000v8\00000\000\000\000\000\000 */ +{ 127622 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles even= t\000event=3D0x2b\000v8\00000\000\000\000\000\000 */ =20 }; =20 @@ -2751,17 +2755,17 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_sys[] =3D { { .entries =3D pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_p= mu), - .pmu_name =3D { 127500 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name =3D { 127698 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_p= mu), - .pmu_name =3D { 127596 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name =3D { 127794 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_p= mu), - .pmu_name =3D { 127405 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name =3D { 127603 /* uncore_sys_ddr_pmu\000 */ }, }, }; =20 diff --git a/tools/perf/util/expr.c b/tools/perf/util/expr.c index 4df56f2b283d..465fe2e9bbbe 100644 --- a/tools/perf/util/expr.c +++ b/tools/perf/util/expr.c @@ -401,17 +401,12 @@ double expr__get_literal(const char *literal, const s= truct expr_scanner_ctx *ctx if (ev !=3D TOOL_PMU__EVENT_NONE) { u64 count; =20 - if (tool_pmu__read_event(ev, /*evsel=3D*/NULL, &count)) + if (tool_pmu__read_event(ev, /*evsel=3D*/NULL, + ctx->system_wide, ctx->user_requested_cpu_list, + &count)) result =3D count; else pr_err("Failure to read '%s'", literal); - - } else if (!strcmp("#core_wide", literal)) { - result =3D core_wide(ctx->system_wide, ctx->user_requested_cpu_list) - ? 1.0 : 0.0; - } else if (!strcmp("#target_cpu", literal)) { - result =3D (ctx->system_wide || ctx->user_requested_cpu_list) - ? 1.0 : 0.0; } else { pr_err("Unrecognized literal '%s'", literal); } diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index c1547128c396..b3b482e1808f 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -72,6 +72,8 @@ static int prepare_metric(const struct metric_expr *mexp, case TOOL_PMU__EVENT_SLOTS: case TOOL_PMU__EVENT_SMT_ON: case TOOL_PMU__EVENT_SYSTEM_TSC_FREQ: + case TOOL_PMU__EVENT_CORE_WIDE: + case TOOL_PMU__EVENT_TARGET_CPU: default: pr_err("Unexpected tool event '%s'", evsel__name(metric_events[i])); abort(); diff --git a/tools/perf/util/tool_pmu.c b/tools/perf/util/tool_pmu.c index f075098488ba..a72c665ee644 100644 --- a/tools/perf/util/tool_pmu.c +++ b/tools/perf/util/tool_pmu.c @@ -6,6 +6,7 @@ #include "pmu.h" #include "print-events.h" #include "smt.h" +#include "stat.h" #include "time-utils.h" #include "tool_pmu.h" #include "tsc.h" @@ -30,6 +31,8 @@ static const char *const tool_pmu__event_names[TOOL_PMU__= EVENT_MAX] =3D { "slots", "smt_on", "system_tsc_freq", + "core_wide", + "target_cpu", }; =20 bool tool_pmu__skip_event(const char *name __maybe_unused) @@ -329,7 +332,11 @@ static bool has_pmem(void) return has_pmem; } =20 -bool tool_pmu__read_event(enum tool_pmu_event ev, struct evsel *evsel, u64= *result) +bool tool_pmu__read_event(enum tool_pmu_event ev, + struct evsel *evsel, + bool system_wide, + const char *user_requested_cpu_list, + u64 *result) { const struct cpu_topology *topology; =20 @@ -421,6 +428,14 @@ bool tool_pmu__read_event(enum tool_pmu_event ev, stru= ct evsel *evsel, u64 *resu *result =3D arch_get_tsc_freq(); return true; =20 + case TOOL_PMU__EVENT_CORE_WIDE: + *result =3D core_wide(system_wide, user_requested_cpu_list) ? 1 : 0; + return true; + + case TOOL_PMU__EVENT_TARGET_CPU: + *result =3D system_wide || (user_requested_cpu_list !=3D NULL) ? 1 : 0; + return true; + case TOOL_PMU__EVENT_NONE: case TOOL_PMU__EVENT_DURATION_TIME: case TOOL_PMU__EVENT_USER_TIME: @@ -452,11 +467,16 @@ int evsel__tool_pmu_read(struct evsel *evsel, int cpu= _map_idx, int thread) case TOOL_PMU__EVENT_SLOTS: case TOOL_PMU__EVENT_SMT_ON: case TOOL_PMU__EVENT_SYSTEM_TSC_FREQ: + case TOOL_PMU__EVENT_CORE_WIDE: + case TOOL_PMU__EVENT_TARGET_CPU: if (evsel->prev_raw_counts) old_count =3D perf_counts(evsel->prev_raw_counts, cpu_map_idx, thread); val =3D 0; if (cpu_map_idx =3D=3D 0 && thread =3D=3D 0) { - if (!tool_pmu__read_event(ev, evsel, &val)) { + if (!tool_pmu__read_event(ev, evsel, + stat_config.system_wide, + stat_config.user_requested_cpu_list, + &val)) { count->lost++; val =3D 0; } diff --git a/tools/perf/util/tool_pmu.h b/tools/perf/util/tool_pmu.h index d642e7d73910..f1714001bc1d 100644 --- a/tools/perf/util/tool_pmu.h +++ b/tools/perf/util/tool_pmu.h @@ -22,6 +22,8 @@ enum tool_pmu_event { TOOL_PMU__EVENT_SLOTS, TOOL_PMU__EVENT_SMT_ON, TOOL_PMU__EVENT_SYSTEM_TSC_FREQ, + TOOL_PMU__EVENT_CORE_WIDE, + TOOL_PMU__EVENT_TARGET_CPU, =20 TOOL_PMU__EVENT_MAX, }; @@ -34,7 +36,12 @@ enum tool_pmu_event tool_pmu__str_to_event(const char *s= tr); bool tool_pmu__skip_event(const char *name); int tool_pmu__num_skip_events(void); =20 -bool tool_pmu__read_event(enum tool_pmu_event ev, struct evsel *evsel, u64= *result); +bool tool_pmu__read_event(enum tool_pmu_event ev, + struct evsel *evsel, + bool system_wide, + const char *user_requested_cpu_list, + u64 *result); + =20 u64 tool_pmu__cpu_slots_per_cycle(void); =20 --=20 2.51.2.1041.gc1ab5b90ca-goog