From nobody Sat Feb 7 19:45:33 2026 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C65F4325723 for ; Tue, 11 Nov 2025 19:26:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889202; cv=none; b=EV+Skd+DIwMj4SxOZUJD7LE9ynUXlmYz/klxY0ftQImj0mHZ6VWmMoa1kORrknXv4WQqAvQLMImyoDdQ3cvSQAIzHIAl79MR47wOkXw87aINX+I3TICMpJeQLyO380qtIoydX6iOvKHQEkHlj5u0AExzXYjXg/eZ5ISw9Fz/W7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889202; c=relaxed/simple; bh=ntK/UrJHb73TADpVCn2bgPri20vaZbmZx8YTKPY57c4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UycdPAVfTdDgWDZiT9px/DZYO7ENJ1ETVUfia4QP7AgG999gDI+OvNVPH570Ji9yxOqcEm8mDBKTh7LjnPgjFxYuZUUCP2ol8P8Brum3qXcSqSfr2dtCOcXeySzgNuebj8+n74QmF2ZpJJkX5DMjoQxIeOSoVxmOMD/gL1DTDVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=XT9e4kA/; arc=none smtp.client-ip=209.85.215.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="XT9e4kA/" Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-ba599137cf8so346a12.0 for ; Tue, 11 Nov 2025 11:26:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1762889200; x=1763494000; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TOiFmH8IcpAAycagiDhvMebDsaH97fid1dP1cj7j5ro=; b=XT9e4kA/hlTvcKys4mxxf6CC7lEqMrIRPqbikPmjxGMyD49AuMB/Yj6sZ8O+6HW0Sf PH4vTdS1NqQxWK8RRU5wGJmkcpuSMb4v92p7tm4TybxCf2gHDTAVYEpgprHBvXBFWjmM 5TSJb8MhS0txT93GDt2y9i4trrIjI5FLnQqTA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762889200; x=1763494000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TOiFmH8IcpAAycagiDhvMebDsaH97fid1dP1cj7j5ro=; b=lJp+tDr/EduBJHOQPZhrdbX1kVVrAJYR2WjEjLluc28LyKCAvPDyleHhyNOPLfD8/r F1WlPz2xd1IuG2xSnaU3BdrFMo3Qp1G5WhsQISf5CHEOB7bZM0LgP7PhMMj/ii8xlqXO 2D9NUj/qoVRYGVAeBs/C1Pw77RDD4MMPv7fp4h8RhCsHIWGaoIFz1M7O8FRw3gOEs45l EVn1AXNtXro+NpNt8eoBn1yr6qUZpL8hvqRjSVhPaZ18dQdqhPAB+iILHSMZSX1OLdPi a2SlC1WYlr8uvNwjwDcOU/h4ykAG3BxjnjU1vlPuFUGcbzqyQDijkE7i1QvWtbBQa/1n 9uCA== X-Forwarded-Encrypted: i=1; AJvYcCVxXdsj3EILNl/IVSfWSXDx92WxRgMqada6GhIUCTjErLI/PIOSyhyhE/dW8GfLPtqQ2vh32dfynRPTaW8=@vger.kernel.org X-Gm-Message-State: AOJu0YwkyPPdN/P/s/t2LsCCYtbTsBN67Z7F9VXkuqawIATvR/+btGfT KUMDXF9GHZ2vCpxw74kHRwzOYtbTgTNDhkpVpDs5OivECds3YIOWWxnBe7S+h9wpWg== X-Gm-Gg: ASbGncukPQGo19KncZ3OQPi4/Ry8ki08ur7MrbpK4CLW9xTRtkgUg7vHj7UUdG+7+Pe LHyOawhv6s4UipLneIkcQJoTO+C8osymuvZy/jR0H6OaIMRAJbOq0Uj7nA2Mo7Uwia3EA8YSE1a IQvzkhX27aZEH3KDJpR72TjJX43KsU9AQTrRorf0wRTY5ksc93IF+HPP9RS/ZWfAAwmMlG+d/pN v741ovBtKwk3rv3Tt4sLVufMu2ywE7xcPYY62bixHzP+oRhLKCNRB23OGNtwXtyyx14Scs3ypXC APi5Fc1Ib/LP6cedVv4VikC0jdyEqEQ9kyMmKxkimtwnJhBOnyi1zdOVlJzEvW4NWNOba5ytVTb rLNOd4dycQMMBHYb78wRm4hTYOFUcqjYgKYEaXz1Nv9EsbnbzO2gusJBkeGmGg6z33sqDodVYoj y/D93ULPuSjTHnL6NrXJrki+osXqs0iE0FtuUNv6X9AsX6bpakbzkuomhSPrw= X-Google-Smtp-Source: AGHT+IExodWlioL1RP371Naq0b/EutoicCgiE5LxahmeztexeT56t42134E6a4LSJf3+oS+yxTk0Jg== X-Received: by 2002:a17:903:234d:b0:296:5ebe:8fa with SMTP id d9443c01a7336-2984094a5bcmr45666845ad.23.1762889200005; Tue, 11 Nov 2025 11:26:40 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2a00:79e0:2e7c:8:ba9f:d4c6:9323:4864]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2984dcd0974sm4861075ad.90.2025.11.11.11.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 11:26:39 -0800 (PST) From: Douglas Anderson To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus Cc: linux-samsung-soc@vger.kernel.org, Roy Luo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Julius Werner , William McVicker , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: arm: google: Add bindings for frankel/blazer/mustang Date: Tue, 11 Nov 2025 11:22:04 -0800 Message-ID: <20251111112158.1.I72a0b72562b85d02fee424fed939fea9049ddda9@changeid> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog In-Reply-To: <20251111192422.4180216-1-dianders@chromium.org> References: <20251111192422.4180216-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add top-level DT bindings useful for Pixel 10 (frankel), Pixel 10 Pro (blazer), and Pixel 10 Pro XL (mustang). Since overlays are fairly well-supported these days and the downstream Pixel bootloader assumes that the SoC is the base overlay and specific board revisions are overlays, reflect the SoC / board split in the bindings. The SoC in the Pixel 10 series has the marketing name of "Tensor G5". Despite the fact that it sounds very similar to the "Tensor G4", it's a very different chip. Tensor G4 was, for all intents and purposes, a Samsung Exynos offshoot whereas Tensor G5 is entirely its own SoC. This SoC is known internally as "laguna" and canonically referred to in code as "lga". There are two known revisions of the SoC: an A0 pre-production variant (ID 0x000500) and a B0 variant (ID 0x000510) used in production. The ID is canonicaly broken up into a 16-bit SoC product ID, a 4-bit major rev, and a 4-bit minor rev. The dtb for all supported SoC revisions is appended to one of the boot partitions and the bootloader will look at the device trees and pick the correct one. The current bootloader uses a downstream `soc_compatible` node to help it pick the correct device tree. It looks like this: soc_compatible { B0 { description =3D "LGA B0"; product_id =3D <0x5>; major =3D <0x1>; minor =3D <0x0>; pkg_mode =3D <0x0>; }; }; Note that `pkg_mode` isn't currently part of the ID on the SoC and the bootloader always assumes 0 for it. In this patch, put the SoC IDs straight into the compatible. Though the bootloader doesn't look at the compatible at the moment, this should be easy to teach the bootloader about. Boards all know their own platform_id / product_id / stage / major / minor / variant. For instance, Google Pixel 10 Pro XL MP1 is: * platform_id (8-bits): 0x07 - frankel/blazer/mustang * product_id (8-bits): 0x05 - mustang * stage (4-bits): 0x06 - MP * major (8-bits): 0x01 - MP 1 * minor (8-bits): 0x00 - MP 1.0 * variant (8-bits): 0x00 - No special variant When board overlays are packed into the "dtbo" partition, a tool (`mkdtimg`) extracts a board ID and board rev from the overlay and stores that as metadata with the overlay. Downstream, the dtso intended for the Pixel 10 Pro XL MP1 has the following properties at its top-level: board_id =3D <0x70506>; board_rev =3D <0x010000>; The use of top-level IDs can probably be used for overlays upstream as well, but also add the IDs to the compatible string in case it's useful. Compatible strings are added for all board revisions known to be produced based on downstream sources. A few notes: * If you look at `/proc/device-tree/compatible` and `/proc/device-tree/model` on a running device, that won't necessarily be an exact description of the hardware you're running on. If the bootloader can't find a device tree that's an exact match then it will pick the best match (within reason--it will never pick a device tree for a different product--just for different revs of the same product). * There is no merging of the top-level compatible from the SoC and board. The compatible string containing IDs for the SoC will not be found in the device-tree passed to the OS. Signed-off-by: Douglas Anderson --- In the past, attempts to have the SoC as a base device tree and boards supported as overlays has been NAKed. From a previous discussion [1] "Nope, boards are not overlays. Boards are DTB." I believe this needs to be relitigated. In the previous NAK, I didn't see any links to documentation explicitly stating that DTBs have to represent boards. It's also unclear, at least to me, _why_ a DTB would be limited to represent a "board" nor what the definition of a "board" is. As at least one stab at why someone might not want an overlay scheme like this, one could point out that the top-level compatible can be a bit of a mess. Specifically in this scheme the board "compatible" from the overlay will fully replace/hide the SoC "compatible" from the base SoC. If this is truly the main concern, it wouldn't be terribly hard to add a new semantic (maybe selectable via a new additional property?) that caused the compatible strings to be merged in a reasonable way. Aside from dealing with the compatible string, let's think about what a "board" is. I will make the argument here that the SoC qualifies as a "board" and that the main PCB of a phone can be looked at as a "cape" for this SoC "board". While this may sound like a stretch, I would invite a reader to propose a definition of "board" that excludes this. Specifically, it can be noted: * I have a development board at my desk that is "socketed". That is, I can pull the SoC out and put a different one in. I can swap in a "rev A0" or a "rev B0" SoC into this socket. Conceivably, I could even put a "Tensor G6", G7, G8, or G999 in the socket if it was compatible. In this sense, the "SoC" is a standalone thing that can be attached to the devboard "cape". The SoC being a standalone thing is in the name. It's a "system" on a chip. * In case the definition of a board somehow needs a PCB involved, I can note that on my dev board the CPU socket is soldered onto to a CPU daughtercard (a PCB!) that then has a board-to-board connector to the main PCB. * Perhaps one could argue that a dev board like I have describe would qualify for this SoC/board overlay scheme but that a normal cell phone wouldn't because the SoC isn't removable. Perhaps removability is a requirement here? If so, imagine if some company took a Raspberry Pi, soldered some components directly onto the "expansion" pins, and resold that to consumers. Does this mean they can't use overlays? To me, the above arguments justify why SoC DTBs + "board" overlays should be accepted. As far as I can tell, there is no downside and many people who would be made happy with this. [1] https://lore.kernel.org/all/dbeb28be-1aac-400b-87c1-9764aca3a799@kernel= .org/ .../devicetree/bindings/arm/google.yaml | 87 +++++++++++++++---- 1 file changed, 68 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentat= ion/devicetree/bindings/arm/google.yaml index 99961e5282e5..f9f9ea1c8050 100644 --- a/Documentation/devicetree/bindings/arm/google.yaml +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -13,27 +13,18 @@ description: | ARM platforms using SoCs designed by Google branded "Tensor" used in Pix= el devices. =20 - Currently upstream this is devices using "gs101" SoC which is found in P= ixel - 6, Pixel 6 Pro and Pixel 6a. + These bindings for older Pixel devices don't use device tree overlays so + no separate SoC entry is added. This may change in the future. =20 - Google have a few different names for the SoC: - - Marketing name ("Tensor") - - Codename ("Whitechapel") - - SoC ID ("gs101") - - Die ID ("S5P9845") - - Likewise there are a couple of names for the actual device - - Marketing name ("Pixel 6") - - Codename ("Oriole") - - Devicetrees should use the lowercased SoC ID and lowercased board codena= me, - e.g. gs101 and gs101-oriole. + Newer Pixel devices are expected to have the SoC device tree as the base + and specific board device trees as overlays. =20 properties: $nodename: const: '/' compatible: oneOf: + # Google Tensor G1 AKA gs101 AKA whitechapel AKA Die ID S5P9845 boar= ds - description: Google Pixel 6 or 6 Pro (Oriole or Raven) items: - enum: @@ -41,13 +32,71 @@ properties: - google,gs101-raven - const: google,gs101 =20 + # Google Tensor G5 AKA lga (laguna) SoC and boards + - description: Tensor G5 SoC (laguna) + items: + - enum: + - google,soc-id-0005-rev-00 # A0 + - google,soc-id-0005-rev-10 # B0 + - const: google,lga + - description: Google Pixel 10 Board (Frankel) + items: + - enum: + - google,pixel-id-070302-rev-000000 # Proto 0 + - google,pixel-id-070302-rev-010000 # Proto 1 + - google,pixel-id-070302-rev-010100 # Proto 1.1 + - google,pixel-id-070303-rev-010000 # EVT 1 + - google,pixel-id-070303-rev-010100 # EVT 1.1 + - google,pixel-id-070303-rev-010101 # EVT 1.1 Wingboard + - google,pixel-id-070304-rev-010000 # DVT 1 + - google,pixel-id-070305-rev-010000 # PVT 1 + - google,pixel-id-070306-rev-010000 # MP 1 + - const: google,lga-frankel + - const: google,lga + - description: Google Pixel 10 Pro Board (Blazer) + items: + - enum: + - google,pixel-id-070402-rev-000000 # Proto 0 + - google,pixel-id-070402-rev-010000 # Proto 1 + - google,pixel-id-070402-rev-010100 # Proto 1.1 + - google,pixel-id-070403-rev-010000 # EVT 1 + - google,pixel-id-070403-rev-010100 # EVT 1.1 + - google,pixel-id-070404-rev-010000 # DVT 1 + - google,pixel-id-070405-rev-010000 # PVT 1 + - google,pixel-id-070406-rev-010000 # MP 1 + - const: google,lga-blazer + - const: google,lga + - description: Google Pixel 10 Pro XL Board (Mustang) + items: + - enum: + - google,pixel-id-070502-rev-000000 # Proto 0 + - google,pixel-id-070502-rev-010000 # Proto 1 + - google,pixel-id-070502-rev-010100 # Proto 1.1 + - google,pixel-id-070502-rev-010101 # Proto 1.1 Wingboard + - google,pixel-id-070503-rev-010000 # EVT 1 + - google,pixel-id-070503-rev-010100 # EVT 1.1 + - google,pixel-id-070503-rev-010101 # EVT 1.1 Wingboard + - google,pixel-id-070504-rev-010000 # DVT 1 + - google,pixel-id-070505-rev-010000 # PVT 1 + - google,pixel-id-070506-rev-010000 # MP 1 + - const: google,lga-mustang + - const: google,lga + +allOf: # Bootloader requires empty ect node to be present - ect: - type: object - additionalProperties: false + - if: + properties: + compatible: + contains: + const: google,gs101 + then: + properties: + ect: + type: object + additionalProperties: false =20 -required: - - ect + required: + - ect =20 additionalProperties: true =20 --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sat Feb 7 19:45:33 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69BF5326D6D for ; Tue, 11 Nov 2025 19:26:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889204; cv=none; b=HGk9DCCgMlpamLC13tKR43OQle/hKv+wBqTZWQNtIKNUoq/RdSX1hNU+JSJyKm4+xDXawlEk41t3FUabTEMVaJbgWB4vdjLn3UAbeJ9sFji7CyktgfGVTb22uG9hwjxeK4Hux4fTGxCADKd0se/h4cfE8VkWdNFQkhprOn5mWpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889204; c=relaxed/simple; bh=PuM1AACg2d+I1zG41cyM/NLvQTJ2/H6JFpNiUOMJQO8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Tu9IXk+uszdgE8Zrt4FpnCi3YKp1g3cQIufDMAoOcMdhu2wgxrMI2tIHWOHbGdmoD7l5KhmkfHd3bR3/iT8EJ1WNwsitE7hKm6Oly094mWcRJxfQ3USA99m0z6EFvOmoIoLVo4ElvMkffjm5c/EGN/1aX0KUrAYcl0Mr48YNz+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=czTSgGHG; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="czTSgGHG" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-2957850c63bso17375ad.0 for ; Tue, 11 Nov 2025 11:26:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1762889203; x=1763494003; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BdNxsDJ9m7UGbRcYc8TABHid3VHQHv2h0LQ2tYeasVo=; b=czTSgGHGABHc27+UBO36i8NZqqDMtOKmZJeshxFQSzE7w8yHWNBVghJ1OKn+sh/OTr pO7ohLbAh3htpT5Tab1CnPR28QtdkyFyl1OX0XN2t7g8oGbTYQI7SVLTchelDU8JgIxB AvhMjwViVRw3M+mr9FgRdEyIebm2BDdUMFLy8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762889203; x=1763494003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=BdNxsDJ9m7UGbRcYc8TABHid3VHQHv2h0LQ2tYeasVo=; b=YqnaV78K04LoXwfiVsBMTqbvBnQeQG/OTsOxLI4NWw564NNL8GIl0jvjCQC8vBdG0M tZ1XYmq7SM5CQTmVEsaANHxoL7309O0HnrTDWpQNMTlUZukEh7QpuIVj3kSKaJLW4+oQ +Hz4rKPH0YM4YZM0W9cK0uTRdSQ5NOveQ5vHLgN++fjFM7YSq0yj6G6AZ1g1aRRf4xAl 0Mvlm1iXnNg7P+wl3r6VcCqFhE5bEzh0gdwvKiCN3ROZeA2LDIvDwZyJLPFKfGTvxkxF 4dXHaiaAsTtKxlnUvNa1sbKSvOzPUw5P6Oy6pyqBgHJRtZul2XZu5HDxvXqJsXwJ2cs5 z4EQ== X-Forwarded-Encrypted: i=1; AJvYcCUKUG+lZbDgWCaPTZ2I4rBNdXMMua/DVFzB9dqvZ6lfnLSxcsavdRVVLUh5Obp8XvSdbIbx8rAMCz/qYiQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzgxlHlXcXEMIDYyl3F/BkEg+h63RYfJ6oLHGvN0zu9K4HYmCRF 099J2if0na6xN/pjilVntssAyFie/Ax2AB6rnj96zbghpoEPuQEvSZTVao+4SylP0g== X-Gm-Gg: ASbGncsuQs9QkQwXuFQ0+ePhm2QrKU3Mn8YalAdIgxH5SnOea7nBgTybkw2xUjlKqgh H2cRsZC6vDyVypIAZdLtSicrNVG/8EztDvCEAkMkqhLTliZG9+46pT3oIp5vpc0KvfNLwr+yqk/ OqKNaIEPt47JbWhtRjDTyZEwZsr/2NGrGinurISgGIYBTSqnyche3US41prJtcqemUKWR03BxDc /F00deuqSuyB7JZlTOw+fNHmqEMdTXIgd+GmNaYbAjS1MilsDXM92AHA4wMkg8ZA2hUMLf+rAHt eN+/ySoSY652RJReDeJrZmcWIxxbfPrWix4fWc70lXTJmFzSbNPuVrRj8wzSJnj4prEHBbuY8ty LnKjfTXMoGLEIbXNfBHr+P/6pGShH5WF2qQt5JIa0RjNVye4jKnVK4QTl9MHrhDVUicnpa1DEMC yT5BfSIRW9mMzEJK9ymt+AbGVyYpYDGBX57z9lEacbbdRGrbX7Cp3GQEGCbSBDzSeF4OJ/Jg== X-Google-Smtp-Source: AGHT+IFUhgG9WpQVUBXncCvJtpv/AdoMd+/rut91fwnGCd4l3imDRqM9pTW1tm/5jIJ9RftY3SLcaw== X-Received: by 2002:a17:903:944:b0:295:28a4:f0c6 with SMTP id d9443c01a7336-2984ec88253mr6581805ad.0.1762889202759; Tue, 11 Nov 2025 11:26:42 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2a00:79e0:2e7c:8:ba9f:d4c6:9323:4864]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2984dcd0974sm4861075ad.90.2025.11.11.11.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 11:26:41 -0800 (PST) From: Douglas Anderson To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus Cc: linux-samsung-soc@vger.kernel.org, Roy Luo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Julius Werner , William McVicker , Douglas Anderson , Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 2/4] dt-bindings: serial: snps-dw-apb-uart: Add "google,lga-uart" Date: Tue, 11 Nov 2025 11:22:05 -0800 Message-ID: <20251111112158.2.I040412d80bc262f213444aa6f6ec4f0334315a67@changeid> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog In-Reply-To: <20251111192422.4180216-1-dianders@chromium.org> References: <20251111192422.4180216-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Google Tensor G5 SoC (known as "laguna" and canonically written in code as "lga") has a UART based on Designware IP. The UART appears to work reasonably well, at least for serial console, with the existing driver in Linux. Add a compatible for this UART based on the canonical "lga" name for this SoC with a fallback to the existing "snps,dw-apb-uart". Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97afc..df6a7558a9f2 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -53,6 +53,7 @@ properties: - enum: - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart + - google,lga-uart - rockchip,px30-uart - rockchip,rk1808-uart - rockchip,rk3036-uart --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sat Feb 7 19:45:33 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29DC2327216 for ; Tue, 11 Nov 2025 19:26:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889207; cv=none; b=OyBphC6jzTt0IsNmdF9SWB5/NtcwY3Z1JOp9c2aPz5X48KktSyMSwh6WApf5Ymzj7GUetYKDefpK16uLNYIXgDScAmguaq4yEHrkifz1Q8LB1JVUAr1oE4Mp/IJRj1Kv6Nxd9DocJpsXAmxLn8HmgAi2hGw9bAC03PDLxLby+dM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889207; c=relaxed/simple; bh=fwml7KgkE1J3Ai4MZr/kpN1tNeDhuCSqy9eCyYXxwZ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ISSTr3wdxHWY3WyMbuTYlABVjTht/4mruVMosYhzDQM+KWrNei9vfj3QdUSuil9kpmAgam7lXdHvhUzKzr7CFRuRNqAuwf8aL859byN10vXJCa5o4lOrBOqCto7w6oBIvGEVJH3DtsQLkQwaTzamMlgl6KAyWorkb1owKgbAKfA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=i1cBkiZt; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="i1cBkiZt" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-29844c68068so440285ad.2 for ; Tue, 11 Nov 2025 11:26:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1762889205; x=1763494005; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=imIwJUQw0bI9H7QFTurPbNC+Bd5DwsLxwxGR/tUh3uE=; b=i1cBkiZtj4ACKpZgXrCK8MXtMksxE0MitPhMh2HvBM1yS0G2Phu8TuEgf65aw/W1fp WfcvIe1o7HsyKjzXa4E8OkelO1nC5JkyccOOuCYx+r0A3K/tPblUj0i5aeV0TE5gfW7m 7obQszC6ve+2NbSc8NYcHZMtacc9wgh9egSLo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762889205; x=1763494005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=imIwJUQw0bI9H7QFTurPbNC+Bd5DwsLxwxGR/tUh3uE=; b=Eiwcqy5gNPhYj2xL0aDtKcBtWT4I5reaxm5VRa3NRpxrLy6po6IGr6U2CyypNkkQNi afboXpGLUrwYjY1G0C1AWrCt2VBa6DAJm/3BFRyZiieLKPzIgmUvRGM+sej1wcxsnk33 2sQm/pn7p1Ls79nIufrX5IAdbGg2WUWgM1jbD9JdBUA1WkvktDcMMVr9kYWK3L7UxAQw ScQStt/RE6tntJ8ktp1wMsH8x96DmAjr0hPsDx0ao8WmnTGPiEAX39pCV2ii3ll/ncIP EP6hjyS7TyKHVcC+SCIGIGmhZOO3gdqdr0E9HP2J02Ww4vFwLwSee9dRNRH+FEqlAdEh iHSA== X-Forwarded-Encrypted: i=1; AJvYcCWOxBP/3nugAWzRxhUWpJU3EVqrjkKLKjtOrqLCbCKfMx/lIMX0BIrrIfvL3uZbmuKkEoct8/P0WoteDW0=@vger.kernel.org X-Gm-Message-State: AOJu0YyQUpw4Pu18jh7tq4N4sTqRi/kW+AxOZ8+foelFfxzc4LGgCrbI NX7NdBzyCVWIdiEXI+qmsYIeftf0JCe0FdI3ihuCn2aAsF0ohxz/KaeXCNSdGKdAPQ== X-Gm-Gg: ASbGncte9AeYiyxG0rySLc90pbPohic7uD2FeuwC4V0KVLplsx5JfiqxyfpGx+twgsq 9dbqaVsp6oMgfjf9IlCIqzEZ4hdbcnTCcdSAfFGkBaznN/St1yy0xZbMwjOYjEmOUW3+SbgmN71 QUpZKeo1j2Mg4k7FKvRWTmkOrQuKlw31OQHd+yW4BVHUR/axWqntNYAnLP6ENPIgZdGNwKyxmyf G9d9zYMkwbpUqOCHzL5DDprDX6Bat18mXI1pFSuz+f2baXU+1lS/yzl7J5ESOa+Sg8dtOqCrtWE ofjzFgVc8e21Vv9J/L6g+lZ5yAbG9ZkLM7f9w/gDz6VzNt1q/7EuvXXsLV0AYuoBMeQC36Xkjgz R5z3Aj6Zo9iwkkqhnep9T7cN2hyLhoByQ0hMrO4I1piIZN/yG4CnzPpXCx2CeFZzvDpeZxdrVhI CYHtLVQKh83mz2NYAWpwD9YZr+hJ/hXXn17sKMoAhE5Uc8yimPlvRsxgXxeKrmTsMDSYudTg== X-Google-Smtp-Source: AGHT+IGjCOd+4ejNkIaM3IgSSrfNJ+dmBJ/8y2etg+UINkDzARyyHRj4mxQVKfiW2P/glN4METLcKw== X-Received: by 2002:a17:902:e88c:b0:297:d697:41e with SMTP id d9443c01a7336-2984edaab98mr5869605ad.37.1762889205543; Tue, 11 Nov 2025 11:26:45 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2a00:79e0:2e7c:8:ba9f:d4c6:9323:4864]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2984dcd0974sm4861075ad.90.2025.11.11.11.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 11:26:43 -0800 (PST) From: Douglas Anderson To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus Cc: linux-samsung-soc@vger.kernel.org, Roy Luo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Julius Werner , William McVicker , Douglas Anderson , Alexandre Belloni , Arnd Bergmann , Catalin Marinas , Drew Fustini , Krzysztof Kozlowski , Linus Walleij , Will Deacon , linux-kernel@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 3/4] arm64: dts: google: Add dts directory for Google-designed silicon Date: Tue, 11 Nov 2025 11:22:06 -0800 Message-ID: <20251111112158.3.I35b9e835ac49ab408e5ca3e0983930a1f1395814@changeid> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog In-Reply-To: <20251111192422.4180216-1-dianders@chromium.org> References: <20251111192422.4180216-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The first four Google Tensor SoCs were offshoots of Samsung Exynos SoCs and their device trees were organized under the "exynos/google" directory. Starting with the Google Tensor G5 SoC in Pixel 10 phones, Google Tensor SoCs are now of Google's own design. Add a location in the tree to store these device tree files. Signed-off-by: Douglas Anderson Reviewed-by: Peter Griffin --- MAINTAINERS | 1 + arch/arm64/Kconfig.platforms | 6 ++++++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 1 + 4 files changed, 9 insertions(+) create mode 100644 arch/arm64/boot/dts/google/Makefile diff --git a/MAINTAINERS b/MAINTAINERS index ddecf1ef3bed..f73a247ec61c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10606,6 +10606,7 @@ C: irc://irc.oftc.net/pixel6-kernel-dev F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: arch/arm64/boot/dts/exynos/google/ +F: arch/arm64/boot/dts/google/ F: drivers/clk/samsung/clk-gs101.c F: drivers/phy/samsung/phy-gs101-ufs.c F: include/dt-bindings/clock/google,gs101.h diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 13173795c43d..044af9a3b45f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -138,6 +138,12 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. =20 +config ARCH_GOOGLE + bool "Google-Designed SoC family" + help + This enables support for Google Tensor chips starting at the + Google Tensor G5. + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select SOC_TI diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index b0844404eda1..b4b5023d61d2 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -17,6 +17,7 @@ subdir-y +=3D cavium subdir-y +=3D cix subdir-y +=3D exynos subdir-y +=3D freescale +subdir-y +=3D google subdir-y +=3D hisilicon subdir-y +=3D intel subdir-y +=3D lg diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/goog= le/Makefile new file mode 100644 index 000000000000..a6b187e2d631 --- /dev/null +++ b/arch/arm64/boot/dts/google/Makefile @@ -0,0 +1 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Sat Feb 7 19:45:33 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 265FD328B40 for ; Tue, 11 Nov 2025 19:26:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889211; cv=none; b=IsxY4sYIfBct76c8+FvLIwWEBZdCb/mvCnA3y2g4dAzikYzuZGeZXmln8byQ+EZ53ANOvKZzbVxg+R0cZIWRkNa6z8lhvou4ev1ry9fz67BWPe/6tdUgeqbZixB+A3jV7IojunCx6fV4OViUp7Pca3iNl2Z+eHv8gkeStAYZF6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762889211; c=relaxed/simple; bh=4BWqdjAI1FgYLlZRElop3889oLKIxBOOQmVA7HAKui8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PHqYs9fQ2JBozkpZgHFW98BYJ0uz0kqypyfArx+7AIhkOTBbhVa5o0ri27kIMbi1m8xt48tZJF8cepSkNGyNYg69zIFzYf39GWWO47oSTzaj/jyHjPcDU1BbAGBvbCdc+tJlKMbGhtDxSNq9x99JbLAJ+QhKiqoJtVWGomS9h7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=ZV0ndG3Q; arc=none smtp.client-ip=209.85.215.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="ZV0ndG3Q" Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-bbf2c3eccc9so545a12.0 for ; Tue, 11 Nov 2025 11:26:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1762889207; x=1763494007; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sXztKRQeQ42Nxjbxh6sXcYxL5dCWBbnOGAFFc70tEEc=; b=ZV0ndG3QSxczIaODK6znKqK974O2fdCxRLO2KhjU7zAgHpCgPmrqbTCkhOb7stHw1i DupOXRIqvhJMlDU744Og+VV5va5jqIh+zK+mHOroEGbtQfE6fL7/KyVSxsWjneu8f4ZL rpQxlcMKP15wku3LO1/G6vG4Vf3BR/EaXb/u8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762889207; x=1763494007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sXztKRQeQ42Nxjbxh6sXcYxL5dCWBbnOGAFFc70tEEc=; b=azzBmJ7WJHYX3m5g8bxfivXEqECwd5RTKnZ+QXuKsJ8RiLbVljsnuoxZoAYOY36sET CtU+sGi9xdSCJqecyoQiQj27n97XiCyWNJ3h2Me8JcAObKPBWk6LR19MbgvYkCHOD4yN fZr+PtrnjmXUvy77g8MB4EZYiGJlRmlEPP9YhTStP4iNa1XecvKMju6UedQh3k1+hy56 +tvbUhutm4CK3mnVeBSeH6GYqbVeeSJ1KETRyEaJnY6zKzoQ/wP9C9jT4qLCwgLL6mob RIgBJwbMgTqPY3gb0xAbMzmnRkQc+K9fosa+q3LgII9Cc7ZTJ3Y4ekduertSNV9cJ5k6 sWFA== X-Forwarded-Encrypted: i=1; AJvYcCXNQDMp1JVld8Ndi6D+2lfdHNUDF2a+qvuxsSczHQvxsItJkQz+aZ2Qo6aH4mIpSaNxqDy/Uehg3BVvktM=@vger.kernel.org X-Gm-Message-State: AOJu0Yz1o3sNbrqHf+3j6GSYzEyg/dRjAQUh/O8A4q3b/F0cCik5aIyK c9OLj4NzPoTyCMIey/HTX6Khurrvfe21NdPA7avxo8dNPdYNQWaUKzwdPrKsiQPMWQ== X-Gm-Gg: ASbGncs8rwLdmAJ/VOa45QmGuVpRe0XHMle4J3AYLc9UP1usGPIciKX/XWJ5gUpadod CkhNOgFHmuhqtDROZaDM6mwryXgzmSDCkJjvzX7LCx34uSaxASv2NoWG87lo07ejTTzvBEvGs9a rPLp9NXlcxqmi7yfjJszKE97rOSglCMet3NwCQWZW4cQz0vOO2/gn96oHBmmSvmXVkXcWLx6kx1 WNJGOcM1pb6jUaA2lulJs88YSLQxaFlIYICTcVEVMpptNDZ7JfShxkoEXnA5H3sKuyHh6guWHhc YS8iZV8VDF3Yz176tRToAdbtFSQ9s5yxdo5yYN3diKBneiox345/sDxJesu6+11ZcSpvLv8J6tz /B1fBVsuH7mCfQQ/XfpV3gtl9w3gdInFOc/Z1tr6MC68ZI/a4ay7PyrQMk4nZfYHymmY7zNXns9 Zz2fplyEbv8FikcgfVSDf+dzHfd0RRQmGramx3wwaRZf9ld6oTHq8GFJ590xwipRn4C7ZNzg== X-Google-Smtp-Source: AGHT+IF7ICFayTE0+EUDrZlIuO1hDzNuYdngnxM/yVhdMG/Nhpl1saN3IvjKQwNtaS6arb3eRGydPA== X-Received: by 2002:a17:902:cf05:b0:297:e6ca:c053 with SMTP id d9443c01a7336-29840b4a6c1mr53188555ad.28.1762889207422; Tue, 11 Nov 2025 11:26:47 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2a00:79e0:2e7c:8:ba9f:d4c6:9323:4864]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2984dcd0974sm4861075ad.90.2025.11.11.11.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 11:26:46 -0800 (PST) From: Douglas Anderson To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus Cc: linux-samsung-soc@vger.kernel.org, Roy Luo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Julius Werner , William McVicker , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: google: Add initial dts for frankel, blazer, and mustang Date: Tue, 11 Nov 2025 11:22:07 -0800 Message-ID: <20251111112158.4.I5032910018cdd7d6be7aea78870d04c0dc381d6e@changeid> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog In-Reply-To: <20251111192422.4180216-1-dianders@chromium.org> References: <20251111192422.4180216-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add barebones device trees for frankel (Pixel 10), blazer (Pixel 10 Pro), and mustang (Pixel 10 Pro XL). These device trees are enough to boot to a serial prompt using an initramfs. Many things can be noted about these device trees: 1. They are organized as "dts" files for the main SoC and "dtso" overlays for the boards. There is discussion about this in the bindings patch ("dt-bindings: arm: google: Add bindings for frankel/blazer/mustang"). 2. They won't boot with the currently shipping bootloader. The current bootloader hardcodes several paths to nodes that it wants to update and considers it a fatal error if it can't find these nodes. Interested parties will need to wait for fixes to land and a new bootloader to be rolled out before attempting to use these. 3. They only add one revision (MP1) of each of frankel, blazer, and mustang. With this simple barebones device tree, there doesn't appear to be any difference between the revisions. More revisions will be added as needed in the future. The heuristics in the bootloader will pick the MP1 device tree if there are not any better matches. 4. They only add the dts for the B0 SoC for now. The A0 SoC support can be added later if we find the need. 5. Even newer versions of the bootloader will still error out if they don't find a UFS node to add calibration data to. Until UFS is supported, we provide a bogus UFS node for the bootloader. While the bootloader could be changed, there is no long-term benefit since eventually the device tree will have a UFS node. 6. They purposely choose to use the full 64-bit address and size cells for the root node and the `soc@0` node. Although I haven't tested the need for this, I presume the arguments made in commit bede7d2dc8f3 ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") would apply here. 7. Though it looks as if the UART is never enabled, the bootloader knows to enable the UART when the console is turned on. Baud rate is configurable in the bootloader so is never hardcoded in the device tree. Signed-off-by: Douglas Anderson --- To avoid fragmenting the discussion, IMO: * Let's have the discussion about using the "dts" for SoC and the "dtso" for the boards in response to the bindings (patch #1). * If we want to have a discussion about putting "board-id" and "model-id" at the root of the board overlays, we can have it here. I'll preemptively note that the "board-id" and "model-id" won't show up in the final combined device tree and they are just used by the tool (mkdtimg). We could change mkdtimg to parse the "compatible" strings of the overlays files (since I've put the IDs there too), but official the docs [1] seem to indicate that top-level properties like this are OK. In order for these device trees to pass validation without warnings, it's assumed you have my dtc patches: * https://lore.kernel.org/r/20251110204529.2838248-1-dianders@chromium.org * https://lore.kernel.org/r/20251110204529.2838248-2-dianders@chromium.org [1] https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/Documentation/dt-= object-internal.txt?h=3Dmain arch/arm64/boot/dts/google/Makefile | 9 + arch/arm64/boot/dts/google/lga-b0.dts | 391 ++++++++++++++++++ .../arm64/boot/dts/google/lga-blazer-mp1.dtso | 22 + .../boot/dts/google/lga-frankel-mp1.dtso | 22 + .../boot/dts/google/lga-mustang-mp1.dtso | 22 + .../boot/dts/google/lga-muzel-common.dtsi | 17 + 6 files changed, 483 insertions(+) create mode 100644 arch/arm64/boot/dts/google/lga-b0.dts create mode 100644 arch/arm64/boot/dts/google/lga-blazer-mp1.dtso create mode 100644 arch/arm64/boot/dts/google/lga-frankel-mp1.dtso create mode 100644 arch/arm64/boot/dts/google/lga-mustang-mp1.dtso create mode 100644 arch/arm64/boot/dts/google/lga-muzel-common.dtsi diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/goog= le/Makefile index a6b187e2d631..276001e91632 100644 --- a/arch/arm64/boot/dts/google/Makefile +++ b/arch/arm64/boot/dts/google/Makefile @@ -1 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + +dtb-$(CONFIG_ARCH_GOOGLE) +=3D \ + lga-blazer-mp1.dtb \ + lga-frankel-mp1.dtb \ + lga-mustang-mp1.dtb + +lga-blazer-mp1-dtbs :=3D lga-b0.dtb lga-blazer-mp1.dtbo +lga-frankel-mp1-dtbs :=3D lga-b0.dtb lga-frankel-mp1.dtbo +lga-mustang-mp1-dtbs :=3D lga-b0.dtb lga-mustang-mp1.dtbo diff --git a/arch/arm64/boot/dts/google/lga-b0.dts b/arch/arm64/boot/dts/go= ogle/lga-b0.dts new file mode 100644 index 000000000000..83c2db4f20ef --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-b0.dts @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Tensor G5 (laguna) SoC rev B0 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; + +#include +#include + +/ { + model =3D "Google Tensor G5 rev B0"; + compatible =3D "google,soc-id-0005-rev-10", "google,lga"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + memory: memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x00000000 0x80000000 0x00000000 0x00000000>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hayes_0: cpu@0 { + compatible =3D "arm,cortex-a520"; + reg =3D <0x000>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd0>; + }; + + hayes_1: cpu@100 { + compatible =3D "arm,cortex-a520"; + reg =3D <0x100>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd1>; + }; + + hunter_0: cpu@200 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x200>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd2>; + }; + + hunter_1: cpu@300 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x300>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd3>; + }; + + hunter_2: cpu@400 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x400>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd4>; + }; + + hunter_3: cpu@500 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x500>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd5>; + }; + + hunter_4: cpu@600 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x600>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd6>; + }; + + hunterelp_0: cpu@700 { + compatible =3D "arm,cortex-x4"; + reg =3D <0x700>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <1024>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd7>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&hayes_0>; + }; + core1 { + cpu =3D <&hayes_1>; + }; + core2 { + cpu =3D <&hunter_0>; + }; + core3 { + cpu =3D <&hunter_1>; + }; + core4 { + cpu =3D <&hunter_2>; + }; + core5 { + cpu =3D <&hunter_3>; + }; + core6 { + cpu =3D <&hunter_4>; + }; + core7 { + cpu =3D <&hunterelp_0>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_lit_c2: cpu-lit-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <132>; + exit-latency-us =3D <296>; + min-residency-us =3D <3610>; + + idle-state-name =3D "cpu-lit-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid1_c2: cpu-mid1-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid1-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid2_c2: cpu-mid2-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid2-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_big_c2: cpu-big-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <110>; + exit-latency-us =3D <413>; + min-residency-us =3D <3950>; + + idle-state-name =3D "cpu-big-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + }; + + domain-idle-states { + cluster_1_c3: cluster-1-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <325>; + exit-latency-us =3D <553>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-1-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_2_c3: cluster-2-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <345>; + exit-latency-us =3D <673>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-2-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_c4_deep: cluster-c4-deep { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <510>; + exit-latency-us =3D <1027>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-c4-deep"; + + arm,psci-suspend-param =3D <0x40020333>; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_big_c2>; + power-domains =3D <&cpucl2>; + }; + + cpucl1: power-domain-cluster-1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_1_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpucl2: power-domain-cluster-2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_2_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_top_cl: power-domain-top-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_c4_deep>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D + , + , + , + ; + }; + + /* + * The Pixel bootloader considers it a fatal error if it doesn't find + * a `ufs0` alias so it can add calibration data to the node. Until + * the proper UFS controller node is added under the SoC, create a + * temporary node to make the bootloader happy. + */ + ufs: ufs-placeholder { + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + + dma-ranges =3D <0 0 0 0 0x10 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@5880000 { /* TODO ask for CPU IPC CSR */ + compatible =3D "arm,gic-v3"; + reg =3D <0 0x05880000 0 0x00010000>, + <0 0x05900000 0 0x00200000>; + ranges; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + #interrupt-cells =3D <4>; + interrupt-controller; + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&hayes_0 &hayes_1 + &hunter_0 &hunter_1 &hunter_2 + &hunter_3 &hunter_4>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&hunterelp_0>; + }; + }; + }; + + lsion_cli16_uart: serial@db62000 { + compatible =3D "google,lga-uart", "snps,dw-apb-uart"; + reg =3D <0 0x0db62000 0 0x100>; + + clock-frequency =3D <200000000>; + interrupts =3D ; + reg-io-width =3D <4>; + reg-shift =3D <2>; + + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/lga-blazer-mp1.dtso b/arch/arm64/bo= ot/dts/google/lga-blazer-mp1.dtso new file mode 100644 index 000000000000..1c0248b931e8 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-blazer-mp1.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 Pro (blazer) MP 1 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; +/plugin/; + +#include "lga-muzel-common.dtsi" + +/ { + board-id =3D <0x070406>; + board-rev =3D <0x010000>; +}; + +&{/} { + model =3D "BLAZER MP 1 based on LGA"; + compatible =3D "google,pixel-id-070406-rev-010000", + "google,lga-blazer", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-frankel-mp1.dtso b/arch/arm64/b= oot/dts/google/lga-frankel-mp1.dtso new file mode 100644 index 000000000000..133494de7a9b --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-frankel-mp1.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 (frankel) MP 1 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; +/plugin/; + +#include "lga-muzel-common.dtsi" + +/ { + board-id =3D <0x070306>; + board-rev =3D <0x010000>; +}; + +&{/} { + model =3D "FRANKEL MP 1 based on LGA"; + compatible =3D "google,pixel-id-070306-rev-010000", + "google,lga-frankel", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-mustang-mp1.dtso b/arch/arm64/b= oot/dts/google/lga-mustang-mp1.dtso new file mode 100644 index 000000000000..1f79bbe48056 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-mustang-mp1.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 Pro XL (mustang) MP 1 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; +/plugin/; + +#include "lga-muzel-common.dtsi" + +/ { + board-id =3D <0x070506>; + board-rev =3D <0x010000>; +}; + +&{/} { + model =3D "MUSTANG MP 1 based on LGA"; + compatible =3D "google,pixel-id-070506-rev-010000", + "google,lga-mustang", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-muzel-common.dtsi b/arch/arm64/= boot/dts/google/lga-muzel-common.dtsi new file mode 100644 index 000000000000..3505f02f5b36 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-muzel-common.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 family (mustang + blazer + frankel =3D muzel) common dt= si. + * + * Copyright 2024-2025 Google LLC. + */ + +&{/} { + chosen { + stdout-path =3D "serial0"; + }; + + aliases { + serial0 =3D "/soc@0/serial@db62000"; /* &lsion_cli16_uart */ + ufs0 =3D "/ufs-placeholder"; /* &ufs - TODO "/soc@0/ufs@3c400000" */ + }; +}; --=20 2.51.2.1041.gc1ab5b90ca-goog