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Tue, 11 Nov 2025 11:26:47 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2a00:79e0:2e7c:8:ba9f:d4c6:9323:4864]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2984dcd0974sm4861075ad.90.2025.11.11.11.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 11:26:46 -0800 (PST) From: Douglas Anderson To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus Cc: linux-samsung-soc@vger.kernel.org, Roy Luo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Julius Werner , William McVicker , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: google: Add initial dts for frankel, blazer, and mustang Date: Tue, 11 Nov 2025 11:22:07 -0800 Message-ID: <20251111112158.4.I5032910018cdd7d6be7aea78870d04c0dc381d6e@changeid> X-Mailer: git-send-email 2.51.2.1041.gc1ab5b90ca-goog In-Reply-To: <20251111192422.4180216-1-dianders@chromium.org> References: <20251111192422.4180216-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add barebones device trees for frankel (Pixel 10), blazer (Pixel 10 Pro), and mustang (Pixel 10 Pro XL). These device trees are enough to boot to a serial prompt using an initramfs. Many things can be noted about these device trees: 1. They are organized as "dts" files for the main SoC and "dtso" overlays for the boards. There is discussion about this in the bindings patch ("dt-bindings: arm: google: Add bindings for frankel/blazer/mustang"). 2. They won't boot with the currently shipping bootloader. The current bootloader hardcodes several paths to nodes that it wants to update and considers it a fatal error if it can't find these nodes. Interested parties will need to wait for fixes to land and a new bootloader to be rolled out before attempting to use these. 3. They only add one revision (MP1) of each of frankel, blazer, and mustang. With this simple barebones device tree, there doesn't appear to be any difference between the revisions. More revisions will be added as needed in the future. The heuristics in the bootloader will pick the MP1 device tree if there are not any better matches. 4. They only add the dts for the B0 SoC for now. The A0 SoC support can be added later if we find the need. 5. Even newer versions of the bootloader will still error out if they don't find a UFS node to add calibration data to. Until UFS is supported, we provide a bogus UFS node for the bootloader. While the bootloader could be changed, there is no long-term benefit since eventually the device tree will have a UFS node. 6. They purposely choose to use the full 64-bit address and size cells for the root node and the `soc@0` node. Although I haven't tested the need for this, I presume the arguments made in commit bede7d2dc8f3 ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") would apply here. 7. Though it looks as if the UART is never enabled, the bootloader knows to enable the UART when the console is turned on. Baud rate is configurable in the bootloader so is never hardcoded in the device tree. Signed-off-by: Douglas Anderson --- To avoid fragmenting the discussion, IMO: * Let's have the discussion about using the "dts" for SoC and the "dtso" for the boards in response to the bindings (patch #1). * If we want to have a discussion about putting "board-id" and "model-id" at the root of the board overlays, we can have it here. I'll preemptively note that the "board-id" and "model-id" won't show up in the final combined device tree and they are just used by the tool (mkdtimg). We could change mkdtimg to parse the "compatible" strings of the overlays files (since I've put the IDs there too), but official the docs [1] seem to indicate that top-level properties like this are OK. In order for these device trees to pass validation without warnings, it's assumed you have my dtc patches: * https://lore.kernel.org/r/20251110204529.2838248-1-dianders@chromium.org * https://lore.kernel.org/r/20251110204529.2838248-2-dianders@chromium.org [1] https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/Documentation/dt-= object-internal.txt?h=3Dmain arch/arm64/boot/dts/google/Makefile | 9 + arch/arm64/boot/dts/google/lga-b0.dts | 391 ++++++++++++++++++ .../arm64/boot/dts/google/lga-blazer-mp1.dtso | 22 + .../boot/dts/google/lga-frankel-mp1.dtso | 22 + .../boot/dts/google/lga-mustang-mp1.dtso | 22 + .../boot/dts/google/lga-muzel-common.dtsi | 17 + 6 files changed, 483 insertions(+) create mode 100644 arch/arm64/boot/dts/google/lga-b0.dts create mode 100644 arch/arm64/boot/dts/google/lga-blazer-mp1.dtso create mode 100644 arch/arm64/boot/dts/google/lga-frankel-mp1.dtso create mode 100644 arch/arm64/boot/dts/google/lga-mustang-mp1.dtso create mode 100644 arch/arm64/boot/dts/google/lga-muzel-common.dtsi diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/goog= le/Makefile index a6b187e2d631..276001e91632 100644 --- a/arch/arm64/boot/dts/google/Makefile +++ b/arch/arm64/boot/dts/google/Makefile @@ -1 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + +dtb-$(CONFIG_ARCH_GOOGLE) +=3D \ + lga-blazer-mp1.dtb \ + lga-frankel-mp1.dtb \ + lga-mustang-mp1.dtb + +lga-blazer-mp1-dtbs :=3D lga-b0.dtb lga-blazer-mp1.dtbo +lga-frankel-mp1-dtbs :=3D lga-b0.dtb lga-frankel-mp1.dtbo +lga-mustang-mp1-dtbs :=3D lga-b0.dtb lga-mustang-mp1.dtbo diff --git a/arch/arm64/boot/dts/google/lga-b0.dts b/arch/arm64/boot/dts/go= ogle/lga-b0.dts new file mode 100644 index 000000000000..83c2db4f20ef --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-b0.dts @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Tensor G5 (laguna) SoC rev B0 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; + +#include +#include + +/ { + model =3D "Google Tensor G5 rev B0"; + compatible =3D "google,soc-id-0005-rev-10", "google,lga"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + memory: memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x00000000 0x80000000 0x00000000 0x00000000>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hayes_0: cpu@0 { + compatible =3D "arm,cortex-a520"; + reg =3D <0x000>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd0>; + }; + + hayes_1: cpu@100 { + compatible =3D "arm,cortex-a520"; + reg =3D <0x100>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd1>; + }; + + hunter_0: cpu@200 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x200>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd2>; + }; + + hunter_1: cpu@300 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x300>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd3>; + }; + + hunter_2: cpu@400 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x400>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd4>; + }; + + hunter_3: cpu@500 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x500>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd5>; + }; + + hunter_4: cpu@600 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x600>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd6>; + }; + + hunterelp_0: cpu@700 { + compatible =3D "arm,cortex-x4"; + reg =3D <0x700>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <1024>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd7>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&hayes_0>; + }; + core1 { + cpu =3D <&hayes_1>; + }; + core2 { + cpu =3D <&hunter_0>; + }; + core3 { + cpu =3D <&hunter_1>; + }; + core4 { + cpu =3D <&hunter_2>; + }; + core5 { + cpu =3D <&hunter_3>; + }; + core6 { + cpu =3D <&hunter_4>; + }; + core7 { + cpu =3D <&hunterelp_0>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_lit_c2: cpu-lit-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <132>; + exit-latency-us =3D <296>; + min-residency-us =3D <3610>; + + idle-state-name =3D "cpu-lit-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid1_c2: cpu-mid1-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid1-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid2_c2: cpu-mid2-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid2-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_big_c2: cpu-big-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <110>; + exit-latency-us =3D <413>; + min-residency-us =3D <3950>; + + idle-state-name =3D "cpu-big-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + }; + + domain-idle-states { + cluster_1_c3: cluster-1-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <325>; + exit-latency-us =3D <553>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-1-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_2_c3: cluster-2-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <345>; + exit-latency-us =3D <673>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-2-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_c4_deep: cluster-c4-deep { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <510>; + exit-latency-us =3D <1027>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-c4-deep"; + + arm,psci-suspend-param =3D <0x40020333>; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_big_c2>; + power-domains =3D <&cpucl2>; + }; + + cpucl1: power-domain-cluster-1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_1_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpucl2: power-domain-cluster-2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_2_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_top_cl: power-domain-top-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_c4_deep>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D + , + , + , + ; + }; + + /* + * The Pixel bootloader considers it a fatal error if it doesn't find + * a `ufs0` alias so it can add calibration data to the node. Until + * the proper UFS controller node is added under the SoC, create a + * temporary node to make the bootloader happy. + */ + ufs: ufs-placeholder { + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + + dma-ranges =3D <0 0 0 0 0x10 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@5880000 { /* TODO ask for CPU IPC CSR */ + compatible =3D "arm,gic-v3"; + reg =3D <0 0x05880000 0 0x00010000>, + <0 0x05900000 0 0x00200000>; + ranges; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + #interrupt-cells =3D <4>; + interrupt-controller; + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&hayes_0 &hayes_1 + &hunter_0 &hunter_1 &hunter_2 + &hunter_3 &hunter_4>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&hunterelp_0>; + }; + }; + }; + + lsion_cli16_uart: serial@db62000 { + compatible =3D "google,lga-uart", "snps,dw-apb-uart"; + reg =3D <0 0x0db62000 0 0x100>; + + clock-frequency =3D <200000000>; + interrupts =3D ; + reg-io-width =3D <4>; + reg-shift =3D <2>; + + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/lga-blazer-mp1.dtso b/arch/arm64/bo= ot/dts/google/lga-blazer-mp1.dtso new file mode 100644 index 000000000000..1c0248b931e8 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-blazer-mp1.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 Pro (blazer) MP 1 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; +/plugin/; + +#include "lga-muzel-common.dtsi" + +/ { + board-id =3D <0x070406>; + board-rev =3D <0x010000>; +}; + +&{/} { + model =3D "BLAZER MP 1 based on LGA"; + compatible =3D "google,pixel-id-070406-rev-010000", + "google,lga-blazer", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-frankel-mp1.dtso b/arch/arm64/b= oot/dts/google/lga-frankel-mp1.dtso new file mode 100644 index 000000000000..133494de7a9b --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-frankel-mp1.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 (frankel) MP 1 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; +/plugin/; + +#include "lga-muzel-common.dtsi" + +/ { + board-id =3D <0x070306>; + board-rev =3D <0x010000>; +}; + +&{/} { + model =3D "FRANKEL MP 1 based on LGA"; + compatible =3D "google,pixel-id-070306-rev-010000", + "google,lga-frankel", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-mustang-mp1.dtso b/arch/arm64/b= oot/dts/google/lga-mustang-mp1.dtso new file mode 100644 index 000000000000..1f79bbe48056 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-mustang-mp1.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 Pro XL (mustang) MP 1 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; +/plugin/; + +#include "lga-muzel-common.dtsi" + +/ { + board-id =3D <0x070506>; + board-rev =3D <0x010000>; +}; + +&{/} { + model =3D "MUSTANG MP 1 based on LGA"; + compatible =3D "google,pixel-id-070506-rev-010000", + "google,lga-mustang", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-muzel-common.dtsi b/arch/arm64/= boot/dts/google/lga-muzel-common.dtsi new file mode 100644 index 000000000000..3505f02f5b36 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-muzel-common.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 family (mustang + blazer + frankel =3D muzel) common dt= si. + * + * Copyright 2024-2025 Google LLC. + */ + +&{/} { + chosen { + stdout-path =3D "serial0"; + }; + + aliases { + serial0 =3D "/soc@0/serial@db62000"; /* &lsion_cli16_uart */ + ufs0 =3D "/ufs-placeholder"; /* &ufs - TODO "/soc@0/ufs@3c400000" */ + }; +}; --=20 2.51.2.1041.gc1ab5b90ca-goog