From nobody Sat Feb 7 23:10:59 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF2A4351FBE; Tue, 11 Nov 2025 10:53:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762858403; cv=none; b=Gzrk7egagr08pEeLfQrkCSHJRTMY9/ZffEYhxryjVI6jdLpC0NoG1EUETanEs2ouOck7qOvp9WCya96ANNpjgylYfKmi8kD0RzqcjCkmq4MsFWtondFeqP2CpBOS2aQQ1jhfeKWKaamQ8xmQdJg5VyRG8yqYhy2ASnp54EmI7TA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762858403; c=relaxed/simple; bh=g7mlGe76mNaw/xOZJ6E1PI1pNY6kIC2FIUf9CvUkl0o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZlWwZ0gXVDfruaANJjxheEBJaL6GAktbPoDVI6qwU94G9/5yaAHd7aN++6cGdytHCkYzDZjh866OTdP5SLgNjQWTBqI+I5UJqMrBaBC43DlblEFSCnaX7jd0NE1rwKe/n9BB4ZreQQa8vxPHauNu2RPhnRYp8XSR/aGPw/+GXmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=jcSQBGKm; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="jcSQBGKm" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 659B822D94; Tue, 11 Nov 2025 11:53:20 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id o9Ovi-Y2y_qQ; Tue, 11 Nov 2025 11:53:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1762858399; bh=g7mlGe76mNaw/xOZJ6E1PI1pNY6kIC2FIUf9CvUkl0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jcSQBGKm/vAejL7+xus1TLVJO5Z2xoqsf80rqZbeh5HEiKnzTBGt45aBZcfa//8Ca uMn/2KJ0i6BLizTda3xFqn9k3lWN+dCLiT41mKNXfTZGEMFkAgXcz6AhP/dNDtZNzw YyG3QzivOllF/vG4CGlL/B1esq2Cp5Jr8S3mykX0J+165FDx0caY0tUpJG+qA1x4TU YdSQlgQ9lMbRmNdyug/qN8EAkmX2GdG2uuvVr9JZcIzSHKq5KJ6r6GuqsYIdUSXuV9 0KMD/AFwHoPOaNGB9s9eUFBvrY/K482OuLeH5ty5qJz8bbWoPHXgpSuxlPSSGT6RJ1 xgqlBBBaHgELw== From: Yao Zi To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yao Zi , Frank , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Vladimir Oltean , Choong Yong Liang , Chen-Yu Tsai , Jisheng Zhang , Furong Xu <0x1207@gmail.com> Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v2 1/3] net: phy: motorcomm: Support YT8531S PHY in YT6801 Ethernet controller Date: Tue, 11 Nov 2025 10:52:50 +0000 Message-ID: <20251111105252.53487-2-ziyao@disroot.org> In-Reply-To: <20251111105252.53487-1-ziyao@disroot.org> References: <20251111105252.53487-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" YT6801's internal PHY is confirmed as a GMII-capable variant of YT8531S by a previous series[1] and reading PHY ID. Add support for PHY_INTERFACE_MODE_GMII for YT8531S to allow the Ethernet driver to reuse the PHY code for its internal PHY. Link: https://lore.kernel.org/all/a48d76ac-db08-46d5-9528-f046a7b541dc@moto= r-comm.com/ # [1] Co-developed-by: Frank Sae Signed-off-by: Frank Sae Signed-off-by: Yao Zi --- drivers/net/phy/motorcomm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 89b5b19a9bd2..b751fbc6711a 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -910,6 +910,10 @@ static int ytphy_rgmii_clk_delay_config(struct phy_dev= ice *phydev) val |=3D FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); break; + case PHY_INTERFACE_MODE_GMII: + if (phydev->drv->phy_id !=3D PHY_ID_YT8531S) + return -EOPNOTSUPP; + break; default: /* do not support other modes */ return -EOPNOTSUPP; } --=20 2.51.2 From nobody Sat Feb 7 23:10:59 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F9F351FA1; Tue, 11 Nov 2025 10:53:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762858413; cv=none; b=ae36FbivFKbYe8jmwf+69NpeRJZRO+zqmPZTXVikZAdl2wWBbT6oN2KZvEhX+Y7IMa8n1v6S57a+XMXZ+hP2dpSEgO1SeOo/K7tmipsrfY6UVdFgLLC/iox7JGfEta2MwfhZp+5JvoX3FJBJnsyGX4K10fqLPtK0OFB6/DxFm8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762858413; c=relaxed/simple; bh=TMzMZE3uOgl5RtWp0EFxAqO4Id8gKXK/+q/UIwtupIg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kfHWDmQmd5ZgZMyKd9pjzAIXicZjsL77i+5gafx/FO3Dw3GtzEXwXtttTi2aUp3s/Yh9HrwcXfK8cp7XehWAyIXyDn2wn1GXZKt33usyuWvJjQ31FIs1FEc4yHaNuDZu9glLRiJtbd4LOzSpr/X9kZSy6buEsIHeS4Rr/CQtvmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=RZOKaehB; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="RZOKaehB" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id ACC62260C9; Tue, 11 Nov 2025 11:53:29 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id Pi9l2WlWpC_v; Tue, 11 Nov 2025 11:53:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1762858408; bh=TMzMZE3uOgl5RtWp0EFxAqO4Id8gKXK/+q/UIwtupIg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RZOKaehBoHb+dZFBudvLKDpqgXnzVfqB7yLrHnLvpAp9wYfEc1g+mdWxq51s14O/H MXBUn7q6KWFLRpzzlPYtjJKJYz4ThGrIO0mdiY6JjAIc2iGUGo6KWEfKoRAaoPekbz iEMynmAxi1FQnOs7o/YfuqvMcpXsNzdFRvc10wU0aQVVbHn5e10GSC/h9kIbPug39i BVTgHjiJksmhIa75/se6Dq+13/+uEWBDfBa+QIn4OtwfocpWY2HWgTmvICUWLGgATj wC+sRWJ3i+oy2MvHR2zBERWyHlKrg+5DSaEnkvgTro5w6sL9bXYpJuhYmh/zQvWzRe 8E99emR3L3IZw== From: Yao Zi To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yao Zi , Frank , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Vladimir Oltean , Choong Yong Liang , Chen-Yu Tsai , Jisheng Zhang , Furong Xu <0x1207@gmail.com> Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Mingcong Bai , Runhua He , Xi Ruoyao Subject: [PATCH net-next v2 2/3] net: stmmac: Add glue driver for Motorcomm YT6801 ethernet controller Date: Tue, 11 Nov 2025 10:52:51 +0000 Message-ID: <20251111105252.53487-3-ziyao@disroot.org> In-Reply-To: <20251111105252.53487-1-ziyao@disroot.org> References: <20251111105252.53487-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Motorcomm YT6801 is a PCIe ethernet controller based on DWMAC4 IP. It integrates an GbE phy, supporting WOL, VLAN tagging and various types of offloading. It ships an on-chip eFuse for storing various vendor configuration, including MAC address. This patch adds basic glue code for the controller, allowing it to be set up and transmit data at a reasonable speed. Features like WOL could be implemented in the future. Signed-off-by: Yao Zi Tested-by: Mingcong Bai Tested-by: Runhua He Tested-by: Xi Ruoyao --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 7 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-motorcomm.c | 379 ++++++++++++++++++ 3 files changed, 387 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 00df980fd4e0..e6b5c7ebc434 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -378,6 +378,13 @@ config DWMAC_LOONGSON This selects the LOONGSON PCI bus support for the stmmac driver, Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bri= dge. =20 +config DWMAC_MOTORCOMM + tristate "Motorcomm PCI DWMAC support" + select MOTORCOMM_PHY + help + This enables glue driver for Motorcomm DWMAC-based PCI Ethernet + controllers. Currently only YT6801 is supported. + config STMMAC_PCI tristate "STMMAC PCI bus support" depends on COMMON_CLK diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index 7bf528731034..c9263987ef8d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -48,4 +48,5 @@ obj-$(CONFIG_STMMAC_LIBPCI) +=3D stmmac_libpci.o obj-$(CONFIG_STMMAC_PCI) +=3D stmmac-pci.o obj-$(CONFIG_DWMAC_INTEL) +=3D dwmac-intel.o obj-$(CONFIG_DWMAC_LOONGSON) +=3D dwmac-loongson.o +obj-$(CONFIG_DWMAC_MOTORCOMM) +=3D dwmac-motorcomm.o stmmac-pci-objs:=3D stmmac_pci.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c b/driver= s/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c new file mode 100644 index 000000000000..844b742757fb --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DWMAC glue driver for Motorcomm PCI Ethernet controllers + * + * Copyright (c) 2025 Yao Zi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwmac4.h" +#include "stmmac.h" +#include "stmmac_libpci.h" + +#define DRIVER_NAME "dwmac-motorcomm" + +#define PCI_VENDOR_ID_MOTORCOMM 0x1f0a + +/* Register definition */ +#define EPHY_CTRL 0x1004 +/* Clearing this bit asserts resets for internal MDIO bus and PHY */ +#define EPHY_MDIO_PHY_RESET BIT(0) +#define OOB_WOL_CTRL 0x1010 +#define OOB_WOL_CTRL_DIS BIT(0) +#define MGMT_INT_CTRL0 0x1100 +#define MGMT_INT_CTRL0_MASK GENMASK(31, 16) +#define MGMT_INT_CTRL0_MASK_RXCH GENMASK(3, 0) +#define MGMT_INT_CTRL0_MASK_TXCH BIT(4) +#define MGMT_INT_CTRL0_MASK_MISC BIT(5) +#define INT_MODERATION 0x1108 +#define INT_MODERATION_RX GENMASK(11, 0) +#define INT_MODERATION_TX GENMASK(27, 16) +#define EFUSE_OP_CTRL_0 0x1500 +#define EFUSE_OP_MODE GENMASK(1, 0) +#define EFUSE_OP_ROW_READ 0x1 +#define EFUSE_OP_START BIT(2) +#define EFUSE_OP_ADDR GENMASK(15, 8) +#define EFUSE_OP_CTRL_1 0x1504 +#define EFUSE_OP_DONE BIT(1) +#define EFUSE_OP_RD_DATA GENMASK(31, 24) +#define SYS_RESET 0x152c +#define SYS_RESET_RESET BIT(31) +#define GMAC_OFFSET 0x2000 + +/* Constants */ +#define EFUSE_READ_TIMEOUT_US 20000 +#define EFUSE_PATCH_REGION_OFFSET 18 +#define EFUSE_PATCH_MAX_NUM 39 +#define EFUSE_ADDR_MACA0LR 0x1520 +#define EFUSE_ADDR_MACA0HR 0x1524 + +struct motorcomm_efuse_patch { + __le16 addr; + __le32 data; +} __packed; + +struct dwmac_motorcomm_priv { + void __iomem *base; + struct device *dev; +}; + +static int motorcomm_efuse_read_byte(struct dwmac_motorcomm_priv *priv, + u8 offset, u8 *byte) +{ + u32 reg; + int ret; + + writel(FIELD_PREP(EFUSE_OP_MODE, EFUSE_OP_ROW_READ) | + FIELD_PREP(EFUSE_OP_ADDR, offset) | + EFUSE_OP_START, priv->base + EFUSE_OP_CTRL_0); + + ret =3D readl_poll_timeout(priv->base + EFUSE_OP_CTRL_1, + reg, reg & EFUSE_OP_DONE, 2000, + EFUSE_READ_TIMEOUT_US); + + *byte =3D FIELD_GET(EFUSE_OP_RD_DATA, reg); + + return ret; +} + +static int motorcomm_efuse_read_patch(struct dwmac_motorcomm_priv *priv, + u8 index, + struct motorcomm_efuse_patch *patch) +{ + u8 buf[sizeof(*patch)], offset; + int i, ret; + + for (i =3D 0; i < sizeof(*patch); i++) { + offset =3D EFUSE_PATCH_REGION_OFFSET + sizeof(*patch) * index + i; + + ret =3D motorcomm_efuse_read_byte(priv, offset, &buf[i]); + if (ret) + return ret; + } + + memcpy(patch, buf, sizeof(*patch)); + + return 0; +} + +static int motorcomm_efuse_get_patch_value(struct dwmac_motorcomm_priv *pr= iv, + u16 addr, u32 *value) +{ + struct motorcomm_efuse_patch patch; + int i, ret; + + for (i =3D 0; i < EFUSE_PATCH_MAX_NUM; i++) { + ret =3D motorcomm_efuse_read_patch(priv, i, &patch); + if (ret) + return ret; + + if (patch.addr =3D=3D 0) { + return -ENOENT; + } else if (le16_to_cpu(patch.addr) =3D=3D addr) { + *value =3D le32_to_cpu(patch.data); + return 0; + } + } + + return -ENOENT; +} + +static int motorcomm_efuse_read_mac(struct dwmac_motorcomm_priv *priv, u8 = *mac) +{ + u32 maca0lr, maca0hr; + int ret; + + ret =3D motorcomm_efuse_get_patch_value(priv, EFUSE_ADDR_MACA0LR, + &maca0lr); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to read maca0lr from eFuse\n"); + + ret =3D motorcomm_efuse_get_patch_value(priv, EFUSE_ADDR_MACA0HR, + &maca0hr); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to read maca0hr from eFuse\n"); + + mac[0] =3D FIELD_GET(GENMASK(15, 8), maca0hr); + mac[1] =3D FIELD_GET(GENMASK(7, 0), maca0hr); + mac[2] =3D FIELD_GET(GENMASK(31, 24), maca0lr); + mac[3] =3D FIELD_GET(GENMASK(23, 16), maca0lr); + mac[4] =3D FIELD_GET(GENMASK(15, 8), maca0lr); + mac[5] =3D FIELD_GET(GENMASK(7, 0), maca0lr); + + return 0; +} + +static void motorcomm_deassert_mdio_phy_reset(struct dwmac_motorcomm_priv = *priv) +{ + u32 reg =3D readl(priv->base + EPHY_CTRL); + + reg |=3D EPHY_MDIO_PHY_RESET; + + writel(reg, priv->base + EPHY_CTRL); +} + +static void motorcomm_reset(struct dwmac_motorcomm_priv *priv) +{ + u32 reg =3D readl(priv->base + SYS_RESET); + + reg &=3D ~SYS_RESET_RESET; + writel(reg, priv->base + SYS_RESET); + + reg |=3D SYS_RESET_RESET; + writel(reg, priv->base + SYS_RESET); + + motorcomm_deassert_mdio_phy_reset(priv); +} + +static void motorcomm_init(struct dwmac_motorcomm_priv *priv) +{ + writel(0x0, priv->base + MGMT_INT_CTRL0); + + writel(FIELD_PREP(INT_MODERATION_RX, 200) | + FIELD_PREP(INT_MODERATION_TX, 200), + priv->base + INT_MODERATION); + + /* + * OOB WOL must be disabled during normal operation, or DMA interrupts + * cannot be delivered to the host. + */ + writel(OOB_WOL_CTRL_DIS, priv->base + OOB_WOL_CTRL); +} + +static int motorcomm_resume(struct device *dev, void *bsp_priv) +{ + struct dwmac_motorcomm_priv *priv =3D bsp_priv; + int ret; + + ret =3D stmmac_pci_plat_resume(dev, bsp_priv); + if (ret) + return ret; + + /* + * When recovering from D3hot, EPHY_MDIO_PHY_RESET is automatically + * asserted, and must be deasserted for normal operation. + */ + motorcomm_deassert_mdio_phy_reset(priv); + motorcomm_init(priv); + + return 0; +} + +static struct plat_stmmacenet_data * +motorcomm_default_plat_data(struct pci_dev *pdev) +{ + struct plat_stmmacenet_data *plat; + struct device *dev =3D &pdev->dev; + + plat =3D devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL); + if (!plat) + return NULL; + + plat->mdio_bus_data =3D devm_kzalloc(dev, sizeof(*plat->mdio_bus_data), + GFP_KERNEL); + if (!plat->mdio_bus_data) + return NULL; + + plat->dma_cfg =3D devm_kzalloc(dev, sizeof(*plat->dma_cfg), GFP_KERNEL); + if (!plat->dma_cfg) + return NULL; + + plat->axi =3D devm_kzalloc(dev, sizeof(*plat->axi), GFP_KERNEL); + if (!plat->axi) + return NULL; + + plat->dma_cfg->pbl =3D DEFAULT_DMA_PBL; + plat->dma_cfg->pblx8 =3D true; + plat->dma_cfg->txpbl =3D 32; + plat->dma_cfg->rxpbl =3D 32; + plat->dma_cfg->eame =3D true; + plat->dma_cfg->mixed_burst =3D true; + + plat->axi->axi_wr_osr_lmt =3D 1; + plat->axi->axi_rd_osr_lmt =3D 1; + plat->axi->axi_mb =3D true; + plat->axi->axi_blen[0] =3D 4; + plat->axi->axi_blen[1] =3D 8; + plat->axi->axi_blen[2] =3D 16; + plat->axi->axi_blen[3] =3D 32; + + plat->bus_id =3D pci_dev_id(pdev); + plat->phy_addr =3D -1; + plat->phy_interface =3D PHY_INTERFACE_MODE_GMII; + plat->clk_csr =3D STMMAC_CSR_20_35M; + plat->tx_coe =3D 1; + plat->rx_coe =3D 1; + plat->maxmtu =3D JUMBO_LEN; + plat->rx_queues_to_use =3D 1; + plat->tx_queues_to_use =3D 1; + plat->clk_ref_rate =3D 125000000; + plat->core_type =3D DWMAC_CORE_GMAC4; + plat->suspend =3D stmmac_pci_plat_suspend; + plat->resume =3D motorcomm_resume; + plat->flags =3D STMMAC_FLAG_TSO_EN; + + return plat; +} + +static int motorcomm_setup_irq(struct pci_dev *pdev, + struct stmmac_resources *res, + struct plat_stmmacenet_data *plat) +{ + int ret; + + ret =3D pci_alloc_irq_vectors(pdev, 6, 6, PCI_IRQ_MSIX); + if (ret > 0) { + res->rx_irq[0] =3D pci_irq_vector(pdev, 0); + res->tx_irq[0] =3D pci_irq_vector(pdev, 4); + res->irq =3D pci_irq_vector(pdev, 5); + + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + + return 0; + } + + dev_info(&pdev->dev, "failed to allocate MSI-X vector: %d\n", ret); + dev_info(&pdev->dev, "try MSI instead\n"); + + ret =3D pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "failed to allocate MSI\n"); + + res->irq =3D pci_irq_vector(pdev, 0); + + return 0; +} + +static int motorcomm_probe(struct pci_dev *pdev, const struct pci_device_i= d *id) +{ + struct plat_stmmacenet_data *plat; + struct dwmac_motorcomm_priv *priv; + struct stmmac_resources res =3D {}; + int ret; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + + plat =3D motorcomm_default_plat_data(pdev); + if (!plat) + return -ENOMEM; + + plat->bsp_priv =3D priv; + + ret =3D pcim_enable_device(pdev); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to enable device\n"); + + priv->base =3D pcim_iomap_region(pdev, 0, DRIVER_NAME); + if (IS_ERR(priv->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->base), + "failed to map IO region\n"); + + pci_set_master(pdev); + + motorcomm_reset(priv); + + ret =3D motorcomm_efuse_read_mac(priv, res.mac); + if (ret =3D=3D -ENOENT) { + dev_warn(&pdev->dev, "eFuse contains no valid MAC address\n"); + dev_warn(&pdev->dev, "fallback to random MAC address\n"); + + memset(res.mac, 0, sizeof(res.mac)); + } else if (ret) { + return dev_err_probe(&pdev->dev, ret, + "failed to read MAC address from eFuse\n"); + } + + ret =3D motorcomm_setup_irq(pdev, &res, plat); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to setup IRQ\n"); + + motorcomm_init(priv); + + res.addr =3D priv->base + GMAC_OFFSET; + + return stmmac_dvr_probe(&pdev->dev, plat, &res); +} + +static void motorcomm_remove(struct pci_dev *pdev) +{ + stmmac_dvr_remove(&pdev->dev); + pci_free_irq_vectors(pdev); +} + +static const struct pci_device_id dwmac_motorcomm_pci_id_table[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_MOTORCOMM, 0x6801) }, + { }, +}; +MODULE_DEVICE_TABLE(pci, dwmac_motorcomm_pci_id_table); + +static struct pci_driver dwmac_motorcomm_pci_driver =3D { + .name =3D DRIVER_NAME, + .id_table =3D dwmac_motorcomm_pci_id_table, + .probe =3D motorcomm_probe, + .remove =3D motorcomm_remove, + .driver =3D { + .pm =3D &stmmac_simple_pm_ops, + }, +}; + +module_pci_driver(dwmac_motorcomm_pci_driver); + +MODULE_DESCRIPTION("DWMAC glue driver for Motorcomm PCI Ethernet controlle= rs"); +MODULE_AUTHOR("Yao Zi "); +MODULE_LICENSE("GPL"); --=20 2.51.2 From nobody Sat Feb 7 23:10:59 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BEE934EF0A; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="UQdH3Awx" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 074B022D94; Tue, 11 Nov 2025 11:54:14 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id CgxASFd3aDV6; Tue, 11 Nov 2025 11:54:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1762858452; bh=fOoRk5pYJFVJNCXLLphSPxJWA9vKkuaB1E5P1bzsu2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UQdH3Awxb9j3sWRxi2VlWNN0HUTiguirE02jO69CmAnlTJdkCFqMEh66zPWo8qd46 P1asl6D2PLoghtnbii2uFgHP2kADkHpk0izoAURVCXDiLbuMhf2JUcuwPjgIBljpxo lNSGp9suTosikEb/A4vLXB7zqy8w9WqQ3kbOqcQ4hXJerom3zCql3FfNOgbOFJbL9T s2Qz0ZNN+xqip+4m7qeM3UCjNuDSE1hEEfbZpVSkCUWL3NuVKNZKevYFv65OkCDrxm 0tyPt8T1FotXWm527bZnEv94X1wcbYJif2UWcYWpsAavXfOFOPqKtUPh5StHtEmzhu ydSWPVQTPslCw== From: Yao Zi To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yao Zi , Frank , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Vladimir Oltean , Choong Yong Liang , Chen-Yu Tsai , Jisheng Zhang , Furong Xu <0x1207@gmail.com> Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v2 3/3] MAINTAINERS: Assign myself as maintainer of Motorcomm DWMAC glue driver Date: Tue, 11 Nov 2025 10:52:52 +0000 Message-ID: <20251111105252.53487-4-ziyao@disroot.org> In-Reply-To: <20251111105252.53487-1-ziyao@disroot.org> References: <20251111105252.53487-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" I volunteer to maintain the DWMAC glue driver for Motorcomm ethernet controllers. Signed-off-by: Yao Zi --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3e2c790126fe..dce5c589a1fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17548,6 +17548,12 @@ F: drivers/most/ F: drivers/staging/most/ F: include/linux/most.h =20 +MOTORCOMM DWMAC GLUE DRIVER +M: Yao Zi +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c + MOTORCOMM PHY DRIVER M: Frank L: netdev@vger.kernel.org --=20 2.51.2