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Tue, 11 Nov 2025 01:16:44 -0800 From: Kartik Rajput To: , , , , , , , , , , , , , CC: Subject: [PATCH v11 3/4] i2c: tegra: Add support for SW mutex register Date: Tue, 11 Nov 2025 14:46:26 +0530 Message-ID: <20251111091627.870613-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251111091627.870613-1-kkartik@nvidia.com> References: <20251111091627.870613-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002316:EE_|BL3PR12MB6474:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a0d780e-112d-420c-c940-08de21031450 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6pJqve84RbAvXoa0meUDYnv4A4liVTOl4/5eGhzn0PrDV8nPKUlTjtDXissk?= =?us-ascii?Q?DwVSVOXisWpmHvybzuDvxGZJBrbWUsp5zAJfe/4Qh27DFVubmq6kTSMQBDM/?= =?us-ascii?Q?vFTM/jj0b3qiUEpAmtm+3zJVh5g4Z0IgeYKlZXstlQuOYBrL7paIVMwoa0T2?= =?us-ascii?Q?04OF2rxTvddadMvglTivoFX0W+RzkmCyXaYosp6Yiqj/EARudPcLNTu5xN+e?= =?us-ascii?Q?WSbqaw956VVc2+NELx29iTtzFez1iTV1WXWyp6IzMAttOt5PidqPC2MKOXBw?= =?us-ascii?Q?4JUeHZnYYOSIk8fpw2ervru8oRk0yQJkmUKcDKf9ma7h0z2eEubxZpbp7zLm?= =?us-ascii?Q?+KmnkMJ47hqm1QTood76XI9SS3qzpEvKJoi1Y9LsMwGtl9t92SROJzTCBHg6?= =?us-ascii?Q?OmSGy0f9bUwGv1k679XJ4CYkIjkYzXqXi7wckjDoWGmXjbLRYRmMx5yeWj5B?= =?us-ascii?Q?qZpUC21VPvXTMpsKuNeOJ25g2dzHIjYIXQFrC/dfpD5dBTnUg1//9YUQ9UbM?= =?us-ascii?Q?6QYOIYZxxYuGYeDflCytKQ16lZSHqeHIZ/cGGwH2f/RmXGDEKoBpANfs/Epc?= =?us-ascii?Q?fSVCfxkNfZCquxCb1xDRKTfrxd5ksR7JTLu6/i0LxQRCN8Odsk+vB5jRwSCW?= =?us-ascii?Q?9PDAMifXBtU3SayAeOh1wehAARc2Ob+LhY66/xExncicExylvkZsgxHPWF7D?= =?us-ascii?Q?b+JOqrhzbDwiVTodKOZ4ySZm+uE2GZ0BDECTlL3eJjVihscq1zMRLRvhTPGG?= =?us-ascii?Q?jmS09Jcw2CD1fMnOhN2IAeKfJfpbQ7mumlqR6wFcFNc+fns+RnJyLTbNcJeX?= =?us-ascii?Q?w2FmrdK7gmX5IIkyVDqTtfaBsrSOzlt6bOu7OAPt1WAAXHBEpETA9pt5SHUT?= =?us-ascii?Q?5ecjUwrftw4KFbxGS5Kx0UBQbxHdQkN4xdB2EWtuwjWzh3rZFVKO5rHYNr2E?= =?us-ascii?Q?OjjGmdYtvPmCb8PmSAYBCzNBhy6/656MmYfAM5IsFepKlXGnuxX8hIrzdRud?= =?us-ascii?Q?+maFu6MwhWjJBNUIIHBlZjvxvBdZ8bU8E3DDpe2A8OEchZmH7O3WPnLpAlBs?= =?us-ascii?Q?Du/WvbVqpG9CI0cwWNQmeUq+LAHdFOa6ib+aPBz20nwnaxSMc2up+x+CUAQ8?= =?us-ascii?Q?mgGYbqj158t6vfQUzOf5qswtHZ+WV3PnFBzShWxVSsLxZhMZ9r4DqehD+fCl?= =?us-ascii?Q?Ds6TcVCTm+U2+zadgwlju5DYzgkylgsfsUDCVTNNn1HKuCNJ/xdOSB/dbMLt?= =?us-ascii?Q?2N7IcdT5y0l3ZsSB6rS5AlNG68b5vq38CoqigpV3JP8PvhS7P0UltZHCFXUX?= =?us-ascii?Q?Ag106esqCIBM6b+FQw7grgWTnGoFaOQXstQRdsD73U8pRfN79rlM0C4c+a6k?= =?us-ascii?Q?T75RDUFlgfrWyc5wDdHNMYy4neXKo3l9j1RGFX5l145U0xLRrpC/9mtGndM/?= =?us-ascii?Q?GxAPU0dNTq03nfVf/L38yJLE84sas4JeA3raVFa0orkaW7lGRfJCluacx1u6?= =?us-ascii?Q?CjOakMNig/yi2DI5WoGq8fBmRibut/Zy02tuh2gSvxGQ31lv0fFrcTNZts7y?= =?us-ascii?Q?1oKUO0iw8wlVL5K8Vyl/2VYIeRfd92C9rmsLuh5x?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 09:17:04.2289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a0d780e-112d-420c-c940-08de21031450 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002316.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6474 Content-Type: text/plain; charset="utf-8" Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. This involves following steps: - A firmware/OS writes its unique ID to the mutex REQUEST field. - Ownership is established when reading the GRANT field returns the same ID. - If GRANT shows a different non-zero ID, the firmware/OS retries until timeout. - After completing access, it releases the mutex by writing 0. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Kartik Rajput Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- v7 -> v8: * Use `bool` instead of `int` for `locked` variable in tegra_i2c_mutex_lock() function. v6 -> v7: * Return bool from tegra_i2c_mutex_acquired() and tegra_i2c_mutex_trylock() functions. * Move `has_mutex` check inside tegra_i2c_mutex_lock/unlock functions. * Remove redundant empty line added in tegra_i2c_xfer() in v6. * Fix pm_runtime_put() not getting called if mutex unlock fails. * In tegra_i2c_mutex_lock() simplify the logic to check if the mutex is acquired or not by checking the value of `ret` variable. * Update commit message to describe the functioning of SW mutex feature. v4 -> v6: * Guard tegra_i2c_mutex_lock() and tegra_i2c_mutex_unlock() to ensure that they are called on platforms which support SW mutex. v3 -> v4: * Update timeout logic of tegra_i2c_mutex_lock() to use read_poll_timeout APIs for improving timeout logic. * Add tegra_i2c_mutex_acquired() to check if mutex is acquired or not. * Rename I2C_SW_MUTEX_ID as I2C_SW_MUTEX_ID_CCPLEX. * Function tegra_i2c_poll_register() was moved unnecessarily, it has now been moved to its original location. * Use tegra_i2c_mutex_lock/unlock APIs in the tegra_i2c_xfer() function. This ensures proper propagation of error in case mutex lock fails. Please note that as the function tegra_i2c_xfer() is already guarded by the bus lock operation there is no need of additional lock for the tegra_i2c_mutex_lock/unlock APIs. v2 -> v3: * Update tegra_i2c_mutex_trylock and tegra_i2c_mutex_unlock to use readl and writel APIs instead of i2c_readl and i2c_writel which use relaxed APIs. * Use dev_warn instead of WARN_ON if mutex lock/unlock fails. v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 92 ++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2b18ceb837da..3c20cb4a8fa6 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -137,6 +137,14 @@ =20 #define I2C_MASTER_RESET_CNTRL 0x0a8 =20 +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID_CCPLEX 9 + +/* SW mutex acquire timeout value in microseconds. */ +#define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC) + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 =20 @@ -210,6 +218,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -237,6 +246,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; =20 /** @@ -381,6 +391,76 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, = void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } =20 +static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + return id =3D=3D I2C_SW_MUTEX_ID_CCPLEX; +} + +static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id !=3D 0 && id !=3D I2C_SW_MUTEX_ID_CCPLEX) + return false; + + val =3D FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX); + writel(val, i2c_dev->base + reg); + + return tegra_i2c_mutex_acquired(i2c_dev); +} + +static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + bool locked; + int ret; + + if (!i2c_dev->hw->has_mutex) + return 0; + + if (i2c_dev->atomic_mode) + ret =3D read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked, + USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US, + false, i2c_dev); + else + ret =3D read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_= PER_MSEC, + I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev); + + if (ret) + dev_warn(i2c_dev->dev, "failed to acquire mutex\n"); + + return ret; +} + +static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + if (!i2c_dev->hw->has_mutex) + return 0; + + val =3D readl(i2c_dev->base + reg); + + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id && id !=3D I2C_SW_MUTEX_ID_CCPLEX) { + dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n"= , id); + return -EPERM; + } + + writel(0, i2c_dev->base + reg); + + return 0; +} + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -1423,6 +1503,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, = struct i2c_msg msgs[], return ret; } =20 + ret =3D tegra_i2c_mutex_lock(i2c_dev); + if (ret) + return ret; + for (i =3D 0; i < num; i++) { enum msg_end_type end_type =3D MSG_END_STOP; =20 @@ -1452,6 +1536,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, s= truct i2c_msg msgs[], break; } =20 + ret =3D tegra_i2c_mutex_unlock(i2c_dev); pm_runtime_put(i2c_dev->dev); =20 return ret ?: i; @@ -1528,6 +1613,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { @@ -1554,6 +1640,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1580,6 +1667,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1606,6 +1694,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1632,6 +1721,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { @@ -1658,6 +1748,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1686,6 +1777,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D true, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { --=20 2.43.0