From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93953225761; Tue, 11 Nov 2025 08:06:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762848413; cv=none; b=I9I1sWOtgdwmxcmwPQo+iE3DELt9sT5DPqJgn66MJeyGKWCTvF+fvELEayXiBgbsKU6qA/qK7pQFePGkqJf9zCiB+UUG85i/dLavKwO3ytH/PAxHGiMk2RfFiX4CcsIqjE7r9FPltAxx3WGJmFFacPOcCbKTh7BR27OksxOU4Ew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762848413; c=relaxed/simple; bh=+dx0yAue3k/b+NhkIOWETt6EUxGzeOC9bbDVu5NRtzg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=WyOZhir/pVAnkK8ZMHVlxIVPCxb7yaCf3vO47M77gaUKY3549THCGpW/n0BekmFoPDTUwWW7Y3Dkly3mDMN/eDm6/L1mFnSKwvQZVd6N4Jq6HscSDvdNNz22ichDDeVZcKTL0so2jjKqczCbFRTrgaEgOQIiqfqHF6H9ZuY+Foo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=O1O/W8AA; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="O1O/W8AA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=I5TppMaK+ikNiBO g8YvMLHSWasF8jG7nBiJREzuIfZ4=; b=O1O/W8AAda22sTQLo7jG1n1WNBbMb2c TanABFK3Rurg4S122KrUN6gvYgI84moOK1t3w65f9bWgYaFQRsFJBeEU+I0L94XD f0WWfAN/WXVP3enr1uXNndgPYBwNXmR2GLV9LwrQLufBNXcaahhR6TLn6SRD498O hV37Q+wQa2Us= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnq6ln7hJpK0KCDA--.117S3; Tue, 11 Nov 2025 16:06:06 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: christophe.jaillet@wanadoo.fr, corbet@lwn.net, devicetree@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, wenliang202407@163.com Subject: [PATCH 1/8] dt-binding:ti,ina3221:Add SQ52210 Date: Tue, 11 Nov 2025 03:05:39 -0500 Message-Id: <20251111080546.32421-2-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251111080546.32421-1-wenliang202407@163.com> References: <20251111080546.32421-1-wenliang202407@163.com> X-CM-TRANSID: _____wCnq6ln7hJpK0KCDA--.117S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxJF1ruFWUCryxCry5tFy5Jwb_yoW8GFy7pF WIkr98Ww1Sqw1fX3yIgF4Fkr15Jws7ua12kFnru3yIqF4DGryYqa95Kw1qyry3JrWfXFW7 Wa4Igr48Kw1vyr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUvfOrUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/1tbiRx0D02kS5gDazAAAsB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a compatible string for sq52210, sq52210 is forward compatible with INA3221 and add alert register to implement four additional alert function. Signed-off-by: Wenliang Yan --- .../devicetree/bindings/hwmon/ti,ina3221.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml b/Docu= mentation/devicetree/bindings/hwmon/ti,ina3221.yaml index 5f10f1207d69..0fae82ca3ee1 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml @@ -12,7 +12,9 @@ maintainers: =20 properties: compatible: - const: ti,ina3221 + enum: + - silergy,sq52210 + - ti,ina3221 =20 reg: maxItems: 1 @@ -77,6 +79,18 @@ patternProperties: exclude specific channels from the summation control function. type: boolean =20 + alert-type: + description: | + The SQ52210 features a configurable alert function with four + types: SUL, BOL, BUL, and POL. Each channel can be configured to + select one of these types to enable the alert function. This ale= rt + function can operate concurrently with both Critical and Warning + functions. + + The configuration must use numerical values 0 through 3, + 0 corresponds to SUL, 1 to BOL, 2 to BUL, and 3 to POL. + enum: [ 0, 1, 2, 3 ] + required: - reg =20 --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A87242FD7D0; Tue, 11 Nov 2025 08:06:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762848418; cv=none; b=S3oSlu+t4309uXMhYxRCL52bhLS9rtg9+2bEAfj+AuO06od77PEJz+lEr+SQcJAUXpya9gslcd++AXP1ZHM0yOI/JfoWE8Zib2r+ElCZEFJiNUT8RO/9QmkYdb6RSyD+EHeXutykgPPqvpipAfCMDjKtg+wjM002kTitQowVnsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762848418; c=relaxed/simple; bh=CX/PSWNrjKc+hEDePDyvgxX6zfLVBi/fR5WqiOSW9TA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=UaY3EcyEoUkxOahzEz3yxTg5CISmPjZQ54i+AmckNYztCnO2XcvaGomjkpdji8ZWZyQ+M6+N+8gXzRkBdPN2Vx9oFAIOtl2Wi+D3x1dtgRoL9S7G/en5uBf92Nq9kwWE3gwFaAqIbLYLS2l3KNc6xK2KGlllSD5rBUY+s7mhCXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=efXiPWVK; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="efXiPWVK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=qXolhaRWieEKrGJ SOG0StxPvKSJDw5mx4INVPcUdE/A=; b=efXiPWVKl9iwy1kAs5F/tXRUUlx6X3u Q9EjprHDErk6ulbKHcukAPPSmMlBp6gF05iLnapNyHWsq1DC6cdGScIYuABNtCVp Ytk6tH6CQ6qSLBIMCxj17mbN2f/jCSHHzMC/H5cGLowAkkz/arbFuO24Eu3qJPwp //+Q2kK5dD+Y= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnq6ln7hJpK0KCDA--.117S4; Tue, 11 Nov 2025 16:06:07 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: christophe.jaillet@wanadoo.fr, conor+dt@kernel.org, corbet@lwn.net, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, wenliang202407@163.com Subject: [PATCH 2/8] hwmon:(ina3221)Add support for SQ52210 Date: Tue, 11 Nov 2025 03:05:40 -0500 Message-Id: <20251111080546.32421-3-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251111080546.32421-1-wenliang202407@163.com> References: <20251111080546.32421-1-wenliang202407@163.com> X-CM-TRANSID: _____wCnq6ln7hJpK0KCDA--.117S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF4rJw48Xry8GFWxAF1fJFb_yoW5Zw4xpa n5Ca4rtr45Xr4Ig3yfKFs5tF15tr4xG3yIvrnrK3yIvF4DAry0qF1rKw4qyr98ZFyfZF4U X342y3y8uwnrJw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR8hL8UUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCvw+1iWkS7m9YDwAA3h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 is compatible with INA3221, but also includes current registers, power registers, and registers related to alerts. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 5ecc68dcf169..80c1bcc7edd7 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -34,6 +34,17 @@ #define INA3221_SHUNT_SUM 0x0d #define INA3221_CRIT_SUM 0x0e #define INA3221_MASK_ENABLE 0x0f +#define SQ52210_ALERT_CONFIG 0x12 +#define SQ52210_CALIBRATION 0x14 +#define SQ52210_CURRENT1 0x15 +#define SQ52210_CURRENT2 0x16 +#define SQ52210_CURRENT3 0x17 +#define SQ52210_POWER1 0x18 +#define SQ52210_POWER2 0x19 +#define SQ52210_POWER3 0x1A +#define SQ52210_ALERT_LIMIT1 0x1B +#define SQ52210_ALERT_LIMIT2 0x1C +#define SQ52210_ALERT_LIMIT3 0x1D =20 #define INA3221_CONFIG_MODE_MASK GENMASK(2, 0) #define INA3221_CONFIG_MODE_POWERDOWN 0 @@ -108,8 +119,12 @@ struct ina3221_input { bool summation_disable; }; =20 +enum ina3221_ids { ina3221, sq52210 }; + + /** * struct ina3221_data - device specific information + * @chip: Chip type identifier * @pm_dev: Device pointer for pm runtime * @regmap: Register map of the device * @fields: Register fields of the device @@ -120,6 +135,8 @@ struct ina3221_input { * @single_shot: running in single-shot operating mode */ struct ina3221_data { + enum ina3221_ids chip; + struct device *pm_dev; struct regmap *regmap; struct regmap_field *fields[F_MAX_FIELDS]; @@ -734,6 +751,7 @@ static const struct regmap_range ina3221_yes_ranges[] = =3D { regmap_reg_range(INA3221_CONFIG, INA3221_BUS3), regmap_reg_range(INA3221_SHUNT_SUM, INA3221_SHUNT_SUM), regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE), + regmap_reg_range(SQ52210_ALERT_CONFIG, SQ52210_POWER3), }; =20 static const struct regmap_access_table ina3221_volatile_table =3D { @@ -818,13 +836,18 @@ static int ina3221_probe(struct i2c_client *client) struct device *dev =3D &client->dev; struct ina3221_data *ina; struct device *hwmon_dev; + enum ina3221_ids chip; char name[32]; int i, ret; =20 + chip =3D (uintptr_t)i2c_get_match_data(client); + ina =3D devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); if (!ina) return -ENOMEM; =20 + ina->chip =3D chip; + ina->regmap =3D devm_regmap_init_i2c(client, &ina3221_regmap_config); if (IS_ERR(ina->regmap)) { dev_err(dev, "Unable to allocate register map\n"); @@ -996,13 +1019,21 @@ static DEFINE_RUNTIME_DEV_PM_OPS(ina3221_pm, ina3221= _suspend, ina3221_resume, NULL); =20 static const struct of_device_id ina3221_of_match_table[] =3D { - { .compatible =3D "ti,ina3221", }, + { + .compatible =3D "silergy,sq52210", + .data =3D (void *)sq52210 + }, + { + .compatible =3D "ti,ina3221", + .data =3D (void *)ina3221 + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, ina3221_of_match_table); =20 static const struct i2c_device_id ina3221_ids[] =3D { - { "ina3221" }, + { "ina3221", ina3221 }, + { "sq52210", sq52210 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(i2c, ina3221_ids); --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 517DA2DC76C; Tue, 11 Nov 2025 08:06:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762848415; 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dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="DG9tKP4o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=3t0h6n+eqtjIrFM pOBvIO1k86GOu1HiS+K0i+CYmE0M=; b=DG9tKP4oGXDyjYP/uvMpDRWOmDdkSNx cWRw6iPpnSlcoJ64JZGUSPyAoeR+b+cnczhXjLdBAoSvJL7R2bHJwZGnah0NzKm2 eqshPTH+EHOEqJBXl/BaCwU7Ux0EicvkZQR/GQB9nnEARqvBHlJEAf3KujtWKNjE bDwwQzY/dqF8= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnq6ln7hJpK0KCDA--.117S5; Tue, 11 Nov 2025 16:06:08 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: christophe.jaillet@wanadoo.fr, conor+dt@kernel.org, corbet@lwn.net, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, wenliang202407@163.com Subject: [PATCH 3/8] hwmon:(ina3221)Support alert-type Date: Tue, 11 Nov 2025 03:05:41 -0500 Message-Id: <20251111080546.32421-4-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251111080546.32421-1-wenliang202407@163.com> References: <20251111080546.32421-1-wenliang202407@163.com> X-CM-TRANSID: _____wCnq6ln7hJpK0KCDA--.117S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxGr4rCFyfKF1kAw47Jw45trb_yoWrCF1fpa yYyFyrtr12qF4Sg393KFs5CF1Fyw4xXrW7trn3W340vF47JryjvFyrGF1DtFyYkr1rZF17 J3y7tFWUCw4DAw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUEfOwUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/1tbibgED02kS5prMFwAAsj Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 supports setting alert-type, and this parameter has been described in the devicetree. Add support for it to the driver. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 73 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 80c1bcc7edd7..ee9ad022e255 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -65,6 +65,8 @@ =20 #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 +#define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) + #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 =20 @@ -105,6 +107,13 @@ enum ina3221_channels { INA3221_NUM_CHANNELS }; =20 +enum ina3221_alert_type { + SUL, + BOL, + BUL, + POL +}; + /** * struct ina3221_input - channel input source specific information * @label: label of channel input source @@ -121,9 +130,15 @@ struct ina3221_input { =20 enum ina3221_ids { ina3221, sq52210 }; =20 +struct ina3221_config { + bool has_alerts; /* chip supports alerts and limits */ + bool has_current; /* chip has internal current reg */ + bool has_power; /* chip has internal power reg */ +}; =20 /** * struct ina3221_data - device specific information + * @config: Used to store characteristics of different chips * @chip: Chip type identifier * @pm_dev: Device pointer for pm runtime * @regmap: Register map of the device @@ -132,9 +147,11 @@ enum ina3221_ids { ina3221, sq52210 }; * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE + * @alert_type_select: Used to store the alert trigger type * @single_shot: running in single-shot operating mode */ struct ina3221_data { + const struct ina3221_config *config; enum ina3221_ids chip; =20 struct device *pm_dev; @@ -144,10 +161,24 @@ struct ina3221_data { u32 reg_config; int summation_shunt_resistor; u32 summation_channel_control; + u32 alert_type_select; =20 bool single_shot; }; =20 +static const struct ina3221_config ina3221_config[] =3D { + [ina3221] =3D { + .has_alerts =3D false, + .has_current =3D false, + .has_power =3D false, + }, + [sq52210] =3D { + .has_alerts =3D true, + .has_current =3D true, + .has_power =3D true, + }, +}; + static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channe= l) { /* Summation channel checks shunt resistor values */ @@ -772,7 +803,7 @@ static int ina3221_probe_child_from_dt(struct device *d= ev, struct ina3221_data *ina) { struct ina3221_input *input; - u32 val; + u32 val, alert_type; int ret; =20 ret =3D of_property_read_u32(child, "reg", &val); @@ -792,6 +823,34 @@ static int ina3221_probe_child_from_dt(struct device *= dev, return 0; } =20 + if (ina->config->has_alerts) { + ret =3D of_property_read_u32(child, "alert-type", &alert_type); + if (ret < 0) { + dev_err(dev, "missing alert-type property of %pOFn\n", child); + return ret; + } else if (alert_type > POL) { + dev_err(dev, "invalid alert-type of %pOFn\n", child); + return -EINVAL; + } + switch (alert_type) { + /* val is channel value*/ + case SUL: + ina->alert_type_select |=3D BIT(15 - val); + break; + case BOL: + ina->alert_type_select |=3D BIT(12 - val); + break; + case BUL: + ina->alert_type_select |=3D BIT(9 - val); + break; + case POL: + ina->alert_type_select |=3D BIT(6 - val); + break; + default: + break; + } + } + /* Save the connected input label if available */ of_property_read_string(child, "label", &input->label); =20 @@ -847,6 +906,7 @@ static int ina3221_probe(struct i2c_client *client) return -ENOMEM; =20 ina->chip =3D chip; + ina->config =3D &ina3221_config[chip]; =20 ina->regmap =3D devm_regmap_init_i2c(client, &ina3221_regmap_config); if (IS_ERR(ina->regmap)) { @@ -1012,6 +1072,17 @@ static int ina3221_resume(struct device *dev) } } =20 + /* Restore alert config register value to hardware */ + if (ina->config->has_alerts) { + ret =3D regmap_update_bits(ina->regmap, SQ52210_ALERT_CONFIG, + SQ52210_ALERT_CONFIG_MASK, + ina->alert_type_select); + if (ret) { + dev_err(dev, "Unable to select alert type\n"); + return ret; + } + } + return 0; } =20 --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 939BA231A30; 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arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ZkM7/ght" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=jyygY7O70/zK+La 2Mnqd8X8wqYmBF5ypQLHKNTfsnys=; b=ZkM7/ghttr2Jkzu89YXMoWvuBREPVSi ok/agrJUxWlUq1vY2LYYllVNLTZuYyfLJkrdwyzipTWJvbqTGq3olwMvUzyTfnFu q3dw8iI37uOXC5LCd3qdmGB8eH87XgCXXo6U2IWYoGIa4e8FJBHxdL0PVfluydAI Wj6+U8Y4OkZU= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnq6ln7hJpK0KCDA--.117S6; Tue, 11 Nov 2025 16:06:10 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: christophe.jaillet@wanadoo.fr, conor+dt@kernel.org, corbet@lwn.net, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, wenliang202407@163.com Subject: [PATCH 4/8] hwmon:(ina3221)Pre-calculate current and power LSB Date: Tue, 11 Nov 2025 03:05:42 -0500 Message-Id: <20251111080546.32421-5-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251111080546.32421-1-wenliang202407@163.com> References: <20251111080546.32421-1-wenliang202407@163.com> X-CM-TRANSID: _____wCnq6ln7hJpK0KCDA--.117S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxAFy7WFW8ZF4UWr1rZr43Jrb_yoW7Jr45pF 4fGFy5ta4jq3WSga9Ikan7GF1rt34xJF47trsrG34IqanrKryq9ayrJa4DtFy5Ary5ZF17 X3yDtr4DCan7AaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUFLvNUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/1tbiRxoD02kS5gDbPgAAs1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The LSB for current and power can be pre-calculated for data read/write operations. The current LSB is determined by the calibration value and shunt resistor value, with the calibration value fixed within the driver. The power LSB can be derived from the current LSB. Use DIV_ROUND_CLOSEST function to replace division operations and reduce rouding errors. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 71 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index ee9ad022e255..e339860ed3a2 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -69,6 +69,7 @@ =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 +#define SQ52210_SHUNT_LSB 40000000 /* pV/LSB */ =20 enum ina3221_fields { /* Configuration */ @@ -134,6 +135,8 @@ struct ina3221_config { bool has_alerts; /* chip supports alerts and limits */ bool has_current; /* chip has internal current reg */ bool has_power; /* chip has internal power reg */ + int calibration_value; /* calculate current_lsb */ + int power_lsb_factor; }; =20 /** @@ -148,6 +151,8 @@ struct ina3221_config { * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE * @alert_type_select: Used to store the alert trigger type + * @current_lsb_uA: The value of one LSB corresponding to the current regi= ster + * @power_lsb_uW: The value of one LSB corresponding to the power register * @single_shot: running in single-shot operating mode */ struct ina3221_data { @@ -162,6 +167,8 @@ struct ina3221_data { int summation_shunt_resistor; u32 summation_channel_control; u32 alert_type_select; + long current_lsb_uA; + long power_lsb_uW; =20 bool single_shot; }; @@ -176,6 +183,13 @@ static const struct ina3221_config ina3221_config[] = =3D { .has_alerts =3D true, .has_current =3D true, .has_power =3D true, + /* + * With this default value configuration, + * the following formula can be obtained: + * Current_LSB =3D Shunt_LSB / Rshunt + */ + .calibration_value =3D 256, + .power_lsb_factor =3D 20, }, }; =20 @@ -729,6 +743,25 @@ static const struct hwmon_chip_info ina3221_chip_info = =3D { }; =20 /* Extra attribute groups */ + +/* + * Calculate the value corresponding to one LSB of the current and + * power registers. + * formula : Current_LSB =3D Shunt_LSB / Rshunt + * Power_LSB =3D power_lsb_factor * Current_LSB + */ +static int ina3221_set_shunt(struct ina3221_data *ina, unsigned long val) +{ + if (!val || val > SQ52210_SHUNT_LSB) + return -EINVAL; + + ina->current_lsb_uA =3D DIV_ROUND_CLOSEST(SQ52210_SHUNT_LSB, val); + ina->power_lsb_uW =3D ina->config->power_lsb_factor * + ina->current_lsb_uA; + + return 0; +} + static ssize_t ina3221_shunt_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -761,7 +794,17 @@ static ssize_t ina3221_shunt_store(struct device *dev, =20 /* Update summation_shunt_resistor for summation channel */ ina->summation_shunt_resistor =3D ina3221_summation_shunt_resistor(ina); - + /* + * The current and power registers can only be used when + * all enabled channels have identical shunt resistors + */ + if (ina->summation_shunt_resistor) { + if (ina->config->has_current) { + ret =3D ina3221_set_shunt(ina, val); + if (ret < 0) + return ret; + } + } return count; } =20 @@ -953,6 +996,16 @@ static int ina3221_probe(struct i2c_client *client) ina->summation_channel_control |=3D BIT(14 - i); } =20 + /* + * The current and power registers can only be used when + * all enabled channels have identical shunt resistors + */ + if (ina->summation_shunt_resistor) { + ret =3D ina3221_set_shunt(ina, ina->summation_shunt_resistor); + if (ret < 0) + return ret; + } + ina->pm_dev =3D dev; dev_set_drvdata(dev, ina); =20 @@ -970,8 +1023,8 @@ static int ina3221_probe(struct i2c_client *client) } =20 hwmon_dev =3D devm_hwmon_device_register_with_info(dev, client->name, ina, - &ina3221_chip_info, - ina3221_groups); + &ina3221_chip_info, + ina3221_groups); if (IS_ERR(hwmon_dev)) { dev_err(dev, "Unable to register hwmon device\n"); ret =3D PTR_ERR(hwmon_dev); @@ -1070,6 +1123,18 @@ static int ina3221_resume(struct device *dev) dev_err(dev, "Unable to control summation channel\n"); return ret; } + /* + * The calibration register can only be enabled when all + * shunt resistor values are identical. + */ + if (ina->config->has_current) { + ret =3D regmap_write(ina->regmap, SQ52210_CALIBRATION, + ina->config->calibration_value); + if (ret) { + dev_err(dev, "Unable to set calibration value\n"); + return ret; + } + } } =20 /* Restore alert config register value to hardware */ --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 388A12E6CA4; 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charset="utf-8" SQ52210 has built-in current and power sensors as well as multiple alert functions. Add power attributes and different critical characteristics in hwmon to report the corresponding data. Signed-off-by: Wenliang Yan --- Documentation/hwmon/ina3221.rst | 24 +++++++++++++ drivers/hwmon/ina3221.c | 60 +++++++++++++++++++++++++++++---- 2 files changed, 77 insertions(+), 7 deletions(-) diff --git a/Documentation/hwmon/ina3221.rst b/Documentation/hwmon/ina3221.= rst index 8c12c54d2c24..224c6cf735ed 100644 --- a/Documentation/hwmon/ina3221.rst +++ b/Documentation/hwmon/ina3221.rst @@ -13,6 +13,13 @@ Supported chips: =20 https://www.ti.com/ =20 + * Silergy SQ52210 + + Prefix: 'SQ52210' + + Addresses: I2C 0x40 - 0x43 + + Author: Andrew F. Davis =20 Description @@ -23,6 +30,9 @@ side of up to three D.C. power supplies. The INA3221 moni= tors both shunt drop and supply voltage, with programmable conversion times and averaging, curr= ent and power are calculated host-side from these. =20 +The SQ52210 is a mostly compatible chip from Silergy. It incorporates inte= rnal +current and power registers, and provides an extra configurable alert func= tion. + Sysfs entries ------------- =20 @@ -72,3 +82,17 @@ update_interval Data conversion time in millisec= ond, following: Note that setting update_interval to 0ms sets both= BC and SC to 140 us (minimum conversion time). =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Additional sysfs entries for sq52210 +------------------------------------- + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +in[123]_crit Critical high bus voltage +in[123]_crit_alarm Bus voltage critical high alarm +in[123]_lcrit Critical low bus voltage +in[123]_lcrit_alarm Bus voltage critical low alarm +curr[123]_lcrit Critical low current +curr[123]_lcrit_alarm Current critical low alarm +power[123]_input Current for channels 1, 2, and 3 respectively +power[123]_crit Critical high power +power[123]_crit_alarm Power critical high alarm diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index e339860ed3a2..77b2505a49a2 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -652,6 +652,8 @@ static umode_t ina3221_is_visible(const void *drvdata, { const struct ina3221_data *ina =3D drvdata; const struct ina3221_input *input =3D NULL; + bool has_alerts =3D ina->config->has_alerts; + bool has_power =3D ina->config->has_power; =20 switch (type) { case hwmon_chip: @@ -679,6 +681,16 @@ static umode_t ina3221_is_visible(const void *drvdata, return 0444; case hwmon_in_enable: return 0644; + case hwmon_in_crit: + case hwmon_in_lcrit: + if (has_alerts) + return 0644; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + if (has_alerts) + return 0444; + return 0; default: return 0; } @@ -691,6 +703,28 @@ static umode_t ina3221_is_visible(const void *drvdata, case hwmon_curr_crit: case hwmon_curr_max: return 0644; + case hwmon_curr_lcrit: + if (has_alerts) + return 0644; + return 0; + case hwmon_curr_lcrit_alarm: + if (has_alerts) + return 0444; + return 0; + default: + return 0; + } + case hwmon_power: + switch (attr) { + case hwmon_power_input: + case hwmon_power_crit_alarm: + if (has_power) + return 0444; + return 0; + case hwmon_power_crit: + if (has_alerts) + return 0644; + return 0; default: return 0; } @@ -701,7 +735,14 @@ static umode_t ina3221_is_visible(const void *drvdata, =20 #define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \ HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \ - HWMON_C_MAX | HWMON_C_MAX_ALARM) + HWMON_C_MAX | HWMON_C_MAX_ALARM | \ + HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM) +#define SQ52210_HWMON_POWER_CONFIG (HWMON_P_INPUT | \ + HWMON_P_CRIT | HWMON_P_CRIT_ALARM) +#define SQ52210_HWMON_BUS_CONFIG (HWMON_I_INPUT | \ + HWMON_I_ENABLE | HWMON_I_LABEL | \ + HWMON_I_LCRIT_ALARM | HWMON_I_LCRIT |\ + HWMON_I_CRIT_ALARM | HWMON_I_CRIT) =20 static const struct hwmon_channel_info * const ina3221_info[] =3D { HWMON_CHANNEL_INFO(chip, @@ -711,9 +752,9 @@ static const struct hwmon_channel_info * const ina3221_= info[] =3D { /* 0: dummy, skipped in is_visible */ HWMON_I_INPUT, /* 1-3: input voltage Channels */ - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, + SQ52210_HWMON_BUS_CONFIG, + SQ52210_HWMON_BUS_CONFIG, + SQ52210_HWMON_BUS_CONFIG, /* 4-6: shunt voltage Channels */ HWMON_I_INPUT, HWMON_I_INPUT, @@ -727,6 +768,11 @@ static const struct hwmon_channel_info * const ina3221= _info[] =3D { INA3221_HWMON_CURR_CONFIG, /* 4: summation of current channels */ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM), + HWMON_CHANNEL_INFO(power, + /* 1-3: power channels*/ + SQ52210_HWMON_POWER_CONFIG, + SQ52210_HWMON_POWER_CONFIG, + SQ52210_HWMON_POWER_CONFIG), NULL }; =20 @@ -748,7 +794,7 @@ static const struct hwmon_chip_info ina3221_chip_info = =3D { * Calculate the value corresponding to one LSB of the current and * power registers. * formula : Current_LSB =3D Shunt_LSB / Rshunt - * Power_LSB =3D power_lsb_factor * Current_LSB + * Power_LSB =3D power_lsb_factor * Current_LSB */ static int ina3221_set_shunt(struct ina3221_data *ina, unsigned long val) { @@ -1023,8 +1069,8 @@ static int ina3221_probe(struct i2c_client *client) } =20 hwmon_dev =3D devm_hwmon_device_register_with_info(dev, client->name, ina, - &ina3221_chip_info, - ina3221_groups); + &ina3221_chip_info, + ina3221_groups); if (IS_ERR(hwmon_dev)) { dev_err(dev, "Unable to register hwmon device\n"); ret =3D PTR_ERR(hwmon_dev); --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A87D02FE048; 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charset="utf-8" SQ52210 adds current, power, and alert-limit sensors, with read/write functions modified to accommodate these new changes. The ina3221_read_value function has been rewritten to adapt to the new register format for data reading. The sq52210_alert_to_reg function has been added to handle reading of different data types. Each channel supports four new alert trigger modes, with only one trigger active at any given time. Alert values are stored in the same register. The sq52210_alert_limit_write function has been implemented for writing alert threshold values. The 'in' read/write functions have been modified to add crit, lcrit, crit_alarm, and lcrit_alarm characteristics. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 182 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 178 insertions(+), 4 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 77b2505a49a2..abb6049c8eab 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -66,6 +66,9 @@ #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 #define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6)) +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5)) +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4)) =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 @@ -84,6 +87,9 @@ enum ina3221_fields { /* Alert Flags: SF is the summation-alert flag */ F_SF, F_CF3, F_CF2, F_CF1, =20 + /* Alert Flags: AFF is the alert function flag */ + F_AFF3, F_AFF2, F_AFF1, + /* sentinel */ F_MAX_FIELDS }; @@ -99,6 +105,10 @@ static const struct reg_field ina3221_reg_fields[] =3D { [F_CF3] =3D REG_FIELD(INA3221_MASK_ENABLE, 7, 7), [F_CF2] =3D REG_FIELD(INA3221_MASK_ENABLE, 8, 8), [F_CF1] =3D REG_FIELD(INA3221_MASK_ENABLE, 9, 9), + + [F_AFF3] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 1, 1), + [F_AFF2] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 2, 2), + [F_AFF1] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 3, 3), }; =20 enum ina3221_channels { @@ -293,11 +303,39 @@ static int ina3221_read_value(struct ina3221_data *in= a, unsigned int reg, * Shunt Voltage Sum register has 14-bit value with 1-bit shift * Other Shunt Voltage registers have 12 bits with 3-bit shift */ - if (reg =3D=3D INA3221_SHUNT_SUM || reg =3D=3D INA3221_CRIT_SUM) + switch (reg) { + case INA3221_SHUNT_SUM: + case INA3221_CRIT_SUM: *val =3D sign_extend32(regval >> 1, 14); - else + break; + case SQ52210_CURRENT1: + case SQ52210_CURRENT2: + case SQ52210_CURRENT3: + case SQ52210_POWER1: + case SQ52210_POWER2: + case SQ52210_POWER3: + *val =3D regval; + break; + case INA3221_BUS1: + case INA3221_BUS2: + case INA3221_BUS3: + case INA3221_SHUNT1: + case INA3221_SHUNT2: + case INA3221_SHUNT3: + case INA3221_WARN1: + case INA3221_WARN2: + case INA3221_WARN3: + case INA3221_CRIT1: + case INA3221_CRIT2: + case INA3221_CRIT3: *val =3D sign_extend32(regval >> 3, 12); - + break; + case SQ52210_ALERT_LIMIT1: + case SQ52210_ALERT_LIMIT2: + case SQ52210_ALERT_LIMIT3: + *val =3D regval >> 3; + break; + }; return 0; } =20 @@ -311,6 +349,56 @@ static const u8 ina3221_in_reg[] =3D { INA3221_SHUNT_SUM, }; =20 +static const u8 alert_limit_reg[] =3D { + SQ52210_ALERT_LIMIT1, + SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3, +}; + +static const u8 alert_flag[] =3D { + F_AFF1, + F_AFF2, + F_AFF3, +}; + +/* + * Turns alert limit values into register values. + * Opposite of the formula in ina3221_read_value(). + */ +static u16 sq52210_alert_to_reg(struct ina3221_data *ina, int reg, long va= l) +{ + int regval; + /* + * Formula to convert voltage_uv to register value: + * regval =3D (voltage_mv / scale) << shift + * Results: + * bus_voltage: (1 / 8mV) << 3 =3D 1 mV + */ + switch (reg) { + case INA3221_BUS1: + case INA3221_BUS2: + case INA3221_BUS3: + /* clamp voltage */ + regval =3D clamp_val(val, -32760, 32760); + return regval; + case SQ52210_CURRENT1: + case SQ52210_CURRENT2: + case SQ52210_CURRENT3: + /* signed register, result in mA */ + regval =3D DIV_ROUND_CLOSEST(val * 8000, ina->current_lsb_uA); + return clamp_val(regval, -32760, 32760); + case SQ52210_POWER1: + case SQ52210_POWER2: + case SQ52210_POWER3: + regval =3D DIV_ROUND_CLOSEST(val * 8000, ina->power_lsb_uW); + return clamp_val(regval, 0, 65528); + default: + /* programmer goofed */ + WARN_ON_ONCE(1); + return 0; + } +} + static int ina3221_read_chip(struct device *dev, u32 attr, long *val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -373,6 +461,25 @@ static int ina3221_read_in(struct device *dev, u32 att= r, int channel, long *val) case hwmon_in_enable: *val =3D ina3221_is_enabled(ina, channel); return 0; + case hwmon_in_crit: + case hwmon_in_lcrit: + reg =3D alert_limit_reg[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* + * Scale of bus voltage (mV): LSB is 8mV + */ + *val =3D regval * 8; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + reg =3D alert_flag[channel]; + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; default: return -EOPNOTSUPP; } @@ -450,6 +557,58 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, } } =20 +static const u32 sq52210_alert_mask[][INA3221_NUM_CHANNELS] =3D { + [hwmon_curr_lcrit] =3D { BIT(15), BIT(14), BIT(13) }, + [hwmon_in_crit] =3D { BIT(12), BIT(11), BIT(10) }, + [hwmon_in_lcrit] =3D { BIT(9), BIT(8), BIT(7) }, + [hwmon_power_crit] =3D { BIT(6), BIT(5), BIT(4) }, +}; + +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, i= nt channel, long val) +{ + struct regmap *regmap =3D ina->regmap; + int ret, limit_reg, item; + u32 alert_group; + + if (val < 0) + return -EINVAL; + item =3D channel % INA3221_NUM_CHANNELS; + switch (item) { + case 0: + alert_group =3D SQ52210_MASK_ALERT_CHANNEL1; + limit_reg =3D SQ52210_ALERT_LIMIT1; + break; + case 1: + alert_group =3D SQ52210_MASK_ALERT_CHANNEL2; + limit_reg =3D SQ52210_ALERT_LIMIT2; + break; + case 2: + alert_group =3D SQ52210_MASK_ALERT_CHANNEL3; + limit_reg =3D SQ52210_ALERT_LIMIT3; + break; + default: + break; + } + /* + * Clear all alerts first to avoid accidentally triggering ALERT pin + * due to register write sequence. Then, only enable the alert + * if the value is non-zero. + */ + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, + alert_group, 0); + if (ret < 0) + return ret; + ret =3D regmap_write(regmap, limit_reg, + sq52210_alert_to_reg(ina, ina3221_curr_reg[attr][item], val)); + if (ret < 0) + return ret; + + if (val) + return regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, + alert_group, sq52210_alert_mask[attr][item]); + return 0; +} + static int ina3221_write_chip(struct device *dev, u32 attr, long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -586,6 +745,21 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_in(struct device *dev, u32 attr, int channel, lon= g val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_in_lcrit: + return sq52210_alert_limit_write(ina, attr, channel, val); + case hwmon_in_crit: + return sq52210_alert_limit_write(ina, attr, channel, val); + case hwmon_in_enable: + return ina3221_write_enable(dev, channel, val); + default: + return 0; + } +} static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { @@ -620,7 +794,7 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, break; case hwmon_in: /* 0-align channel ID */ - ret =3D ina3221_write_enable(dev, channel - 1, val); + ret =3D ina3221_write_in(dev, attr, channel - 1, val); break; case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F097230101C; Tue, 11 Nov 2025 08:06:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="TuIW0osF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=HW1AjLFpbCzDd1F kQpNb+K2o12psfz4Vu11gila8P9o=; b=TuIW0osFnwlSj5aSVaVUVflEev2GhEg fqlEXLOJMh0J7U+hapshabBwZmrpJK4IHLjsya+x7lN69FjLSC9Z4HxQmNbyObgi MZ+jpHccbKHDYcuYCX8XvQyH4a2Yacxttw1b0bvQPo5p6DlZmFT1qq7CljaHlebx GqDNZRfbtD/Y= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnq6ln7hJpK0KCDA--.117S9; Tue, 11 Nov 2025 16:06:15 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: christophe.jaillet@wanadoo.fr, conor+dt@kernel.org, corbet@lwn.net, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, wenliang202407@163.com Subject: [PATCH 7/8] hwmon:(ina3221)Support read/write functions for 'power' attribute Date: Tue, 11 Nov 2025 03:05:45 -0500 Message-Id: <20251111080546.32421-8-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251111080546.32421-1-wenliang202407@163.com> References: <20251111080546.32421-1-wenliang202407@163.com> X-CM-TRANSID: _____wCnq6ln7hJpK0KCDA--.117S9 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF45ZFWxCr1rur4DWF48WFg_yoWrWFWkpw 4DCFy5tw42qF1SvwsakF4DKw1Ykr4xX3y2yr9Fkwnava1UAr90gFyrJa4vyry5Cry3XF47 JayxJF15u3ZrKr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUX0ePUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/1tbibhED02kS5prMugABsf Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 adds power attribute to report power data, and implements read/write functions for this purpose. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 79 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 4 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index abb6049c8eab..ea01687ad1fa 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -348,19 +348,16 @@ static const u8 ina3221_in_reg[] =3D { INA3221_SHUNT3, INA3221_SHUNT_SUM, }; - static const u8 alert_limit_reg[] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, SQ52210_ALERT_LIMIT3, }; - static const u8 alert_flag[] =3D { F_AFF1, F_AFF2, F_AFF3, }; - /* * Turns alert limit values into register values. * Opposite of the formula in ina3221_read_value(). @@ -557,6 +554,61 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, } } =20 +static const u8 ina3221_power_reg[][INA3221_NUM_CHANNELS] =3D { + [hwmon_power_input] =3D { SQ52210_POWER1, SQ52210_POWER2, SQ52210_POWER3 = }, + [hwmon_power_crit] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3 }, + [hwmon_power_crit_alarm] =3D { F_AFF1, F_AFF2, F_AFF3 }, +}; + +static int ina3221_read_power(struct device *dev, u32 attr, int channel, l= ong *val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + u8 reg =3D ina3221_power_reg[attr][channel]; + int regval, ret; + + switch (attr) { + case hwmon_power_input: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + /* Write CONFIG register to trigger a single-shot measurement */ + if (ina->single_shot) { + regmap_write(ina->regmap, INA3221_CONFIG, + ina->reg_config); + + ret =3D ina3221_wait_for_data(ina); + if (ret) + return ret; + } + + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* Return power in mW */ + *val =3D DIV_ROUND_CLOSEST(regval * ina->power_lsb_uW, 1000); + return 0; + case hwmon_power_crit: + reg =3D ina3221_power_reg[attr][channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* Return power in mW */ + *val =3D DIV_ROUND_CLOSEST(regval * ina->power_lsb_uW, 1000); + return 0; + case hwmon_power_crit_alarm: + reg =3D ina3221_power_reg[attr][channel]; + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; + + default: + return -EOPNOTSUPP; + } +} + static const u32 sq52210_alert_mask[][INA3221_NUM_CHANNELS] =3D { [hwmon_curr_lcrit] =3D { BIT(15), BIT(14), BIT(13) }, [hwmon_in_crit] =3D { BIT(12), BIT(11), BIT(10) }, @@ -760,6 +812,19 @@ static int ina3221_write_in(struct device *dev, u32 at= tr, int channel, long val) return 0; } } + +static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_power_crit: + return sq52210_alert_limit_write(ina, attr, channel, val); + default: + return 0; + } +} + static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { @@ -776,6 +841,9 @@ static int ina3221_read(struct device *dev, enum hwmon_= sensor_types type, case hwmon_curr: ret =3D ina3221_read_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_read_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; @@ -799,6 +867,9 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_write_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; @@ -977,7 +1048,7 @@ static int ina3221_set_shunt(struct ina3221_data *ina,= unsigned long val) =20 ina->current_lsb_uA =3D DIV_ROUND_CLOSEST(SQ52210_SHUNT_LSB, val); ina->power_lsb_uW =3D ina->config->power_lsb_factor * - ina->current_lsb_uA; + ina->current_lsb_uA; =20 return 0; } --=20 2.17.1 From nobody Tue Nov 11 11:30:27 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62783306B15; Tue, 11 Nov 2025 08:06:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="QK0SShaE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=k9WdnwaT6IcbCWY uC+hGTHfHC9EqlI1hGdAkWWWRtRc=; b=QK0SShaE/I6tO1hHeU8PKDVbbwiHI1T zWMgxNLgTVygpOM+LvwxYPOg3ukMfE48r5Mqq8TYa4FeJnDs7NuUR2MpzLJfdiD1 uByu7fjBbT+eoNiT1Uyt7OgRR+uvuonY+RqZC2DfnugbMnxcLQF4U3ZsTLjICGZv 3IGEVbZQUH88= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnq6ln7hJpK0KCDA--.117S10; Tue, 11 Nov 2025 16:06:17 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: christophe.jaillet@wanadoo.fr, conor+dt@kernel.org, corbet@lwn.net, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, wenliang202407@163.com Subject: [PATCH 8/8] hwmon:(ina3221)Support read/write functions for current_lcrict attribute Date: Tue, 11 Nov 2025 03:05:46 -0500 Message-Id: <20251111080546.32421-9-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251111080546.32421-1-wenliang202407@163.com> References: <20251111080546.32421-1-wenliang202407@163.com> X-CM-TRANSID: _____wCnq6ln7hJpK0KCDA--.117S10 X-Coremail-Antispam: 1Uf129KBjvJXoWxCFWDAr1kGr1ftw18XrW8WFg_yoW5AF4rpw 43Gayrtr4Yq3WIg3ySkF4kXr98Jw4xXF12yr9Fk39Y9a15AryDWFy8G3Wq93yUGFyfXa17 JayIyr48ua1qvr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUFZXrUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwBm4jGkS7nkcBAAA3Z Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modify the read/write functions for current attributes. SQ52210 can directly use its internal current registers to compare with alert values for implementing curr_lcrit functionality. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index ea01687ad1fa..50916ce26cb3 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -488,8 +488,11 @@ static const u8 ina3221_curr_reg[][INA3221_NUM_CHANNEL= S + 1] =3D { [hwmon_curr_max] =3D { INA3221_WARN1, INA3221_WARN2, INA3221_WARN3, 0 }, [hwmon_curr_crit] =3D { INA3221_CRIT1, INA3221_CRIT2, INA3221_CRIT3, INA3221_CRIT_SUM }, + [hwmon_curr_lcrit] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3, 0 }, [hwmon_curr_max_alarm] =3D { F_WF1, F_WF2, F_WF3, 0 }, [hwmon_curr_crit_alarm] =3D { F_CF1, F_CF2, F_CF3, F_SF }, + [hwmon_curr_lcrit_alarm] =3D { F_AFF1, F_AFF2, F_AFF3, 0 }, }; =20 static int ina3221_read_curr(struct device *dev, u32 attr, @@ -536,8 +539,20 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, /* Return current in mA */ *val =3D DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); return 0; + case hwmon_curr_lcrit: + if (!resistance_uo) + return -ENODATA; + + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + + /* Return current in mA */ + *val =3D DIV_ROUND_CLOSEST(regval * ina->current_lsb_uA, 1000); + return 0; case hwmon_curr_crit_alarm: case hwmon_curr_max_alarm: + case hwmon_curr_lcrit_alarm: /* No actual register read if channel is disabled */ if (!ina3221_is_enabled(ina, channel)) { /* Return 0 for alert flags */ @@ -703,10 +718,9 @@ static int ina3221_write_chip(struct device *dev, u32 = attr, long val) } } =20 -static int ina3221_write_curr(struct device *dev, u32 attr, +static int ina3221_write_curr_shunt(struct ina3221_data *ina, u32 attr, int channel, long val) { - struct ina3221_data *ina =3D dev_get_drvdata(dev); struct ina3221_input *input =3D ina->inputs; u8 reg =3D ina3221_curr_reg[attr][channel]; int resistance_uo, current_ma, voltage_uv; @@ -749,6 +763,22 @@ static int ina3221_write_curr(struct device *dev, u32 = attr, return regmap_write(ina->regmap, reg, regval); } =20 +static int ina3221_write_curr(struct device *dev, u32 attr, + int channel, long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_curr_crit: + case hwmon_curr_max: + return ina3221_write_curr_shunt(ina, attr, channel, val); + case hwmon_curr_lcrit: + return sq52210_alert_limit_write(ina, attr, channel, val); + default: + return 0; + } +} + static int ina3221_write_enable(struct device *dev, int channel, bool enab= le) { struct ina3221_data *ina =3D dev_get_drvdata(dev); --=20 2.17.1