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Mon, 10 Nov 2025 23:35:38 -0800 (PST) From: Yunhui Cui To: akpm@linux-foundation.org, alex@ghiti.fr, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, catalin.marinas@arm.com, cuiyunhui@bytedance.com, dianders@chromium.org, johannes@sipsolutions.net, lihuafei1@huawei.com, mark.rutland@arm.com, masahiroy@kernel.org, maz@kernel.org, mingo@kernel.org, nicolas.schier@linux.dev, palmer@dabbelt.com, paul.walmsley@sifive.com, suzuki.poulose@arm.com, thorsten.blum@linux.dev, wangjinchao600@gmail.com, will@kernel.org, yangyicong@hisilicon.com, zhanjie9@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley Subject: [PATCH v5 2/2] riscv: add HARDLOCKUP_DETECTOR_PERF support Date: Tue, 11 Nov 2025 15:34:59 +0800 Message-Id: <20251111073459.44030-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251111073459.44030-1-cuiyunhui@bytedance.com> References: <20251111073459.44030-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the HARDLOCKUP_DETECTOR_PERF function based on RISC-V SSE. Signed-off-by: Yunhui Cui Reviewed-by: Douglas Anderson Acked-by: Paul Walmsley --- arch/riscv/Kconfig | 3 +++ drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fadec20b87a8e..74835cdc89ddf 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -186,6 +186,9 @@ config RISCV select HAVE_PAGE_SIZE_4KB select HAVE_PCI select HAVE_PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if RISCV_PMU_SBI_SSE + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_N= MI + select WATCHDOG_PERF_ADJUST_PERIOD if HARDLOCKUP_DETECTOR_PERF && CPU_FREQ select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_POSIX_CPU_TIMERS_TASK_WORK diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index c852f64a50221..0c7c5924687c9 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -1192,6 +1193,13 @@ static int pmu_sbi_setup_sse(struct riscv_pmu *pmu) } #endif =20 +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +bool arch_perf_nmi_is_available(void) +{ + return IS_ENABLED(CONFIG_RISCV_PMU_SBI_SSE); +} +#endif + static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu =3D hlist_entry_safe(node, struct riscv_pmu, node); @@ -1618,6 +1626,8 @@ static int __init pmu_sbi_devinit(void) /* Notify legacy implementation that SBI pmu is available*/ riscv_pmu_legacy_skip_init(); =20 + lockup_detector_retry_init(); + return ret; } device_initcall(pmu_sbi_devinit) --=20 2.39.5