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Mon, 10 Nov 2025 23:35:30 -0800 (PST) From: Yunhui Cui To: akpm@linux-foundation.org, alex@ghiti.fr, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, catalin.marinas@arm.com, cuiyunhui@bytedance.com, dianders@chromium.org, johannes@sipsolutions.net, lihuafei1@huawei.com, mark.rutland@arm.com, masahiroy@kernel.org, maz@kernel.org, mingo@kernel.org, nicolas.schier@linux.dev, palmer@dabbelt.com, paul.walmsley@sifive.com, suzuki.poulose@arm.com, thorsten.blum@linux.dev, wangjinchao600@gmail.com, will@kernel.org, yangyicong@hisilicon.com, zhanjie9@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 1/2] watchdog: move arm64 watchdog_hld into common code Date: Tue, 11 Nov 2025 15:34:58 +0800 Message-Id: <20251111073459.44030-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251111073459.44030-1-cuiyunhui@bytedance.com> References: <20251111073459.44030-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the contents of arch/arm64/watchdog_hld.c to kernel/watchdog_perf.c to create a generic implementation that can be reused by other arch, such as RISC-V. Signed-off-by: Yunhui Cui Reviewed-by: Douglas Anderson --- arch/arm64/Kconfig | 1 + arch/arm64/kernel/Makefile | 1 - arch/arm64/kernel/watchdog_hld.c | 94 -------------------------------- drivers/perf/arm_pmu.c | 10 +++- include/linux/perf/arm_pmu.h | 2 - kernel/watchdog_perf.c | 83 ++++++++++++++++++++++++++++ lib/Kconfig.debug | 8 +++ 7 files changed, 101 insertions(+), 98 deletions(-) delete mode 100644 arch/arm64/kernel/watchdog_hld.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 6663ffd23f252..3f030559da178 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -231,6 +231,7 @@ config ARM64 select HAVE_GCC_PLUGINS select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI + select WATCHDOG_PERF_ADJUST_PERIOD if HARDLOCKUP_DETECTOR_PERF && CPU_FREQ select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_IOREMAP_PROT select HAVE_IRQ_TIME_ACCOUNTING diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 76f32e424065e..12d77f373fea4 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -44,7 +44,6 @@ obj-$(CONFIG_KUSER_HELPERS) +=3D kuser32.o obj-$(CONFIG_FUNCTION_TRACER) +=3D ftrace.o entry-ftrace.o obj-$(CONFIG_MODULES) +=3D module.o module-plts.o obj-$(CONFIG_PERF_EVENTS) +=3D perf_regs.o perf_callchain.o -obj-$(CONFIG_HARDLOCKUP_DETECTOR_PERF) +=3D watchdog_hld.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=3D hw_breakpoint.o obj-$(CONFIG_CPU_PM) +=3D sleep.o suspend.o obj-$(CONFIG_KGDB) +=3D kgdb.o diff --git a/arch/arm64/kernel/watchdog_hld.c b/arch/arm64/kernel/watchdog_= hld.c deleted file mode 100644 index 3093037dcb7be..0000000000000 --- a/arch/arm64/kernel/watchdog_hld.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -/* - * Safe maximum CPU frequency in case a particular platform doesn't implem= ent - * cpufreq driver. Although, architecture doesn't put any restrictions on - * maximum frequency but 5 GHz seems to be safe maximum given the available - * Arm CPUs in the market which are clocked much less than 5 GHz. On the o= ther - * hand, we can't make it much higher as it would lead to a large hard-loc= kup - * detection timeout on parts which are running slower (eg. 1GHz on - * Developerbox) and doesn't possess a cpufreq driver. - */ -#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz -u64 hw_nmi_get_sample_period(int watchdog_thresh) -{ - unsigned int cpu =3D smp_processor_id(); - unsigned long max_cpu_freq; - - max_cpu_freq =3D cpufreq_get_hw_max_freq(cpu) * 1000UL; - if (!max_cpu_freq) - max_cpu_freq =3D SAFE_MAX_CPU_FREQ; - - return (u64)max_cpu_freq * watchdog_thresh; -} - -bool __init arch_perf_nmi_is_available(void) -{ - /* - * hardlockup_detector_perf_init() will success even if Pseudo-NMI turns = off, - * however, the pmu interrupts will act like a normal interrupt instead of - * NMI and the hardlockup detector would be broken. - */ - return arm_pmu_irq_is_nmi(); -} - -static int watchdog_perf_update_period(void *data) -{ - int cpu =3D smp_processor_id(); - u64 max_cpu_freq, new_period; - - max_cpu_freq =3D cpufreq_get_hw_max_freq(cpu) * 1000UL; - if (!max_cpu_freq) - return 0; - - new_period =3D watchdog_thresh * max_cpu_freq; - hardlockup_detector_perf_adjust_period(new_period); - - return 0; -} - -static int watchdog_freq_notifier_callback(struct notifier_block *nb, - unsigned long val, void *data) -{ - struct cpufreq_policy *policy =3D data; - int cpu; - - if (val !=3D CPUFREQ_CREATE_POLICY) - return NOTIFY_DONE; - - /* - * Let each online CPU related to the policy update the period by their - * own. This will serialize with the framework on start/stop the lockup - * detector (softlockup_{start,stop}_all) and avoid potential race - * condition. Otherwise we may have below theoretical race condition: - * (core 0/1 share the same policy) - * [core 0] [core 1] - * hardlockup_detector_event_create() - * hw_nmi_get_sample_period() - * (cpufreq registered, notifier callback invoked) - * watchdog_freq_notifier_callback() - * watchdog_perf_update_period() - * (since core 1's event's not yet created, - * the period is not set) - * perf_event_create_kernel_counter() - * (event's period is SAFE_MAX_CPU_FREQ) - */ - for_each_cpu(cpu, policy->cpus) - smp_call_on_cpu(cpu, watchdog_perf_update_period, NULL, false); - - return NOTIFY_DONE; -} - -static struct notifier_block watchdog_freq_notifier =3D { - .notifier_call =3D watchdog_freq_notifier_callback, -}; - -static int __init init_watchdog_freq_notifier(void) -{ - return cpufreq_register_notifier(&watchdog_freq_notifier, - CPUFREQ_POLICY_NOTIFIER); -} -core_initcall(init_watchdog_freq_notifier); diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 973a027d90639..294a5c3438ad1 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -703,10 +704,17 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, in= t cpu) return per_cpu(hw_events->irq, cpu); } =20 -bool arm_pmu_irq_is_nmi(void) +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +bool arch_perf_nmi_is_available(void) { + /* + * watchdog_hardlockup_probe() will success even if Pseudo-NMI turns off, + * however, the pmu interrupts will act like a normal interrupt instead of + * NMI and the hardlockup detector would be broken. + */ return has_nmi; } +#endif =20 /* * PMU hardware loses all context when a CPU goes offline. diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 52b37f7bdbf9e..8f06751f1e176 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -183,8 +183,6 @@ void kvm_host_pmu_init(struct arm_pmu *pmu); #define kvm_host_pmu_init(x) do { } while(0) #endif =20 -bool arm_pmu_irq_is_nmi(void); - /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); void armpmu_free(struct arm_pmu *pmu); diff --git a/kernel/watchdog_perf.c b/kernel/watchdog_perf.c index d3ca70e3c256a..8aa5e9a0ba20a 100644 --- a/kernel/watchdog_perf.c +++ b/kernel/watchdog_perf.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include =20 @@ -306,3 +307,85 @@ void __init hardlockup_config_perf_event(const char *s= tr) wd_hw_attr.type =3D PERF_TYPE_RAW; wd_hw_attr.config =3D config; } + +#ifdef CONFIG_WATCHDOG_PERF_ADJUST_PERIOD +/* + * Safe maximum CPU frequency in case a particular platform doesn't implem= ent + * cpufreq driver. Although, architecture doesn't put any restrictions on + * maximum frequency but 5 GHz seems to be safe maximum given the available + * CPUs in the market which are clocked much less than 5 GHz. On the other + * hand, we can't make it much higher as it would lead to a large hard-loc= kup + * detection timeout on parts which are running slower (eg. 1GHz on + * Developerbox) and doesn't possess a cpufreq driver. + */ +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz +u64 hw_nmi_get_sample_period(int watchdog_thresh) +{ + unsigned int cpu =3D smp_processor_id(); + unsigned long max_cpu_freq; + + max_cpu_freq =3D cpufreq_get_hw_max_freq(cpu) * 1000UL; + if (!max_cpu_freq) + max_cpu_freq =3D SAFE_MAX_CPU_FREQ; + + return (u64)max_cpu_freq * watchdog_thresh; +} + +static int watchdog_perf_update_period(void *data) +{ + int cpu =3D smp_processor_id(); + u64 max_cpu_freq, new_period; + + max_cpu_freq =3D cpufreq_get_hw_max_freq(cpu) * 1000UL; + if (!max_cpu_freq) + return 0; + + new_period =3D watchdog_thresh * max_cpu_freq; + hardlockup_detector_perf_adjust_period(new_period); + + return 0; +} + +static int watchdog_freq_notifier_callback(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct cpufreq_policy *policy =3D data; + int cpu; + + if (val !=3D CPUFREQ_CREATE_POLICY) + return NOTIFY_DONE; + + /* + * Let each online CPU related to the policy update the period by their + * own. This will serialize with the framework on start/stop the lockup + * detector (softlockup_{start,stop}_all) and avoid potential race + * condition. Otherwise we may have below theoretical race condition: + * (core 0/1 share the same policy) + * [core 0] [core 1] + * hardlockup_detector_event_create() + * hw_nmi_get_sample_period() + * (cpufreq registered, notifier callback invoked) + * watchdog_freq_notifier_callback() + * watchdog_perf_update_period() + * (since core 1's event's not yet created, + * the period is not set) + * perf_event_create_kernel_counter() + * (event's period is SAFE_MAX_CPU_FREQ) + */ + for_each_cpu(cpu, policy->cpus) + smp_call_on_cpu(cpu, watchdog_perf_update_period, NULL, false); + + return NOTIFY_DONE; +} + +static struct notifier_block watchdog_freq_notifier =3D { + .notifier_call =3D watchdog_freq_notifier_callback, +}; + +static int __init init_watchdog_freq_notifier(void) +{ + return cpufreq_register_notifier(&watchdog_freq_notifier, + CPUFREQ_POLICY_NOTIFIER); +} +core_initcall(init_watchdog_freq_notifier); +#endif diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 2cbfa3dead0be..85fdfa9b52346 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1193,6 +1193,14 @@ config HARDLOCKUP_DETECTOR_PERF depends on !HAVE_HARDLOCKUP_DETECTOR_ARCH select HARDLOCKUP_DETECTOR_COUNTS_HRTIMER =20 +config WATCHDOG_PERF_ADJUST_PERIOD + bool + help + Adjust the watchdog hardlockup detector's period based on CPU max + frequency. Uses cpufreq if available; falls back to a safe 5 GHz + default otherwise. Registers a cpufreq notifier to update the period + automatically. + config HARDLOCKUP_DETECTOR_BUDDY bool depends on HARDLOCKUP_DETECTOR --=20 2.39.5 From nobody Tue Nov 11 11:34:13 2025 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C826332ECC for ; Tue, 11 Nov 2025 07:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762846541; cv=none; b=P+6HOzpfE26MapOUOiFGGdL18TSTiNN7Lwj3TJ5MOTPSDj7+XdCvAdxhz2szNPzEppLoR4XwpdIbwx64eR0ccA5xtx6TTKpaUlhWGHW1XWSAaXid31yrPAKbBRL8VxmpBqTsVP6IsZFNZmPMO9jz5+aGDTIxyzenDtUTD8d4YJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762846541; c=relaxed/simple; bh=TXw2u5rDDypAuPP/PEkhaT2sUClVbxjCMBkI2ULXV/E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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Mon, 10 Nov 2025 23:35:38 -0800 (PST) From: Yunhui Cui To: akpm@linux-foundation.org, alex@ghiti.fr, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, catalin.marinas@arm.com, cuiyunhui@bytedance.com, dianders@chromium.org, johannes@sipsolutions.net, lihuafei1@huawei.com, mark.rutland@arm.com, masahiroy@kernel.org, maz@kernel.org, mingo@kernel.org, nicolas.schier@linux.dev, palmer@dabbelt.com, paul.walmsley@sifive.com, suzuki.poulose@arm.com, thorsten.blum@linux.dev, wangjinchao600@gmail.com, will@kernel.org, yangyicong@hisilicon.com, zhanjie9@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley Subject: [PATCH v5 2/2] riscv: add HARDLOCKUP_DETECTOR_PERF support Date: Tue, 11 Nov 2025 15:34:59 +0800 Message-Id: <20251111073459.44030-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251111073459.44030-1-cuiyunhui@bytedance.com> References: <20251111073459.44030-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the HARDLOCKUP_DETECTOR_PERF function based on RISC-V SSE. Signed-off-by: Yunhui Cui Reviewed-by: Douglas Anderson Acked-by: Paul Walmsley --- arch/riscv/Kconfig | 3 +++ drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fadec20b87a8e..74835cdc89ddf 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -186,6 +186,9 @@ config RISCV select HAVE_PAGE_SIZE_4KB select HAVE_PCI select HAVE_PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if RISCV_PMU_SBI_SSE + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_N= MI + select WATCHDOG_PERF_ADJUST_PERIOD if HARDLOCKUP_DETECTOR_PERF && CPU_FREQ select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_POSIX_CPU_TIMERS_TASK_WORK diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index c852f64a50221..0c7c5924687c9 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -1192,6 +1193,13 @@ static int pmu_sbi_setup_sse(struct riscv_pmu *pmu) } #endif =20 +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +bool arch_perf_nmi_is_available(void) +{ + return IS_ENABLED(CONFIG_RISCV_PMU_SBI_SSE); +} +#endif + static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu =3D hlist_entry_safe(node, struct riscv_pmu, node); @@ -1618,6 +1626,8 @@ static int __init pmu_sbi_devinit(void) /* Notify legacy implementation that SBI pmu is available*/ riscv_pmu_legacy_skip_init(); =20 + lockup_detector_retry_init(); + return ret; } device_initcall(pmu_sbi_devinit) --=20 2.39.5