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Signed-off-by: Jack Hsu Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 718d732174b9..cb0eda4e87ac 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -389,6 +389,10 @@ properties: - enum: - mediatek,mt8188-evb - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8189-evb + - const: mediatek,mt8189 - description: Google Hayato items: - const: google,hayato-rev1 --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEC4B34DB6B; Tue, 11 Nov 2025 07:02:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N add compatible string for mt8189 dts node of disp-pwm Signed-off-by: Jack Hsu Acked-by: Uwe Kleine-K=C3=B6nig Acked-by: Conor Dooley --- Changs in v7: - update dt-bindings commit msg (use "mt8189" instead of "mt8189 evb board") --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b= /Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 68ef30414325..22712769518b 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt6893-disp-pwm - mediatek,mt8186-disp-pwm - mediatek,mt8188-disp-pwm + - mediatek,mt8189-disp-pwm - mediatek,mt8192-disp-pwm - mediatek,mt8195-disp-pwm - mediatek,mt8365-disp-pwm --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1CD234D92F; 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charset="utf-8" add compatible string for mt8189 dts node of uart Signed-off-by: Jack Hsu Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- Changs in v7: - update dt-bindings commit msg (use "mt8189" instead of "mt8189 evb board") --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/= Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 5bd8a8853ae0..3f0f4aea0a4c 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -47,6 +47,7 @@ properties: - mediatek,mt8183-uart - mediatek,mt8186-uart - mediatek,mt8188-uart + - mediatek,mt8189-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8365-uart --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EACB34EEF3; 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charset="utf-8" add compatible string for mt8189 dts node of timer Signed-off-by: Jack Hsu Acked-by: Conor Dooley --- Changs in v7: - update dt-bindings commit msg (use "mt8189" instead of "mt8189 evb board") =20 --- Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/= Documentation/devicetree/bindings/timer/mediatek,timer.yaml index 337580dc77d8..8e705fe58dc5 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml +++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml @@ -44,6 +44,7 @@ properties: - mediatek,mt8183-timer - mediatek,mt8186-timer - mediatek,mt8188-timer + - mediatek,mt8189-timer - mediatek,mt8192-timer - mediatek,mt8195-timer - mediatek,mt8196-timer --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 771C934DB7C; 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charset="utf-8" modify dt-binding for support mt8189 dts node of xhci Signed-off-by: Jack Hsu --- Changs in v7: - drop "reset-names" property - update dt-bindings commit msg (use "mt8189" instead of "mt8189 evb board") =20 --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b= /Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 004d3ebec091..231e6f35a986 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8183-xhci - mediatek,mt8186-xhci - mediatek,mt8188-xhci + - mediatek,mt8189-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci - mediatek,mt8365-xhci @@ -168,7 +169,8 @@ properties: 104 - used by mt8195, IP1, specific 1.04; 105 - used by mt8195, IP2, specific 1.05; 106 - used by mt8195, IP3, specific 1.06; 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Tue, 11 Nov 2025 15:02:32 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 11 Nov 2025 15:02:30 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 11 Nov 2025 15:02:30 +0800 From: Jack Hsu To: , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , Jack Hsu , Conor Dooley Subject: [PATCH v7 6/9] dt-bindings: watchdog: Support MediaTek MT8189 wdt Date: Tue, 11 Nov 2025 14:59:20 +0800 Message-ID: <20251111070031.305281-7-jh.hsu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251111070031.305281-1-jh.hsu@mediatek.com> References: <20251111070031.305281-1-jh.hsu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" modify dt-binding for support mt8189 dts node of wdt Signed-off-by: Jack Hsu Acked-by: Conor Dooley Acked-by: Guenter Roeck --- Changs in v7: - update dt-bindings commit msg (use "mt8189" instead of "mt8189 evb board") --- Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.ya= ml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index ba0bfd73ab62..a05f8155b738 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -41,6 +41,7 @@ properties: - mediatek,mt7623-wdt - mediatek,mt7629-wdt - mediatek,mt8173-wdt + - mediatek,mt8188-wdt - mediatek,mt8365-wdt - mediatek,mt8516-wdt - const: mediatek,mt6589-wdt --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EFE034EEF6; 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charset="utf-8" Add support for MediaTek MT6319 PMIC IC Signed-off-by: Jack Hsu --- Changs in v7: - change pmic node name as "pmic@" --- arch/arm64/boot/dts/mediatek/mt6319.dtsi | 66 ++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6319.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6319.dtsi b/arch/arm64/boot/dts= /mediatek/mt6319.dtsi new file mode 100644 index 000000000000..6586f0ba5b2f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6319.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + */ +#include + +&spmi { + mt6319_7: pmic@7 { + compatible =3D "mediatek,mt6315-regulator"; + buck1-modeset-mask =3D <0x3>; + reg =3D <0x7 SPMI_USID>; + + regulators { + mt6319_7_vbuck1: vbuck1 { + regulator-name =3D "vbuck1"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + mt6319_7_vbuck2: vbuck2 { + regulator-name =3D "vbuck2"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + mt6319_7_vbuck3: vbuck3 { + regulator-name =3D "vbuck3"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + mt6319_7_vbuck4: vbuck4 { + regulator-name =3D "vbuck4"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6319_8: pmic@8 { + compatible =3D "mediatek,mt6315-regulator"; + buck1-modeset-mask =3D <0xb>; + reg =3D <0x8 SPMI_USID>; + + regulators { + mt6319_8_vbuck1: vbuck1 { + regulator-name =3D "vbuck1"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + mt6319_8_vbuck2: vbuck2 { + regulator-name =3D "vbuck2"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + mt6319_8_vbuck3: vbuck3 { + regulator-name =3D "vbuck3"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + mt6319_8_vbuck4: vbuck4 { + regulator-name =3D "vbuck4"; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D8E534DB53; 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charset="utf-8" Update properties of rtc for mt6359 PMIC Signed-off-by: Jack Hsu --- Changs in v7: - remove mt635x-auadc.h - remove fg nodes --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts= /mediatek/mt6359.dtsi index 467d8a4c2aa7..fe737254c091 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -302,6 +302,9 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { =20 mt6359rtc: rtc { compatible =3D "mediatek,mt6358-rtc"; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; }; }; }; --=20 2.45.2 From nobody Tue Nov 11 11:31:35 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C804034DCC4; Tue, 11 Nov 2025 07:02:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 11 Nov 2025 15:02:33 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 11 Nov 2025 15:02:31 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 11 Nov 2025 15:02:31 +0800 From: Jack Hsu To: , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , Jack Hsu Subject: [PATCH v7 9/9] arm64: dts: mediatek: Add mt8189 evaluation board dts Date: Tue, 11 Nov 2025 14:59:23 +0800 Message-ID: <20251111070031.305281-10-jh.hsu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251111070031.305281-1-jh.hsu@mediatek.com> References: <20251111070031.305281-1-jh.hsu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add MediaTek mt8189 evaluation board dts, dtsi, Mafefile. Signed-off-by: Jack Hsu --- Changs in v7: - update mt8189 clk node (refer to: https://lore.kernel.org/linux-mediatek/20251106124330.11456= 00-1-irving-ch.lin@mediatek.com/) - xhci node drop "reset-names" property - update mt8189 thermal node (refer to: https://lore.kernel.org/linux-mediatek/20251110094113.39651= 82-1-hanchien.lin@mediatek.com/) - Link to v6: https://lore.kernel.org/linux-mediatek/20251030134541.784011= -1-jh.hsu@mediatek.com/ --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 1082 ++++++ arch/arm64/boot/dts/mediatek/mt8189.dtsi | 3310 +++++++++++++++++++ 3 files changed, 4393 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index c5fd6191a925..188e479a6916 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -94,6 +94,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku4.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku6.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku7.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8189-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8189-evb.dts new file mode 100644 index 000000000000..2ed404829730 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts @@ -0,0 +1,1082 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sirius Wang + */ +/dts-v1/; +#include "mt8189.dtsi" +#include "mt8189-pinfunc.h" +#include "mt6319.dtsi" +#include "mt6359.dtsi" +#include + +/ { + model =3D "MediaTek MT8189 evaluation board"; + compatible =3D "mediatek,mt8189-evb", "mediatek,mt8189"; + + chosen: chosen { + stdout-path =3D "serial0:115200n8"; + }; + + usb_p0_vbus: regulator@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "p0_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 82 0>; + enable-active-high; + }; + + usb_p1_vbus: regulator@1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "p1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 84 0>; + enable-active-high; + }; + + usb_p2_vbus: regulator@2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "p2_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 85 0>; + enable-active-high; + }; + + usb_p3_vbus: regulator@3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "p3_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 86 0>; + enable-active-high; + }; + + usb_p4_vbus: regulator@4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "p4_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 87 0>; + enable-active-high; + }; +}; + +&afe{ + pinctrl-names =3D "aud-gpio-i2sin0-off", + "aud-gpio-i2sin0-on", + "aud-gpio-i2sout0-off", + "aud-gpio-i2sout0-on", + "aud-gpio-i2sin1-off", + "aud-gpio-i2sin1-on", + "aud-gpio-i2sout1-off", + "aud-gpio-i2sout1-on", + /*dmic*/ + "aud-gpio-ap-dmic-off", + "aud-gpio-ap-dmic-on", + "aud-gpio-ap-dmic1-off", + "aud-gpio-ap-dmic1-on", + /*pcm*/ + "aud-gpio-pcm-off", + "aud-gpio-pcm-on"; + + /* i2s */ + pinctrl-0 =3D <&aud_gpio_i2sin0_off>; + pinctrl-1 =3D <&aud_gpio_i2sin0_on>; + pinctrl-2 =3D <&aud_gpio_i2sout0_off>; + pinctrl-3 =3D <&aud_gpio_i2sout0_on>; + pinctrl-4 =3D <&aud_gpio_i2sin1_off>; + pinctrl-5 =3D <&aud_gpio_i2sin1_on>; + pinctrl-6 =3D <&aud_gpio_i2sout1_off>; + pinctrl-7 =3D <&aud_gpio_i2sout1_on>; + /* dmic */ + pinctrl-8 =3D <&aud_gpio_ap_dmic_off>; + pinctrl-9 =3D <&aud_gpio_ap_dmic_on>; + pinctrl-10 =3D <&aud_gpio_ap_dmic1_off>; + pinctrl-11 =3D <&aud_gpio_ap_dmic1_on>; + /* pcm */ + pinctrl-12 =3D <&aud_gpio_pcm_off>; + pinctrl-13 =3D <&aud_gpio_pcm_on>; + + status =3D "okay"; +}; + +&auxadc { + status =3D "okay"; +}; + +&cpuhvfs { + proc1-supply =3D <&mt6359_vmodem_buck_reg>; //L + proc2-supply =3D <&mt6319_7_vbuck1>; //B + proc3-supply =3D <&mt6359_vmodem_buck_reg>; //DSU +}; + +&disp_dvo0 { + status =3D "okay"; + + ports { + port { + disp_dvo0_out: endpoint { + remote-endpoint =3D <&edptx_in>; + }; + }; + }; +}; + +&disp_dvo1 { + status =3D "okay"; + + port { + disp1_dp_intf0_out: endpoint { + remote-endpoint =3D <&dptx_in0>; + }; + }; +}; + +&dp_tx { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dptx_pin>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dptx_in0: endpoint { + remote-endpoint =3D <&disp1_dp_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + dptx_out: endpoint { + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel1@0 { + compatible =3D "boe,tv101wum-nl6"; + reg =3D <0>; + reset-gpios =3D <&pio 25 GPIO_ACTIVE_HIGH>; + enable-gpios =3D <&pio 14 GPIO_ACTIVE_HIGH>; + gate-ic =3D <4831>; + pinctrl-names =3D "default"; + status =3D "okay"; + + port { + panel_in1: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + }; + + port { + dsi_out: endpoint { + remote-endpoint =3D <&panel_in1>; + }; + }; +}; + +&edp_tx { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_tx_hpd_pins>; + max-lane-count =3D <4>; + max-linkrate-mhz =3D <5400>; + use-aux-bus; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edptx_in: endpoint { + remote-endpoint =3D <&disp_dvo0_out>; + }; + }; + + port@1 { + reg =3D <1>; + edp_out: endpoint { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&edp_panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible =3D "edp-panel"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&panel_fixed_pins>; + + status =3D "okay"; + + port { + edp_panel_in: endpoint { + remote-endpoint =3D <&edp_out>; + }; + }; + }; + }; +}; + +&gpu { + supply-names =3D "mali"; + mali-supply =3D <&mt6359_vproc1_buck_reg>; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "disabled"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + status =3D "disabled"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + status =3D "disabled"; + + nau8825: audio-codec@1a { + compatible =3D "nuvoton,nau8825"; + reg =3D <0x1a>; + interrupts-extended =3D <&pio 4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_codec_pins>; + #sound-dai-cells =3D <0>; + + nuvoton,jkdet-enable; + nuvoton,jkdet-polarity =3D <1>; + nuvoton,vref-impedance =3D <2>; + nuvoton,micbias-voltage =3D <6>; + nuvoton,sar-threshold-num =3D <4>; + nuvoton,sar-threshold =3D <0xc 0x1e 0x38 0x60>; + nuvoton,sar-hysteresis =3D <1>; + nuvoton,sar-voltage =3D <0>; + nuvoton,sar-compare-time =3D <0>; + nuvoton,sar-sampling-time =3D <0>; + nuvoton,short-key-debounce =3D <2>; + nuvoton,jack-insert-debounce =3D <7>; + nuvoton,jack-eject-debounce =3D <7>; + nuvoton,adc-delay-ms =3D <300>; + status =3D "disabled"; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + status =3D "disabled"; +}; + +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + status =3D "disabled"; +}; + +&i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + status =3D "disabled"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + status =3D "disabled"; +}; + +&i2c7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_pins>; + status =3D "disabled"; +}; + +&i2c8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c8_pins>; + status =3D "disabled"; +}; + +&mipi_tx_config0 { + status =3D "okay"; +}; + +&mmc0 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_pins_default>; + pinctrl-1 =3D <&mmc0_pins_uhs>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + non-removable; + hs400-ds-delay =3D <0x1481b>; + mediatek,hs400-ds-dly3 =3D <0x14>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; +}; + +&mmc1 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_pins_default>; + pinctrl-1 =3D <&mmc1_pins_uhs>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + cd-gpios =3D <&pio 2 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <&mt6359_vpa_buck_reg>; + vqmmc-supply =3D <&mt6359_vsim1_ldo_reg>; +}; + +/delete-node/ &mt6319_7_vbuck2; +/delete-node/ &mt6319_8_vbuck2; +/delete-node/ &mt6319_8_vbuck4; + +&mt6359_vpa_buck_reg { + regulator-max-microvolt =3D <3000000>; +}; + +&mt6359_vmodem_buck_reg { + regulator-always-on; +}; + +&mt6359_vsram_proc2_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg{ + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg{ + regulator-always-on; +}; + +&mt6359_vaux18_ldo_reg{ + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg{ + regulator-always-on; +}; + +&mt6359_va09_ldo_reg{ + regulator-always-on; +}; + +&mt6359_vrfck_ldo_reg{ + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg{ + regulator-always-on; +}; + +&mt6359_vsram_proc1_ldo_reg{ + /delete-property/ regulator-always-on; +}; + + +&mt6359_vproc1_buck_reg { + regulator-name =3D "buck_vgpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <900000>; + regulator-coupled-with =3D <&mt6359_vsram_proc1_ldo_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vsram_proc1_ldo_reg { + regulator-name =3D "ldo_sram_gpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <900000>; + regulator-coupled-with =3D <&mt6359_vproc1_buck_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359rtc { + status =3D "okay"; +}; + +&nor_flash { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_pins>; + + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <52000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + }; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins_default>; + status =3D "okay"; +}; + +&pciephy { + status =3D "okay"; +}; + +&pio { + edp_tx_hpd_pins: edp-tx-hpd-pins{ + pins-hpd { + pinmux =3D ; + bias-pull-up; + }; + }; + + panel_fixed_pins: panel-fixed-pins { + pins1 { + pinmux =3D , + , + , + ; + bias-pull-up; + }; + }; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c4_pins: i2c4-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + i2c5_pins: i2c5-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c6_pins: i2c6-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + i2c8_pins: i2c8-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + + spi0_pins: spi0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + spi2_pins: spi2-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + spi3_pins: spi3-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + spi4_pins: spi4-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + spi5_pins: spi5-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + pcie_pins_default: pcie-default-pins { + pins-cmd-dat { + pinmux =3D , + , + ; + }; + }; + + nor_pins: nor-pins { + pins-ck-io { + pinmux =3D , + , + ; + drive-strength =3D <8>; + bias-pull-down; + }; + + pins-cs { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-up; + }; + }; + + dptx_pin: dptx-default-pins { + pins-cmd-dat { + pinmux =3D ; + }; + }; + + /* AUDIO GPIO standardization start */ + audio_spk_en_pins: audio-spk-en-pins { + pins-spk-en { + pinmux =3D ; + output-low; + }; + }; + + audio_codec_pins: audio-codec-pins { + pins-hp-int-odl { + pinmux =3D ; + input-enable; + bias-disable; + }; + }; + + aud_gpio_i2sin0_off: aud-gpio-i2sin0-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + + aud_gpio_i2sin0_on: aud-gpio-i2sin0-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_i2sout0_off: aud-gpio-i2sout0-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + + pins-cmd2-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + + pins-cmd3-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + + pins-cmd4-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + + aud_gpio_i2sout0_on: aud-gpio-i2sout0-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + + pins-cmd2-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + + pins-cmd3-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + + pins-cmd4-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_i2sin1_off: aud-gpio-i2sin1-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + + aud_gpio_i2sin1_on: aud-gpio-i2sin1-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_i2sout1_off: aud-gpio-i2sout1-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + + pins-cmd2-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + + pins-cmd3-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + + pins-cmd4-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + + aud_gpio_i2sout1_on: aud-gpio-i2sout1-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + + pins-cmd2-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + + pins-cmd3-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + + pins-cmd4-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_ap_dmic_off: aud-gpio-ap-dmic-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + pins-cmd2-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + aud_gpio_ap_dmic_on: aud-gpio-ap-dmic-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + pins-cmd2-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + aud_gpio_ap_dmic1_off: aud-gpio-ap-dmic1-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + pins-cmd2-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + aud_gpio_ap_dmic1_on: aud-gpio-ap-dmic1-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + pins-cmd2-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_pcm_off: aud-gpio-pcm-off-pins { + pins-cmd1-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + pins-cmd2-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + pins-cmd3-dat { + pinmux =3D ; + input-enable; + bias-pull-down; + }; + }; + + aud_gpio_pcm_on: aud-gpio-pcm-on-pins { + pins-cmd1-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + pins-cmd2-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + pins-cmd3-dat { + pinmux =3D ; + input-schmitt-enable; + bias-disable; + }; + }; + /* AUDIO GPIO standardization end */ + + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + pins-rst { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + pins-ds { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + pins-insert { + pinmux =3D ; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + }; +}; + +&pmic { + interrupts-extended =3D <&pio 194 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sound { + compatible =3D "mediatek,mt8189-nau8825"; + model =3D "mt8189_rt9123_8825"; + status =3D "okay"; + + dai-link-0 { + link-name =3D "I2SOUT0_BE"; + mediatek,clk-provider =3D "cpu"; + + codec { + sound-dai =3D <&nau8825>; + }; + }; + + dai-link-1 { + link-name =3D "I2SIN0_BE"; + mediatek,clk-provider =3D "cpu"; + + codec { + sound-dai =3D <&nau8825>; + }; + }; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + status =3D "disabled"; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + status =3D "disabled"; +}; + +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2_pins>; + status =3D "disabled"; +}; + +&spi3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi3_pins>; + status =3D "disabled"; +}; + +&spi4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi4_pins>; + status =3D "disabled"; +}; + +&spi5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi5_pins>; + status =3D "disabled"; +}; + +&mfg0 { + domain-supply =3D <&mt6359_vproc1_buck_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6359_vsram_proc1_ldo_reg>; +}; + +&uart0 { + status =3D "okay"; +}; + +&ufshci { + vcc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vccq-supply =3D <&mt6359_vio18_ldo_reg>; + vccq2-supply =3D <&mt6359_vufs_ldo_reg>; +}; + +&xhci0{ + vbus-supply =3D <&usb_p0_vbus>; + status =3D "okay"; +}; + +&xhci1{ + vbus-supply =3D <&usb_p1_vbus>; + status =3D "okay"; +}; + +&xhci2{ + vbus-supply =3D <&usb_p2_vbus>; + status =3D "okay"; +}; + +&xhci3{ + vbus-supply =3D <&usb_p3_vbus>; + status =3D "okay"; +}; + +&xhci4{ + vbus-supply =3D <&usb_p4_vbus>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts= /mediatek/mt8189.dtsi new file mode 100644 index 000000000000..2f2648f43f34 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi @@ -0,0 +1,3310 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mt8189-gce.h" + +/ { + compatible =3D "mediatek,mt8189"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + dvo0 =3D &disp_dvo0; + dvo1 =3D &disp_dvo1; + dsc0 =3D &disp_dsc_wrap0; + gce0 =3D &gce; + gce1 =3D &gce_m; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; + mutex0 =3D &disp_mutex0; + ovl0 =3D &disp_ovl0_4l; + ovl1 =3D &disp_ovl1_4l; + rdma0 =3D &disp_rdma0; + rdma1 =3D &disp_rdma1; + serial0 =3D &uart0; + }; + + clk32k: oscillator-clk32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32000>; + clock-output-names =3D "clk32k"; + }; + + clk13m: oscillator-clk13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <1>; + clock-div =3D <2>; + clock-output-names =3D "clk13m"; + }; + + clk26m: oscillator-clk26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk104m: oscillator-clk104m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <4>; + clock-div =3D <1>; + clock-output-names =3D "clk104m"; + }; + + ulposc: oscillator-ulposc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <520000000>; + clock-output-names =3D "ulposc"; + }; + + ulposc3: oscillator-ulposc3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "ulposc3"; + }; + + vowpll: oscillator-vowpll { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "vowpll"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <358>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <358>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <358>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <358>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <358>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <358>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x600>; + enable-method =3D "psci"; + clock-frequency =3D <3000000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b>, <&cpu_s2idle>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x700>; + enable-method =3D "psci"; + clock-frequency =3D <3000000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b>, <&cpu_s2idle>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + core4 { + cpu =3D <&cpu4>; + }; + core5 { + cpu =3D <&cpu5>; + }; + core6 { + cpu =3D <&cpu6>; + }; + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <25>; + exit-latency-us =3D <57>; + min-residency-us =3D <5700>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <35>; + exit-latency-us =3D <82>; + min-residency-us =3D <1890>; + }; + + cpu_s2idle: cpu-s2idle { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x020180ff>; + local-timer-stop; + entry-latency-us =3D <10000>; + exit-latency-us =3D <10000>; + min-residency-us =3D <4294967295>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + }; + }; + + firmware: firmware { + scmi: scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&tinysys_mbox 0>, <&tinysys_mbox 1>; + shmem =3D <&scmi_tx_shmem>, <&scmi_rx_shmem>; + mbox-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_tinysys: protocol@80 { + reg =3D <0x80>; + mediatek,scmi-mminfra =3D <5>; + }; + }; + }; + + memory: memory@40000000 { + device_type =3D "memory"; + /* This memory size is filled in by the bootloader */ + reg =3D <0 0x40000000 0 0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + /*TODO: add reserved memory node here*/ + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + afe_dma_mem_reserved: snd-dma-mem-region@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0x300000>; + no-map; + }; + }; + + timer: timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + wl_info: wl-info@c2bf090 { + compatible =3D "mediatek,wl-info"; + wl-support =3D <0>; + reg =3D <0 0x0c2bf090 0 0x10>, /*tcm sram base*/ + <0 0x0c2c2f10 0 0x1520>; /*tcm wl-base sram*/ + reg-names =3D "wl_sram_base", "wl_tbl_base"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + cpuhvfs: cpuhvfs@100a00 { + compatible =3D "mediatek,cpufreq-hybrid"; + reg =3D <0 0x00100a00 0 0xc00>, + <0 0x00108d68 0 0x1400>, + <0 0x0010a168 0 0x1800>, + <0 0x00103640 0 0xc0>; + reg-names =3D "USRAM", "CSRAM", "ESRAM", "FREQ_HW_STATE"; + + /* pll mcucfg */ + mcucfg-ver =3D <0>; + }; + + performance: performance-controller@108d68 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x00108d78 0 0x120>, + <0 0x00108e98 0 0x120>; + reg-names =3D "performance-domain0", + "performance-domain1"; + #performance-domain-cells =3D <1>; + }; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu6 &cpu7>; + }; + }; + }; + + dbgao_clk: syscon@d01a000 { + compatible =3D "mediatek,mt8189-dbg-ao", "syscon"; + reg =3D <0 0xd01a000 0 0x1000>; + #clock-cells =3D <1>; + }; + + soc_dbg_error_flag: soc-dbg-error-flag@d01a000 { + compatible =3D "mediatek, soc-dbg-error-flag"; + reg =3D <0 0x0d01a000 0 0x1000>; + interrupts =3D ; + interrupt-names =3D "dbg-error-flag"; + /* error flag mask description */ + mcu2sub-emi-m1-parity-mask =3D <0x1>; + mcu2sub-emi-m0-parity-mask =3D <0x2>; + mcu2emi-m1-parity-mask =3D <0x4>; + mcu2emi-m0-parity-mask =3D <0x8>; + mcu2infra-reg-parity-mask =3D <0x10>; + infra-l3-cache2mcu-parity-mask =3D <0x20>; + emi-parity-cen-mask =3D <0x40>; + emi-parity-sub-cen-mask =3D <0x80>; + emi-parity-chan1-mask =3D <0x100>; + emi-parity-chan2-mask =3D <0x200>; + emi-parity-chan3-mask =3D <0x400>; + emi-parity-chan4-mask =3D <0x800>; + dramc-error-flag-ch-a-mask =3D <0x1000>; + dramc-error-flag-ch-b-mask =3D <0x2000>; + dramc-error-flag-ch-c-mask =3D <0x4000>; + dramc-error-flag-ch-d-mask =3D <0x8000>; + ap-tracker-timeout-mask =3D <0x10000>; + infra-tracker-timeout-mask =3D <0x20000>; + infra-lastbus-timeout-mask =3D <0x1000000>; + peri-lastbus-timeout-mask =3D <0x2000000>; + dram-md32-wdt-event-ch-a-mask =3D <0x8000000>; + dram-md32-wdt-event-ch-b-mask =3D <0x10000000>; + dram-md32-wdt-event-ch-c-mask =3D <0x20000000>; + }; + + dem_clk: syscon@d0a0000 { + compatible =3D "mediatek,mt8189-dem", "syscon"; + reg =3D <0 0xd0a0000 0 0x1000>; + #clock-cells =3D <1>; + }; + + topckgen_clk: syscon@10000000 { + compatible =3D "mediatek,mt8189-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg_ao_clk: syscon@10001000 { + compatible =3D "mediatek,mt8189-infra-ao", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt8189-pinctrl"; + reg =3D <0 0x10005000 0 0x1000>, + <0 0x11b50000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11c60000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11ce0000 0 0x1000>, + <0 0x11de0000 0 0x1000>, + <0 0x11e60000 0 0x1000>, + <0 0x1c01e000 0 0x1000>, + <0 0x11f00000 0 0x1000>; + reg-names =3D "base", + "lm", + "rb0", + "rb1", + "bm0", + "bm1", + "bm2", + "lt0", + "lt1", + "rt", + "eint0", + "eint1", + "eint2", + "eint3", + "eint4"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 182>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + apmixedsys_clk: syscon@1000c000 { + compatible =3D "mediatek,mt8189-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + devapc_infra: devapc@10207000 { + compatible =3D "mediatek,mt8189-devapc"; + reg =3D <0 0x10207000 0 0x1000>, + <0 0x10030000 0 0x1000>; /* infra ao/pd */ + vio-idx-num =3D <105>; + interrupts =3D ;/* infra irq */ + }; + + emicen: emicen@10219000 { + compatible =3D "mediatek,mt8189-emicen"; + reg =3D <0 0x10219000 0 0x1000>; + mediatek,emi-reg =3D <&emichn>; + }; + + emichn: emichn@10235000 { + compatible =3D "mediatek,common-emichn"; + reg =3D <0 0x10235000 0 0x1000>, + <0 0x10245000 0 0x1000>; + }; + + emicfg_ao_mem_clk: syscon@10270000 { + compatible =3D "mediatek,mt8189-emicfg-ao-mem", "syscon"; + reg =3D <0 0x10270000 0 0x1000>; + }; + + devapc_infra1: devapc@10274000 { + compatible =3D "mediatek,mt8189-devapc"; + reg =3D <0 0x10274000 0 0x1000>, + <0 0x10034000 0 0x1000>; /* infra1 ao/pd */ + vio-idx-num =3D <132>; + interrupts =3D ;/* infra irq */ + }; + + lvts_ap: lvts@10315000 { + compatible =3D "mediatek,mt8189-lvts-ap"; + reg =3D <0 0x10315000 0 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + nvmem-cells =3D <&lvts_e_data1>, <&lvts_e_data2>; + nvmem-cell-names =3D "lvts-calib-data-1", "lvts-calib-data-2"; + }; + + lvts_mcu: lvts@10316000 { + compatible =3D "mediatek,mt8189-lvts-mcu"; + reg =3D <0 0x10316000 0 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + nvmem-cells =3D <&lvts_e_data1>, <&lvts_e_data2>; + nvmem-cell-names =3D "lvts-calib-data-1", "lvts-calib-data-2"; + }; + + infra_iommu_m4: iommu@10330000 { + compatible =3D "mediatek,mt8189-iommu-infra"; + reg =3D <0 0x10330000 0 0x1000>; + interrupts =3D ; + #iommu-cells =3D <1>; + }; + + infra_iommu_m7: iommu@1033a000 { + compatible =3D "mediatek,mt8189-iommu-infra"; + reg =3D <0 0x1033a000 0 0x1000>; + interrupts =3D ; + #iommu-cells =3D <1>; + }; + + uart0: serial@11001000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + afe: mt8189-afe-pcm@11050000 { + compatible =3D "mediatek,mt8189-afe-pcm"; + reg =3D <0 0x11050000 0 0x10000>; + interrupts =3D ; + power-domains =3D <&spm MT8189_POWER_DOMAIN_AUDIO>; + memory-region =3D <&afe_dma_mem_reserved>; + clocks =3D <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen_clk CLK_TOP_AUDIO_H_SEL>, + <&apmixedsys_clk CLK_APMIXED_APLL1>, + <&apmixedsys_clk CLK_APMIXED_APLL2>, + <&topckgen_clk CLK_TOP_APLL1_D4>, + <&topckgen_clk CLK_TOP_APLL2_D4>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SIN0>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SIN1>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SOUT0>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SOUT1>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_FMI2S>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, + <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_B>, + <&topckgen_clk CLK_TOP_AUD_1_SEL>, + <&topckgen_clk CLK_TOP_AUD_2_SEL>, + <&topckgen_clk CLK_TOP_APLL_I2SIN0_MCK_SEL>, + <&topckgen_clk CLK_TOP_APLL_I2SIN1_MCK_SEL>, + <&topckgen_clk CLK_TOP_APLL_I2SOUT0_MCK_SEL>, + <&topckgen_clk CLK_TOP_APLL_I2SOUT1_MCK_SEL>, + <&topckgen_clk CLK_TOP_APLL_FMI2S_MCK_SEL>, + <&topckgen_clk CLK_TOP_APLL_TDMOUT_MCK_SEL>, + <&clk26m>, + <&pericfg_ao_clk CLK_PERAO_AUDIO0>, + <&pericfg_ao_clk CLK_PERAO_AUDIO1>, + <&pericfg_ao_clk CLK_PERAO_AUDIO2>; + clock-names =3D "top_aud_intbus", + "top_aud_eng1", + "top_aud_eng2", + "top_aud_h", + "apll1", + "apll2", + "apll1_d4", + "apll2_d4", + "apll12_div_i2sin0", + "apll12_div_i2sin1", + "apll12_div_i2sout0", + "apll12_div_i2sout1", + "apll12_div_fmi2s", + "apll12_div_tdmout_m", + "apll12_div_tdmout_b", + "top_apll1", + "top_apll2", + "top_i2sin0", + "top_i2sin1", + "top_i2sout0", + "top_i2sout1", + "top_fmi2s", + "top_dptx", + "clk26m", + "aud_slv_ck_peri", + "aud_mst_ck_peri", + "aud_intbus_ck_peri"; + mediatek,apmixedsys =3D <&apmixedsys_clk>; + status =3D "disabled"; + }; + + sound: sound { + mediatek,platform =3D <&afe>; + status =3D "disabled"; + }; + + disp_pwm0: pwm@1100e000 { + compatible =3D "mediatek,mt8189-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_DISP_PWM0>, + <&topckgen_clk CLK_TOP_DISP_PWM_SEL>, + <&topckgen_clk CLK_TOP_OSC_D4>; + clock-names =3D "main", "mm", "pwm_src"; + interrupts =3D ; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + + spi0: spi@11010800 { + compatible =3D "mediatek,mt8189-spi"; + reg =3D <0 0x11010800 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen_clk CLK_TOP_SPI0_SEL>, + <&pericfg_ao_clk CLK_PERAO_SPI0_B>, + <&pericfg_ao_clk CLK_PERAO_SPI0_H>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pad-select =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@11011800 { + compatible =3D "mediatek,mt8189-spi"; + reg =3D <0 0x11011800 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen_clk CLK_TOP_SPI1_SEL>, + <&pericfg_ao_clk CLK_PERAO_SPI1_B>, + <&pericfg_ao_clk CLK_PERAO_SPI1_H>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pad-select =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@11012800 { + compatible =3D "mediatek,mt8189-spi"; + reg =3D <0 0x11012800 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen_clk CLK_TOP_SPI2_SEL>, + <&pericfg_ao_clk CLK_PERAO_SPI2_B>, + <&pericfg_ao_clk CLK_PERAO_SPI2_H>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pad-select =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@11013800 { + compatible =3D "mediatek,mt8189-spi"; + reg =3D <0 0x11013800 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen_clk CLK_TOP_SPI3_SEL>, + <&pericfg_ao_clk CLK_PERAO_SPI3_B>, + <&pericfg_ao_clk CLK_PERAO_SPI3_H>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pad-select =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@11014800 { + compatible =3D "mediatek,mt8189-spi"; + reg =3D <0 0x11014800 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen_clk CLK_TOP_SPI4_SEL>, + <&pericfg_ao_clk CLK_PERAO_SPI4_B>, + <&pericfg_ao_clk CLK_PERAO_SPI4_H>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pad-select =3D <0>; + status =3D "disabled"; + }; + + spi5: spi@11015800 { + compatible =3D "mediatek,mt8189-spi"; + reg =3D <0 0x11015800 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen_clk CLK_TOP_SPI5_SEL>, + <&pericfg_ao_clk CLK_PERAO_SPI5_B>, + <&pericfg_ao_clk CLK_PERAO_SPI5_H>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pad-select =3D <0>; + status =3D "disabled"; + }; + + nor_flash: spi@11018000 { + compatible =3D "mediatek,mt8189-nor","mediatek,mt8186-nor"; + reg =3D <0 0x11018000 0 0x1000>; + clocks =3D <&topckgen_clk CLK_TOP_SFLASH_SEL>, + <&pericfg_ao_clk CLK_PERAO_SFLASH>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_F>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_H>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_P>; + clock-names =3D "spi", "sf", "axi_f", "axi_h", "axi_p"; + assigned-clocks =3D <&topckgen_clk CLK_TOP_SFLASH_SEL>; + assigned-clock-parents =3D <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + auxadc: adc@11019000 { + compatible =3D "mediatek,mt8189-auxadc", "mediatek,mt8173-auxadc"; + reg =3D <0 0x11019000 0 0x1000>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_AUXADC_26M>; + clock-names =3D "main"; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + devapc_peri: devapc@11020000 { + compatible =3D "mediatek,mt8189-devapc"; + reg =3D <0 0x11020000 0 0x1000>, + <0 0x1103c000 0 0x1000>; /* peri ao/pd */ + vio-idx-num =3D <62>; + interrupts =3D ; /* peri irq */ + }; + + pericfg_ao_clk: syscon@11036000 { + compatible =3D "mediatek,mt8189-peri-ao", "syscon", "simple-mfd"; + reg =3D <0 0x11036000 0 0x1000>; + #clock-cells =3D <1>; + usb_rst: reset-controller { + compatible =3D "ti,syscon-reset"; + #reset-cells =3D <1>; + reset-duration-us =3D <100>; + ti,reset-bits =3D < + /* xhci mac reset */ + /* 22: xhci */ + 0x0 22 0x0 22 0 0 + (ASSERT_SET|ASSERT_CLEAR|STATUS_NONE) + >; + }; + }; + + afe_clk: syscon@11050000 { + compatible =3D "mediatek,mt8189-audiosys", "syscon"; + reg =3D <0 0x11050000 0 0x1000>; + #clock-cells =3D <1>; + }; + + xhci0: usb@11200000 { + compatible =3D "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 207 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "host","wakeup"; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_SSUSB0_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_FRMCNT>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells =3D <1>; + #size-cells =3D <0>; + resets =3D <&usb_rst 0>; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg_ao_clk 0x214 110>; + status =3D "disabled"; + }; + + xhci1: usb@11210000 { + compatible =3D "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11210000 0 0x1000>, + <0 0x11213e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 203 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "host","wakeup"; + phys =3D <&u2port1 PHY_TYPE_USB2>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_SSUSB1_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_FRMCNT>; + clock-names =3D "sys_ck", "ref_ck","mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_SSUSB>; + #address-cells =3D <1>; + #size-cells =3D <0>; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg_ao_clk 0x21c 110>; + status =3D "disabled"; + }; + + xhci2: usb@11220000 { + compatible =3D "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11220000 0 0x1000>, + <0 0x11223e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 193 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "host","wakeup"; + phys =3D <&u2port2 PHY_TYPE_USB2>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_SSUSB2_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_FRMCNT>; + clock-names =3D "sys_ck", "ref_ck","mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_SSUSB>; + #address-cells =3D <1>; + #size-cells =3D <0>; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg_ao_clk 0x27c 110>; + status =3D "disabled"; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8189-mmc"; + reg =3D <0 0x11230000 0 0x10000>, + <0 0x11e70000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_MSDC50_0_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC0_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC0>, + <&topckgen_clk CLK_TOP_MSDC50_0_HCLK_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC0_SLV_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC0_MST_F>, + <&topckgen_clk CLK_TOP_MSDC50_0_SEL>; + clock-names =3D "source", "hclk", "source_cg", "bus_clk", + "pclk_cg", "axi_cg", "crypto"; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8189-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11d80000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen_clk CLK_TOP_MSDC30_1_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC1_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC1>, + <&topckgen_clk CLK_TOP_MSDC30_1_HCLK_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC1_SLV_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC1_MST_F>; + clock-names =3D "source", "hclk", "source_cg", "bus_clk", + "pclk_cg", "axi_cg"; + status =3D "disabled"; + }; + + xhci3: usb@11260000 { + compatible =3D "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11260000 0 0x2e00>, + <0 0x11263e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "host","wakeup"; + phys =3D <&u2port3 PHY_TYPE_USB2>, + <&u3port3 PHY_TYPE_USB3>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_SSUSB3_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_FRMCNT>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_SSUSB>; + #address-cells =3D <1>; + #size-cells =3D <0>; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg_ao_clk 0x284 110>; + status =3D "disabled"; + }; + + xhci4: usb@11270000 { + compatible =3D "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11270000 0 0x1000>, + <0 0x11273e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "host","wakeup"; + phys =3D <&u2port4 PHY_TYPE_USB2>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_SSUSB4_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_FRMCNT>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells =3D <1>; + #size-cells =3D <0>; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg_ao_clk 0x28c 110>; + status =3D "disabled"; + }; + + ufshci: ufshci@112b0000 { + compatible =3D "mediatek,mt8183-ufshci"; + reg =3D <0 0x112b0000 0 0x2300>; + interrupts =3D ; + + clocks =3D <&topckgen_clk CLK_TOP_U_SEL>, + <&clk26m>, + <&topckgen_clk CLK_TOP_MSDCPLL_D2>, + <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>, + <&topckgen_clk CLK_TOP_U_MBIST_SEL>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_SYS>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_SAP_CFG>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_UFS>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_AES>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AHB>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AXI>; + + clock-names =3D "ufs_sel", + "ufs_sel_min_src", + "ufs_sel_max_src", + "ufs_fde", + "ufs_mbist", + "unipro_tx_sym", + "unipro_rx_sym0", + "unipro_rx_sym1", + "unipro_sys", + "unipro_phy_sap", + "phy_top_ahb_s_bus", + "ufshci_ufs", + "ufshci_aes", + "ufshci_ufs_ahb", + "ufshci_aes_axi"; + + freq-table-hz =3D <26000000 208000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + vcc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vccq-supply =3D <&mt6359_vio18_ldo_reg>; + vccq2-supply =3D <&mt6359_vufs_ldo_reg>; + + resets =3D <&ufscfgpdn_rst 0>, + <&ufscfgpdn_rst 1>, + <&ufscfgpdn_rst 2>; + + reset-names =3D "unipro_rst", + "crypto_rst", + "hci_rst"; + + mediatek,ufs-disable-mcq; + mediatek,ufs-rtff-mtcmos; + mediatek,ufs-broken-vcc; + + status =3D "disabled"; + }; + + ufscfg_ao_reg_clk: syscon@112b8000 { + compatible =3D "mediatek,mt8189-ufscfg-ao", "syscon", "simple-mfd"; + reg =3D <0 0x112b8000 0 0x1000>; + #clock-cells =3D <1>; + + ufscfgao_rst: reset-controller { + compatible =3D "ti,syscon-reset"; + #reset-cells =3D <1>; + + ti,reset-bits =3D < + /* ufs mphy reset */ + /* 8: mphy */ + 0x48 8 0x4c 8 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + + ufscfg_pdn_reg_clk: syscon@112bb000 { + compatible =3D "mediatek,mt8189-ufscfg-pdn", "syscon", "simple-mfd"; + reg =3D <0 0x112bb000 0 0x1000>; + #clock-cells =3D <1>; + + ufscfgpdn_rst: reset-controller { + compatible =3D "ti,syscon-reset"; + #reset-cells =3D <1>; + + ti,reset-bits =3D < + /* ufs ufschi/crypto/unipro reset */ + /* 0: unipro */ + 0x48 0 0x4c 0 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + /* 1: ufs-crypto */ + 0x48 1 0x4c 1 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + /* 2: ufshci */ + 0x48 2 0x4c 2 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + + pcie: pcie@112f0000 { + compatible =3D "mediatek,mt8189-pcie", + "mediatek,mt8192-pcie"; + reg =3D <0 0x112f0000 0 0x4000>; + device_type =3D "pci"; + reg-names =3D "pcie-mac"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x30000000 + 0x0 0x30000000 0 0x04000000>; + + clocks =3D <&pericfg_ao_clk CLK_PERAO_AXI>, + <&pericfg_ao_clk CLK_PERAO_AHB_APB>, + <&pericfg_ao_clk CLK_PERAO_TL>, + <&pericfg_ao_clk CLK_PERAO_REF>, + <&topckgen_clk CLK_TOP_F26M_CK_EN>; + + phys =3D <&pcieport PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_PCIE>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + status =3D "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + u3phy3: t-phy@11b00000 { + compatible =3D "mediatek,mt8189-tphy", + "mediatek,generic-tphy-v2"; + reg =3D <0 0x11b00000 0 0x700>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + u2port3: usb-phy@11b00000 { + reg =3D <0 0x11b00000 0 0x700>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + + u3port3: usb-phy@11b00700 { + reg =3D <0 0x11b00700 0 0x700>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + u2phy4: xs-phy@11b10000 { + compatible =3D "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + u2port4: usb-phy@11b10000 { + reg =3D <0 0x11b10000 0 0x700>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P4_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + i2c2: i2c@11b20000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11b20000 0 0x1000>, + <0 0x11300400 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_ws_clk CLK_IMPWS_I2C2>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_ws_clk: syscon@11b21e00 { + compatible =3D "mediatek,mt8189-iic-wrap-ws", "syscon"; + reg =3D <0 0x11b21e00 0 0x10>; + #clock-cells =3D <1>; + }; + + mipi_tx_config0: mipi-tx-config@11b40000 { + compatible =3D "mediatek,mt8189-mipi-tx"; + reg =3D <0 0x11b40000 0 0x1000>; + clocks =3D <&clk26m>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + dispsys-sel-offset =3D <0x170 0x174>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@11b60000 { + compatible =3D "mediatek,mt8189-dp-tx"; + reg =3D <0 0x11b60000 0 0x5000>, + <0 0x11c10000 0 0x1500>, + <0 0x10011018 0 0x4>, + <0 0x1c001e80 0 0x4>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_DP_TX>, + <&spm MT8189_POWER_DOMAIN_SSUSB>; + power-domain-names =3D "pd_dp_tx", "pd_dp_phy"; + interrupts =3D ; + #phy-cells =3D <0>; + clocks =3D <&topckgen_clk CLK_TOP_DP_SEL>, + <&clk26m>; + clock-names =3D "mux_dp", "ck_26m"; + }; + + edp_tx: edp-tx@11b70000 { + compatible =3D "mediatek,mt8189-edp-tx"; + reg =3D <0 0x11b70000 0 0x14000>, + <0 0x11e10000 0 0x1500>; + interrupts =3D ; + power-domains =3D <&spm MT8189_POWER_DOMAIN_EDP_TX_DORMANT>; + clocks =3D <&topckgen_clk CLK_TOP_EDP_SEL>; + clock-names =3D "power"; + }; + + i2c0: i2c@11c20000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11c20000 0 0x1000>, + <0 0x11300200 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_e_clk CLK_IMPE_I2C0>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@11c21000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11c21000 0 0x1000>, + <0 0x11300300 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_e_clk CLK_IMPE_I2C1>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_e_clk: syscon@11c22e00 { + compatible =3D "mediatek,mt8189-iic-wrap-e", "syscon"; + reg =3D <0 0x11c22e00 0 0x10>; + #clock-cells =3D <1>; + }; + + i2c3: i2c@11d70000 { + compatible =3D "mediatek,mt8188-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11d70000 0 0x1000>, + <0 0x11300500 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_s_clk CLK_IMPS_I2C3>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + status =3D "disabled"; + }; + + i2c4: i2c@11d71000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11d71000 0 0x1000>, + <0 0x11300600 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_s_clk CLK_IMPS_I2C4>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@11d72000 { + compatible =3D "mediatek,mt8188-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11d72000 0 0x1000>, + <0 0x11300700 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_s_clk CLK_IMPS_I2C5>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + status =3D "disabled"; + }; + + i2c6: i2c@11d73000 { + compatible =3D "mediatek,mt8188-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11d73000 0 0x1000>, + <0 0x11300800 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_s_clk CLK_IMPS_I2C6>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + status =3D "disabled"; + }; + + imp_iic_wrap_s_clk: syscon@11d74e00 { + compatible =3D "mediatek,mt8189-iic-wrap-s", "syscon"; + reg =3D <0 0x11d74e00 0 0x10>; + #clock-cells =3D <1>; + }; + + pciephy: t-phy@11e50700 { + compatible =3D "mediatek,mt8189-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11e50700 0x700>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_PCIE_PHY>; + status =3D "disabled"; + + pcieport: pcie-phy@0 { + reg =3D <0 0x700>; + #phy-cells =3D <1>; + }; + }; + + u3phy0: xs-phy@11e80000 { + compatible =3D "mediatek,mt8189-xsphy", "mediatek,xsphy"; + reg =3D <0 0x11e83000 0 0x200>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + u2port0: usb-phy@11e80000 { + reg =3D <0 0x11e80000 0 0x700>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + + u3port0: usb-phy@11e83000 { + reg =3D <0 0x11e83400 0 0x500>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + u2phy1: xs-phy@11e90000 { + compatible =3D "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + u2port1: usb-phy@11e90000 { + reg =3D <0 0x11e90000 0 0x700>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P1_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + u2phy2: xs-phy@11ef0000 { + compatible =3D "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + u2port2: usb-phy@11ef0000 { + reg =3D <0 0x11ef0000 0 0x700>; + clocks =3D <&topckgen_clk CLK_TOP_USB2_PHY_RF_P2_EN>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + efuse: efuse@11f10000 { + compatible =3D "mediatek,mt8189-efuse", "mediatek,efuse"; + reg =3D <0 0x11f10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_e_data1: data1@1a4 { + reg =3D <0x1a4 0x54>; + }; + + lvts_e_data2: data2@1f8 { + reg =3D <0x1f8 0x8>; + }; + + gpu_avs0: gpu-avs0@308 { + reg =3D <0x308 0x4>; + }; + + gpu_avs1: gpu-avs1@30c { + reg =3D <0x30c 0x4>; + }; + + gpu_avs2: gpu-avs2@310 { + reg =3D <0x310 0x4>; + }; + + socinfo-data1@7a0 { + reg =3D <0x7a0 0x4>; + }; + + socinfo-data2@7e0 { + reg =3D <0x7e0 0x4>; + }; + }; + + i2c7: i2c@11f30000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11f30000 0 0x1000>, + <0 0x11300900 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_en_clk CLK_IMPEN_I2C7>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@11f31000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11f31000 0 0x1000>, + <0 0x11300a00 0 0x80>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap_en_clk CLK_IMPEN_I2C8>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_en_clk: syscon@11f32e00 { + compatible =3D "mediatek,mt8189-iic-wrap-en", "syscon"; + reg =3D <0 0x11f32e00 0 0x10>; + #clock-cells =3D <1>; + }; + + gpu: gpu@13000000 { + compatible =3D "mediatek,mt8189-mali", + "arm,mali-valhall-jm"; + reg =3D <0 0x13000000 0 0x4000>; + + nvmem-cells =3D <&gpu_avs0>, <&gpu_avs1>, <&gpu_avs2>; + nvmem-cell-names =3D "avs-bin-0", "avs-bin-1", "avs-bin-2"; + + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + + operating-points-v2 =3D <&gpu_opp_table>; + + clocks =3D <&mfg_clk CLK_MFG_BG3D>; + + power-domains =3D <&spm MT8189_POWER_DOMAIN_MFG2>, + <&spm MT8189_POWER_DOMAIN_MFG3>; + power-domain-names =3D "core0", "core1"; + + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <1427>; + + power-model@0 { + compatible =3D "arm,mali-simple-power-model"; + dynamic-coefficient =3D <1427>; + static-coefficient =3D <118279>; + thermal-zone =3D "gpu1-thermal"; + ts =3D <6 (-238) 20283 32499>; + }; + power-model@1 { + compatible =3D "arm,mali-tnax-power-model"; + scale =3D <5>; + }; + }; + + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-390000000 { + opp-hz =3D /bits/ 64 <390000000>; + opp-microvolt =3D <675000>; + }; + + opp-424000000 { + opp-hz =3D /bits/ 64 <424000000>; + opp-microvolt =3D <681250>; + }; + + opp-458000000 { + opp-hz =3D /bits/ 64 <458000000>; + opp-microvolt =3D <681250>; + }; + + opp-492000000 { + opp-hz =3D /bits/ 64 <492000000>; + opp-microvolt =3D <687500>; + }; + + opp-526000000 { + opp-hz =3D /bits/ 64 <526000000>; + opp-microvolt =3D <687500>; + }; + + opp-560000000 { + opp-hz =3D /bits/ 64 <560000000>; + opp-microvolt =3D <693750>; + }; + + opp-595000000 { + opp-hz =3D /bits/ 64 <595000000>; + opp-microvolt =3D <693750>; + }; + + opp-630000000 { + opp-hz =3D /bits/ 64 <630000000>; + opp-microvolt =3D <700000>; + }; + + opp-665000000 { + opp-hz =3D /bits/ 64 <665000000>; + opp-microvolt =3D <700000>; + }; + + opp-700000000 { + opp-hz =3D /bits/ 64 <700000000>; + opp-microvolt =3D <700000>; + }; + + opp-736000000 { + opp-hz =3D /bits/ 64 <736000000>; + opp-microvolt =3D <718750>; + }; + + opp-772000000 { + opp-hz =3D /bits/ 64 <772000000>; + opp-microvolt =3D <737500>; + }; + + opp-808000000 { + opp-hz =3D /bits/ 64 <808000000>; + opp-microvolt =3D <756250>; + }; + + opp-844000000 { + opp-hz =3D /bits/ 64 <844000000>; + opp-microvolt =3D <775000>; + }; + + opp-880000000 { + opp-hz =3D /bits/ 64 <880000000>; + opp-microvolt =3D <793750>; + }; + + opp-935000000 { + opp-hz =3D /bits/ 64 <935000000>; + opp-microvolt =3D <818750>; + }; + + opp-990000000 { + opp-hz =3D /bits/ 64 <990000000>; + opp-microvolt =3D <850000>; + }; + + opp-1045000000 { + opp-hz =3D /bits/ 64 <1045000000>; + opp-microvolt =3D <875000>; + }; + + opp-1100000000 { + opp-hz =3D /bits/ 64 <1100000000>; + opp-microvolt =3D <900000>; + }; + }; + + mfg_clk: syscon@13fbf000 { + compatible =3D "mediatek,mt8189-mfgcfg", "syscon"; + reg =3D <0 0x13fbf000 0 0x1000>; + #clock-cells =3D <1>; + }; + + dispsys_config: syscon@14000000 { + compatible =3D "mediatek,mt8189-mmsys", "syscon"; + reg =3D <0 0x14000000 0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #clock-cells =3D <1>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_DISP>; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_MUTEX0>, + <&dispsys_config_clk CLK_MM_DIPSYS_CONFIG>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + dispsys_config_clk: syscon@14000100 { + compatible =3D "mediatek,mt8189-dispsys", "syscon"; + reg =3D <0 0x14000100 0 0x20>; + #clock-cells =3D <1>; + }; + + disp_mutex0: mutex@14001000 { + compatible =3D "mediatek,mt8189-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_MUTEX0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + }; + + disp_ovl0_4l: ovl@14002000 { + compatible =3D "mediatek,mt8189-disp-ovl"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D ; + iommus =3D <&mm_iommu M4U_L0_P1_DISP_OVL0_4L_RDMA0>, + <&mm_iommu M4U_L1_P2_DISP_OVL0_4L_RDMA1>, + <&mm_iommu M4U_L0_P3_DISP_OVL0_4L_RDMA2>, + <&mm_iommu M4U_L1_P4_DISP_OVL0_4L_RDMA3>, + <&mm_iommu M4U_L0_P0_DISP_OVL0_4L_HDR>; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_OVL0_4L>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x2000 0x1000>; + }; + + disp_ovl1_4l: ovl@14003000 { + compatible =3D "mediatek,mt8189-disp-ovl"; + reg =3D <0 0x14003000 0 0x1000>; + interrupts =3D ; + iommus =3D <&mm_iommu M4U_L1_P1_DISP_OVL1_4L_RDMA0>, + <&mm_iommu M4U_L0_P2_DISP_OVL1_4L_RDMA1>, + <&mm_iommu M4U_L1_P3_DISP_OVL1_4L_RDMA2>, + <&mm_iommu M4U_L0_P4_DISP_OVL1_4L_RDMA3>, + <&mm_iommu M4U_L1_P0_DISP_OVL1_4L_HDR>; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_OVL1_4L>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + }; + + disp_rdma0: rdma@14006000 { + compatible =3D "mediatek,mt8189-disp-rdma"; + reg =3D <0 0x14006000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_RDMA0>; + iommus =3D <&mm_iommu M4U_L0_P5_DISP_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + disp_rdma1: rdma@14007000 { + compatible =3D "mediatek,mt8189-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_RDMA1>; + iommus =3D <&mm_iommu M4U_L1_P5_DISP_RDMA1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + disp_color0: color@14008000 { + compatible =3D "mediatek,mt8189-disp-color"; + reg =3D <0 0x14008000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + }; + + disp_color1: color@14009000 { + compatible =3D "mediatek,mt8189-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_COLOR1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + disp_ccorr0: ccorr@1400a000 { + compatible =3D "mediatek,mt8189-disp-ccorr"; + reg =3D <0 0x1400a000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + disp_ccorr1: ccorr@1400b000 { + compatible =3D "mediatek,mt8189-disp-ccorr"; + reg =3D <0 0x1400b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_CCORR1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + disp_ccorr2: ccorr@1400c000 { + compatible =3D "mediatek,mt8189-disp-ccorr"; + reg =3D <0 0x1400c000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_CCORR2>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + disp_ccorr3: ccorr@1400d000 { + compatible =3D "mediatek,mt8189-disp-ccorr"; + reg =3D <0 0x1400d000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_CCORR3>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + disp_aal0: aal@1400e000 { + compatible =3D "mediatek,mt8189-disp-aal"; + reg =3D <0 0x1400e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + disp_aal1: aal@1400f000 { + compatible =3D "mediatek,mt8189-disp-aal"; + reg =3D <0 0x1400f000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_AAL1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + }; + + disp_gamma0: gamma@14010000 { + compatible =3D "mediatek,mt8189-disp-gamma"; + reg =3D <0 0x14010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0 0x1000>; + }; + + disp_gamma1: gamma@14011000 { + compatible =3D "mediatek,mt8189-disp-gamma"; + reg =3D <0 0x14011000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_GAMMA1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + }; + + disp_dither0: dither@14012000 { + compatible =3D "mediatek,mt8189-disp-dither"; + reg =3D <0 0x14012000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + }; + + disp_dither1: dither@14013000 { + compatible =3D "mediatek,mt8189-disp-dither"; + reg =3D <0 0x14013000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_DITHER1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x3000 0x1000>; + }; + + disp_dsc_wrap0: dsc@14014000 { + compatible =3D "mediatek,mt8189-disp-dsc"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + disp_merge0: merge@14015000 { + compatible =3D "mediatek,mt8189-disp-merge"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_VPP_MERGE0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + + dsi0: dsi@14016000 { + compatible =3D "mediatek,mt8189-dsi"; + reg =3D <0 0x14016000 0 0x1000>; + interrupts =3D ; + phys =3D <&mipi_tx_config0>; + phy-names =3D "dphy"; + clocks =3D <&dispsys_config_clk CLK_MMSYS_0_DISP_DSI0>, + <&dispsys_config_clk CLK_MMSYS_1_DISP_DSI0>, + <&mipi_tx_config0>; + clock-names =3D "engine", "digital", "hs"; + status =3D "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + + disp_dvo0: dvo@14017000 { + compatible =3D "mediatek,mt8189-edp-dvo"; + reg =3D <0 0x14017000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MMSYS_1_DISP_DVO>, + <&topckgen_clk CLK_TOP_EDP_SEL>, + <&apmixedsys_clk CLK_APMIXED_TVDPLL2>, + <&clk26m>, + <&dispsys_config_clk CLK_MMSYS_0_DISP_DVO>; + clock-names =3D "engine", + "pixel", + "pll", + "dvo_clk", + "hf_fdvo_clk"; + status =3D "disabled"; + }; + + disp_dvo1: dvo@14018000 { + compatible =3D "mediatek,mt8189-dp-dvo"; + reg =3D <0 0x14018000 0 0x1000>; + interrupts =3D ; + clocks =3D <&dispsys_config_clk CLK_MM_DP_INTF>, + <&topckgen_clk CLK_TOP_DP_SEL>, + <&apmixedsys_clk CLK_APMIXED_TVDPLL1>, + <&clk26m>, + <&dispsys_config_clk CLK_MM_DP_INTF0>; + clock-names =3D "engine", + "pixel", + "pll", + "dvo_clk", + "hf_fdvo_clk"; + phys =3D <&dp_tx>; + phy-names =3D "dp_tx"; + }; + + smi_larb0: larb@1401c000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1401c000 0 0x1000>; + clocks =3D <&dispsys_config_clk CLK_MM_SMI_LARB>, + <&dispsys_config_clk CLK_MM_SMI_LARB>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_DISP>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_disp_common>; + }; + + smi_larb1: larb@1401d000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1401d000 0 0x1000>; + clocks =3D <&dispsys_config_clk CLK_MM_SMI_LARB>, + <&dispsys_config_clk CLK_MM_SMI_LARB>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_DISP>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_disp_common>; + }; + + imgsys1_clk: syscon@15020000 { + compatible =3D "mediatek,mt8189-imgsys1", "syscon"; + reg =3D <0 0x15020000 0 0x1000>; + #clock-cells =3D <1>; + }; + + smi_larb9: larb@1502e000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1502e000 0 0x1000>; + clocks =3D <&imgsys1_clk CLK_IMGSYS1_LARB9>, + <&imgsys1_clk CLK_IMGSYS1_LARB9>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_ISP_IMG1>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_img_2x1_sub_comm>; + }; + + smi_img_2x1_sub_comm: smi@1502f000 { + compatible =3D "mediatek,mt8189-smi-sub-common"; + reg =3D <0 0x1502f000 0 0x1000>; + clocks =3D <&imgsys1_clk CLK_IMGSYS1_LARB9>, + <&imgsys1_clk CLK_IMGSYS1_LARB11>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_ISP_IMG1>; + mediatek,smi =3D <&smi_disp_common>; + }; + + imgsys2_clk: syscon@15820000 { + compatible =3D "mediatek,mt8189-imgsys2", "syscon"; + reg =3D <0 0x15820000 0 0x1000>; + #clock-cells =3D <1>; + }; + + smi_larb11: larb@1582e000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1582e000 0 0x1000>; + /* larb11 uses larb9's clk */ + clocks =3D <&imgsys2_clk CLK_IMGSYS2_LARB9>, + <&imgsys2_clk CLK_IMGSYS2_LARB9>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_ISP_IMG2>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_img_2x1_sub_comm>; + }; + + vdec: video-codec@16000000 { + compatible =3D "mediatek,mt8189-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x16000000 0 0x26000>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + iommus =3D <&mm_iommu M4U_L4_P0_HW_VDEC_MC_EXT>; + mediatek,scp =3D <&scp>; + + vcodec_core: video-codec@16025000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + iommus =3D <&mm_iommu M4U_L4_P0_HW_VDEC_MC_EXT>, + <&mm_iommu M4U_L4_P1_HW_VDEC_UFO_EXT>, + <&mm_iommu M4U_L4_P2_HW_VDEC_PP_EXT>, + <&mm_iommu M4U_L4_P3_HW_VDEC_PRED_RD_EXT>, + <&mm_iommu M4U_L4_P4_HW_VDEC_PRED_WR_EXT>, + <&mm_iommu M4U_L4_P5_HW_VDEC_PPWRAP_EXT>, + <&mm_iommu M4U_L4_P6_HW_VDEC_TILE_EXT>, + <&mm_iommu M4U_L4_P7_HW_VDEC_VLD_EXT>, + <&mm_iommu M4U_L4_P8_HW_VDEC_VLD2_EXT>, + <&mm_iommu M4U_L4_P9_HW_VDEC_AVC_MV_EXT>, + <&mm_iommu M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT>, + <&mm_iommu M4U_L4_P11_HW_VDEC_UFO_ENC_EXT>; + interrupts =3D ; + clocks =3D <&vdec_core_clk CLK_VDEC_CORE_VDEC_CKEN>, + <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>; + clock-names =3D "soc-vdec", "vdec"; + assigned-clocks =3D <&topckgen_clk CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen_clk CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_VDE0>; + }; + }; + + smi_larb4: larb@1602e000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1602e000 0 0x1000>; + clocks =3D <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>, + <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_VDE0>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_disp_common>; + }; + + vdec_core_clk: syscon@1602f000 { + compatible =3D "mediatek,mt8189-vdec-core", "syscon"; + reg =3D <0 0x1602f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + venc_gcon_clk: syscon@17000000 { + compatible =3D "mediatek,mt8189-venc", "syscon"; + reg =3D <0 0x17000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + smi_larb7: larb@17010000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x17010000 0 0x1000>; + clocks =3D <&venc_gcon_clk CLK_VEN1_CKE0_LARB>, + <&venc_gcon_clk CLK_VEN1_CKE0_LARB>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_VEN0>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_disp_common>; + }; + + venc: video-codec@17020000 { + compatible =3D "mediatek,mt8189-vcodec-enc"; + reg =3D <0 0x17020000 0 0x6000>; + interrupts =3D ; + iommus =3D <&mm_iommu M4U_L7_P0_VENC_RCPU>, + <&mm_iommu M4U_L7_P1_VENC_REC>, + <&mm_iommu M4U_L7_P2_VENC_BSDMA>, + <&mm_iommu M4U_L7_P3_VENC_SV_COMV>, + <&mm_iommu M4U_L7_P4_VENC_RD_COMV>, + <&mm_iommu M4U_L7_P8_VENC_SUB_W_LUMA>, + <&mm_iommu M4U_L7_P10_VENC_CUR_LUMA>, + <&mm_iommu M4U_L7_P11_VENC_CUR_CHROMA>, + <&mm_iommu M4U_L7_P12_VENC_REF_LUMA>, + <&mm_iommu M4U_L7_P13_VENC_REF_CHROMA>, + <&mm_iommu M4U_L7_P14_VENC_SUB_R_LUMA>; + clocks =3D <&venc_gcon_clk CLK_VEN1_CKE1_VENC>; + clock-names =3D "venc_sel"; + assigned-clocks =3D <&topckgen_clk CLK_TOP_VENC_SEL>; + assigned-clock-parents =3D <&topckgen_clk CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_VEN0>; + mediatek,scp =3D <&scp>; + }; + + jpeg_encoder: jpeg-encoder@17030000 { + compatible =3D "mediatek,mt8189-jpgenc", "mediatek,mtk-jpgenc"; + reg =3D <0 0x17030000 0 0x10000>; + interrupts =3D ; + clocks =3D <&venc_gcon_clk CLK_VEN1_CKE2_JPGENC>; + clock-names =3D "jpgenc"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_VEN0>; + mediatek,larb =3D <&smi_larb7>; + iommus =3D <&mm_iommu M4U_L7_P5_JPGENC_Y_RDMA>, + <&mm_iommu M4U_L7_P6_JPGENC_C_RDMA>, + <&mm_iommu M4U_L7_P7_JPGENC_Q_RDMA>, + <&mm_iommu M4U_L7_P9_JPGENC_BSDMA>; + }; + + jpeg_decoder: jpeg-decoder@17040000 { + compatible =3D "mediatek,mt8189-jpgdec", "mediatek,mt2701-jpgdec"; + reg =3D <0 0x17040000 0 0x10000>; + interrupts =3D ; + clocks =3D <&venc_gcon_clk CLK_VEN1_CKE3_JPGDEC>; + clock-names =3D "jpgdec"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_VEN0>; + mediatek,larb =3D <&smi_larb7>; + iommus =3D <&mm_iommu M4U_L7_P15_JPGDEC_WDMA>, + <&mm_iommu M4U_L7_P16_JPGDEC_BSDMA>, + <&mm_iommu M4U_L7_P17_JPGDEC_HUFF_OFFSET>; + }; + + apu_iommu: iommu@19010000 { + compatible =3D "mediatek,mt8189-iommu-apu"; + reg =3D <0 0x19010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>; + clock-names =3D "bclk"; + #iommu-cells =3D <1>; + }; + + camsys_main_clk: syscon@1a000000 { + compatible =3D "mediatek,mt8189-camsys-main", "syscon"; + reg =3D <0 0x1a000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + smi_larb13: larb@1a001000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1a001000 0 0x1000>; + clocks =3D <&camsys_main_clk CLK_CAM_M_LARB13>, + <&camsys_main_clk CLK_CAM_M_LARB13>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_CAM_MAIN>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_cam_4x1_sub_comm>; + }; + + smi_larb14: larb@1a002000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1a002000 0 0x1000>; + clocks =3D <&camsys_main_clk CLK_CAM_M_LARB14>, + <&camsys_main_clk CLK_CAM_M_LARB14>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_CAM_MAIN>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_cam_3x1_sub_comm>; + }; + + smi_cam_3x1_sub_comm: smi@1a00c000 { + compatible =3D "mediatek,mt8189-smi-sub-common"; + reg =3D <0 0x1a00c000 0 0x1000>; + clocks =3D <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>, + <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_CAM_MAIN>; + mediatek,smi =3D <&smi_disp_common>; + }; + + smi_cam_4x1_sub_comm: smi@1a00d000 { + compatible =3D "mediatek,mt8189-smi-sub-common"; + reg =3D <0 0x1a00d000 0 0x1000>; + clocks =3D <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>, + <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_CAM_MAIN>; + mediatek,smi =3D <&smi_disp_common>; + }; + + smi_larb16: larb@1a00f000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1a00f000 0 0x1000>; + clocks =3D <&camsys_rawa_clk CLK_CAM_RA_CAMSYS_RAWA_LARBX>, + <&camsys_rawa_clk CLK_CAM_RA_CAMSYS_RAWA_LARBX>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_CAM_SUBA>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_cam_3x1_sub_comm>; + }; + + smi_larb17: larb@1a010000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1a010000 0 0x1000>; + clocks =3D <&camsys_rawb_clk CLK_CAM_RB_CAMSYS_RAWB_LARBX>, + <&camsys_rawb_clk CLK_CAM_RB_CAMSYS_RAWB_LARBX>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_CAM_SUBB>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_cam_4x1_sub_comm>; + }; + + camsys_rawa_clk: syscon@1a04f000 { + compatible =3D "mediatek,mt8189-camsys-rawa", "syscon"; + reg =3D <0 0x1a04f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawb_clk: syscon@1a06f000 { + compatible =3D "mediatek,mt8189-camsys-rawb", "syscon"; + reg =3D <0 0x1a06f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + ipesys_clk: syscon@1b000000 { + compatible =3D "mediatek,mt8189-ipesys", "syscon"; + reg =3D <0 0x1b000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + smi_ipe_2x1_sub_comm: smi@1b00e000 { + compatible =3D "mediatek,mt8189-smi-sub-common"; + reg =3D <0 0x1b00e000 0 0x1000>; + clocks =3D <&ipesys_clk CLK_IPE_SMI_SUBCOM>, + <&ipesys_clk CLK_IPESYS_GALS>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_ISP_IPE>; + mediatek,smi =3D <&smi_disp_common>; + }; + + smi_larb19: larb@1b10f000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1b10f000 0 0x1000>; + clocks =3D <&ipesys_clk CLK_IPE_LARB19>, + <&ipesys_clk CLK_IPE_LARB19>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_ISP_IPE>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_ipe_2x1_sub_comm>; + }; + + smi_larb20: larb@1b00f000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1b00f000 0 0x1000>; + clocks =3D <&ipesys_clk CLK_IPE_LARB20>, + <&ipesys_clk CLK_IPE_LARB20>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_ISP_IPE>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_ipe_2x1_sub_comm>; + }; + + vlpcfg_ao_reg_clk: syscon@1c000800 { + compatible =3D "mediatek,mt8189-vlp-ao", "syscon"; + reg =3D <0 0x1c000800 0 0x10>; + #clock-cells =3D <1>; + }; + + scpsys: syscon@1c001000 { + compatible =3D "mediatek,mt8189-scpsys", "syscon", "simple-mfd"; + reg =3D <0 0x1c001000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8189-power-controller"; + mfg0-supply =3D <&mt6359_vproc1_buck_reg>; + mfg1-supply =3D <&mt6359_vsram_proc1_ldo_reg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domain of the SoC */ + power-domain@MT8189_POWER_DOMAIN_CONN { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>; + clock-names =3D "audio"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_ADSP_AO { + reg =3D ; + clocks =3D <&vlp_cksys_clk CLK_VLP_CK_VADSP_SEL>; + clock-names =3D "vadsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_ADSP_INFRA { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_MM_INFRA { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_MMINFRA_SEL>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "mminfra", "ss-mminfra"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_ISP_IMG1 { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_IMG1_SEL>, + <&imgsys1_clk CLK_IMGSYS1_LARB9>, + <&imgsys1_clk CLK_IMGSYS1_LARB11>, + <&imgsys1_clk CLK_IMGSYS1_GALS>; + clock-names =3D "img1", "ss-img1-0", "ss-img1-1", "ss-img1-2"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_ISP_IMG2 { + reg =3D ; + clocks =3D <&imgsys2_clk CLK_IMGSYS2_LARB9>, + <&imgsys2_clk CLK_IMGSYS2_LARB11>, + <&imgsys2_clk CLK_IMGSYS2_GALS>; + clock-names =3D "ss-img2-0", "ss-img2-1", "ss-img2-2"; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_ISP_IPE { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_IPE_SEL>, + <&ipesys_clk CLK_IPE_LARB19>, + <&ipesys_clk CLK_IPE_LARB20>, + <&ipesys_clk CLK_IPE_SMI_SUBCOM>, + <&ipesys_clk CLK_IPESYS_GALS>; + clock-names =3D "ipe", "ss-ipe0", "ss-ipe1", "ss-ipe2", "ss-ipe3"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_VDE0 { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_VDEC_SEL>, + <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>; + clock-names =3D "vdec", "ss-vdec"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_VEN0 { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_VENC_SEL>, + <&venc_gcon_clk CLK_VEN1_CKE0_LARB>; + clock-names =3D "venc", "ss-venc"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_CAM_MAIN { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_CAM_SEL>, + <&camsys_main_clk CLK_CAM_M_LARB13>, + <&camsys_main_clk CLK_CAM_M_LARB14>, + <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>; + clock-names =3D "cam", "ss-cam0", "ss-cam1", "ss-cam2"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_CAM_SUBA { + reg =3D ; + clocks =3D <&camsys_rawa_clk CLK_CAM_RA_CAMSYS_RAWA_LARBX>; + clock-names =3D "ss-cam-suba"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_CAM_SUBB { + reg =3D ; + clocks =3D <&camsys_rawb_clk CLK_CAM_RB_CAMSYS_RAWB_LARBX>; + clock-names =3D "ss-cam-subb"; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_MDP0 { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_MDP0_SEL>, + <&mdpsys_config_clk CLK_MDP_SMI0>; + clock-names =3D "mdp", "ss-mdp"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_DISP { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_DISP0_SEL>, + <&dispsys_config_clk CLK_MM_SMI_LARB>; + clock-names =3D "disp", "ss-disp"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_DP_TX { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_EDP_TX_DORMANT { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_CSI_RX { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_SSUSB { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao_clk>; + #power-domain-cells =3D <0>; + }; + + mfg0: power-domain@MT8189_POWER_DOMAIN_MFG0 { + reg =3D ; + clocks =3D <&apmixedsys_clk CLK_APMIXED_MFGPLL>; + clock-names =3D "mfg_top"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + mfg1: power-domain@MT8189_POWER_DOMAIN_MFG1 { + reg =3D ; + clocks =3D <&topckgen_clk CLK_TOP_MFG_REF_SEL>; + clock-names =3D "mfg"; + mediatek,infracfg =3D <&infracfg_ao_clk>; + mediatek,smi =3D <&emicfg_ao_mem_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_MFG2 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8189_POWER_DOMAIN_MFG3 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_PCIE { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8189_POWER_DOMAIN_PCIE_PHY { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + + watchdog: watchdog@1c00a000 { + compatible =3D "mediatek,mt8188-wdt", "mediatek,mt6589-wdt"; + reg =3D <0 0x1c00a000 0 0x1000>; + #reset-cells =3D <1>; + }; + + vlpcfg_reg_bus_clk: syscon@1c00c000 { + compatible =3D "mediatek,mt8189-vlpcfg-ao", "syscon"; + reg =3D <0 0x1c00c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + dvfsrc_top_clk: syscon@1c00f000 { + compatible =3D "mediatek,mt8189-dvfsrc-top", "syscon"; + reg =3D <0 0x1c00f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vlp_cksys_clk: syscon@1c012000 { + compatible =3D "mediatek,mt8189-vlpckgen", "syscon"; + reg =3D <0 0x1c012000 0 0x1000>; + #clock-cells =3D <1>; + }; + + devapc_vlp: devapc@1c01c000 { + compatible =3D "mediatek,mt8189-devapc"; + reg =3D <0 0x1c01c000 0 0x1000>, + <0 0x1c018000 0 0x1000>; /* vlp ao/pd */ + vio-idx-num =3D <62>; + interrupts =3D ; /* vlp irq */ + }; + + sram@1c350000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x1c350000 0x0 0x80>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x1c350000 0x80>; + + scmi_tx_shmem: mailbox-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + }; + + tinysys_mbox: mailbox@1c351000 { + compatible =3D "mediatek,tinysys_mbox"; + reg =3D <0 0x1c351000 0 0x1000>, + <0 0x1c361000 0 0x1000>; + /* for profiling */ + shmem =3D <&scmi_tx_shmem>, <&scmi_rx_shmem>; + interrupts =3D , + ; + #mbox-cells =3D <1>; + /* notify spm clr */ + secure-sspm-md2spm-clr =3D <1>; + }; + + sram@1c360000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x1c360000 0x0 0x80>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x1c360000 0x80>; + + scmi_rx_shmem: mailbox-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + }; + + scp: scp@1c400000 { + compatible =3D "mediatek,mt8189-scp"; + reg =3D <0 0x1c400000 0 0x60000>, + <0 0x1cb20000 0 0xe0000>; + reg-names =3D "sram", "cfg"; + interrupts =3D ; + clocks =3D <&vlp_cksys_clk CLK_VLP_CK_SCP_SEL>; + clock-names =3D "scp_sel"; + status =3D "disabled"; + }; + + scp_iic_clk: syscon@1c80ae10 { + compatible =3D "mediatek,mt8189-scp-i2c-clk", "syscon"; + reg =3D <0 0x1c80ae10 0 0x10>; + #clock-cells =3D <1>; + }; + + scp_clk: syscon@1cb21150 { + compatible =3D "mediatek,mt8189-scp-clk", "syscon"; + reg =3D <0 0x1cb21150 0 0x10>; + #clock-cells =3D <1>; + }; + + pwrap: pwrap@1cc04000 { + compatible =3D "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "sysco= n"; + reg =3D <0 0x1cc04000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>, + <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>; + clock-names =3D "spi", "wrap"; + assigned-clocks =3D <&vlp_cksys_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen_clk CLK_TOP_OSC_D10>; + }; + + spmi: spmi@1cc06000 { + compatible =3D "mediatek,mt8189-spmi", "mediatek,mt8195-spmi"; + reg =3D <0 0x1cc06000 0 0x0008ff>, + <0 0x1cc00000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_P_SYS>, + <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_P_TMR>, + <&vlp_cksys_clk CLK_VLP_CK_SPMI_P_MST_SEL>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + systimer: timer@1cc10000 { + compatible =3D "mediatek,mt8189-timer","mediatek,mt6765-timer"; + reg =3D <0 0x1cc10000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk13m>; + }; + + vadsys_clk: syscon@1e010000 { + compatible =3D "mediatek,mt8189-vadsys", "syscon"; + reg =3D <0 0x1e010000 0 0x1000>; + #clock-cells =3D <1>; + }; + + devapc_adsp: devapc@1e019000 { + compatible =3D "mediatek,mt8189-devapc"; + reg =3D <0 0x1e019000 0 0x1000>, + <0 0x1e340000 0 0x1000>; /* adsp ao/pd */ + vio-idx-num =3D <44>; + interrupts =3D ; /* adsp irq */ + status =3D "disabled"; + }; + + mminfra { + compatible =3D "mediatek,mt8189-mminfra"; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_GCE_D>, + <&mminfra_config_clk CLK_MMINFRA_GCE_M>, + <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; + clock-names =3D "gce_d", "gce_m", "gce_26m"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + mediatek,mminfra =3D <&mminfra_config_clk>; + }; + + mminfra_config_clk: syscon@1e800000 { + compatible =3D "mediatek,mt8189-mm-infra", "syscon"; + reg =3D <0 0x1e800000 0 0x1000>; + #clock-cells =3D <1>; + }; + + smi_disp_common: smi@1e801000 { + compatible =3D "mediatek,mt8189-smi-common"; + reg =3D <0 0x1e801000 0 0x1000>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_SMI>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; + + mm_iommu: iommu@1e802000 { + compatible =3D "mediatek,mt8189-iommu-mm"; + reg =3D <0 0x1e802000 0 0x5000>; + interrupts =3D ; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "bclk"; + #iommu-cells =3D <1>; + mediatek,larbs =3D <&smi_larb0 &smi_larb1 &smi_larb2 &smi_larb4 &smi_la= rb7 + &smi_larb9 &smi_larb11 &smi_larb13 &smi_larb14 + &smi_larb16 &smi_larb17 &smi_larb19 &smi_larb20>; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; + + disp_ssc0_smi_2x1_sub_comm: smi@1e807000 { + compatible =3D "mediatek,mt8189-smi-common"; + reg =3D <0 0x1e807000 0 0x1000>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_SMI>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; + + disp_ssc1_smi_2x1_sub_comm: smi@1e808000 { + compatible =3D "mediatek,mt8189-smi-common"; + reg =3D <0 0x1e808000 0 0x1000>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_SMI>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; + + mminfra_smi_3x1_sub_comm: smi@1e809000 { + compatible =3D "mediatek,mt8189-smi-sub-common"; + reg =3D <0 0x1e809000 0 0x1000>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_SMI>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + mediatek,smi =3D <&smi_disp_common>; + }; + + mminfra_smi_2x1_sub_comm: smi@1e80a000 { + compatible =3D "mediatek,mt8189-smi-sub-common"; + reg =3D <0 0x1e80a000 0 0x1000>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_SMI>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + mediatek,smi =3D <&smi_disp_common>; + }; + + devapc_mminfra: devapc@1e826000 { + compatible =3D "mediatek,mt8189-devapc"; + reg =3D <0 0x1e826000 0 0x1000>, + <0 0x1e820000 0 0x1000>; /* mminfra ao/pd */ + vio-idx-num =3D <304>; + interrupts =3D ; /* mminfra irq */ + }; + + gce: gce@1e980000 { + compatible =3D "mediatek,mt8189-gce"; + reg =3D <0 0x1e980000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <2>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_GCE_D>, + <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; + clock-names =3D "gce0", "gce-timer"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; + + gce_d_clk: syscon@1e9800f0 { + compatible =3D "mediatek,mt8189-gce-d", "syscon"; + reg =3D <0 0x1e9800f0 0 0x1000>; + #clock-cells =3D <1>; + }; + + gce_m: gce@1e990000 { + compatible =3D "mediatek,mt8189-gce"; + reg =3D <0 0x1e990000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <2>; + clocks =3D <&mminfra_config_clk CLK_MMINFRA_GCE_M>, + <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; + clock-names =3D "gce1", "gce-timer"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MM_INFRA>; + }; + + gce_m_clk: syscon@1e9900f0 { + compatible =3D "mediatek,mt8189-gce-m", "syscon"; + reg =3D <0 0x1e9900f0 0 0x1000>; + #clock-cells =3D <1>; + }; + + mdpsys_config_clk: syscon@1f000100 { + compatible =3D "mediatek,mt8189-mdpsys", "syscon"; + reg =3D <0 0x1f000100 0 0x20>; + #clock-cells =3D <1>; + }; + + smi_larb2: larb@1f002000 { + compatible =3D "mediatek,mt8189-smi-larb"; + reg =3D <0 0x1f002000 0 0x1000>; + clocks =3D <&mdpsys_config_clk CLK_MDP_SMI0>, + <&mdpsys_config_clk CLK_MDP_SMI0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8189_POWER_DOMAIN_MDP0>; + mediatek,larb-id =3D ; + mediatek,smi =3D <&smi_disp_common>; + }; + + thermal_zones: thermal-zones { + + cpu0-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_BIG_CPU1>; + sustainable-power =3D <1200>; + trips { + cpu0_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_crit: trip-crit { + temperature =3D <115000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1024>; + }; + + }; + }; + + cpu1-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_BIG_CPU2>; + sustainable-power =3D <1200>; + trips { + cpu1_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1024>; + }; + }; + }; + + cpu2-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_BIG_CPU3>; + sustainable-power =3D <1200>; + trips { + cpu2_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1024>; + }; + }; + }; + + cpu3-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_BIG_CPU4>; + sustainable-power =3D <1200>; + trips { + cpu3_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1024>; + }; + }; + }; + + cpu4-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU1>; + sustainable-power =3D <1200>; + trips { + cpu4_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu4_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu4_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu4_alert>; + cooling-device =3D + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1024>; + }; + }; + }; + + cpu5-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU2>; + sustainable-power =3D <1200>; + trips { + cpu5_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu5_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu5_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu5_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + cpu6-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU3>; + sustainable-power =3D <1200>; + trips { + cpu6_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu6_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu6_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu6_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + cpu7-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU4>; + sustainable-power =3D <1200>; + trips { + cpu7_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu7_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu7_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu7_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + cpu8-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU5>; + sustainable-power =3D <1200>; + trips { + cpu8_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu8_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu8_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu8_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + cpu9-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU6>; + sustainable-power =3D <1200>; + trips { + cpu_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu9_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu9_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu9_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + cpu10-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU7>; + sustainable-power =3D <1200>; + trips { + cpu10_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu10_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu10_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu10_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + cpu11-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_mcu MT8189_MCU_LITTLE_CPU8>; + sustainable-power =3D <1200>; + trips { + cpu11_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu11_alert: target@1 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu11_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu11_alert>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <2345>; + }; + }; + }; + + soc1-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_ap MT8189_AP_SOC1>; + sustainable-power =3D <1200>; + trips { + soc1_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc1_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc1_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + soc2-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_ap MT8189_AP_SOC2>; + sustainable-power =3D <1200>; + trips { + soc2_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc2_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc2_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + soc3-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_ap MT8189_AP_SOC3>; + sustainable-power =3D <1200>; + trips { + soc3_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc3_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc3_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + apu-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_ap MT8189_AP_APU>; + sustainable-power =3D <1200>; + trips { + apu_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + apu_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + apu_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_ap MT8189_AP_GPU1>; + sustainable-power =3D <1200>; + trips { + gpu1_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu1_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu1_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&gpu1_alert>; + cooling-device =3D + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1134>; + }; + }; + }; + + gpu2-thermal { + polling-delay =3D <200>; /* milliseconds */ + polling-delay-passive =3D <100>; /* milliseconds */ + thermal-sensors =3D <&lvts_ap MT8189_AP_GPU2>; + sustainable-power =3D <1200>; + trips { + gpu2_threshold: trip-point@0 { + temperature =3D <68000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu2_alert: target@1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu2_crit: trip-crit { + temperature =3D <119000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&gpu2_alert>; + cooling-device =3D + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution =3D <1134>; + }; + }; + }; + }; + + emiisu { + compatible =3D "mediatek,common-emiisu"; + ctrl-intf =3D <1>; + }; + }; +}; --=20 2.45.2